CN117910256A - Yield analysis method based on Gaussian process substitution model - Google Patents
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Abstract
The invention discloses a yield analysis method based on a Gaussian process substitution model, which adopts Latin hypercube sampling to select initial sample points; training a depth Gaussian process model; solving the super parameters of the Gaussian process model through Gibbs sampling to obtain a low-precision depth Gaussian process model; and selecting a proper sample from the sample space by utilizing active learning, adding the sample into a model training set, and training the model to obtain a high-precision depth Gaussian process model. The method can be used for rapidly analyzing and obtaining the electric Lu Liang rate under the scene of high dimension and high yield, and the yield analysis precision reaches a higher level. The superposition of a plurality of Gaussian processes enables the network to obtain strong nonlinear processing capacity, a good effect can be obtained in a high-dimensional parameter space, the acceptance rate of samples is improved by Gibbs sampling, and the solving efficiency is improved. When the active learning is utilized to acquire the sample points, the sample points are enabled to meet the requirement of model training, and convergence of model accuracy is quickened.
Description
Technical Field
The invention relates to the technical research field of integrated circuit design, in particular to a yield analysis method based on a Gaussian process substitution model.
Background
With the rapid development of the chip manufacturing industry, the semiconductor industry has been following the pace of moore's law, with MOS transistors having been scaled down to the nanometer level, and devices having been smaller and smaller, meaning that more transistors can be integrated on the same area of chip. The following problems are that the influence of process parameter fluctuation in the chip manufacturing process on the circuit performance is more and more severe, and the fluctuation of the transistor electrical characteristics can be caused, so that the circuit performance is fluctuated, the circuit is caused to be faulty, and the yield of the circuit is reduced. The current yield analysis has mainly the following challenges: under the extremely high yield requirement, the difficulty of acquiring a failure sample point is increased, and the simulation times are extremely high; different circuits may have a plurality of different failure areas, and failure areas are easily missed in the analysis process, so that the error of the yield analysis result is increased; the increase in circuit dimensions makes yield analysis more difficult.
Monte Carlo (MC) based methods are directed to randomly extracting samples from a joint probability density function characterizing process deviations of circuit parameters, and performing transistor level simulation on each extracted sample to evaluate circuit performance output values of the circuit under the random samples, but MC methods rely on an extremely high number of sample points to achieve a reliable accuracy. The method based on the device model process corner analysis sets the fast/slow model parameters of the device in various extreme cases to obtain the worst performance of the circuit. Compared with the MC method, the method reduces the simulation times, has high use frequency in the simulation circuit design, and can quickly give out the optimized iteration aiming at the circuit design optimized worker result, but the method has the defects that the statistical distribution of the performance cannot be given, and the failure area is not necessarily in the process angle range. The importance sampling method improves the sampling strategy of MC, the main idea is to transfer the original probability density function distribution to the area more likely to fail by using an offset vector, so that most of samples obtained from the optimal sampling distribution fall in the failure area, the speed of yield evaluation is improved, but the importance sampling method may miss important failure area, and the yield analysis result is inaccurate. The method is characterized in that the distribution and the yield of the circuit output performance are estimated by adopting an approximate model based on a substitution model method, the substitution model established through circuit simulation reflects the mapping relation between the circuit performance and the technological parameter fluctuation, the technological parameter space is mapped to the circuit performance space, a mathematical model is trained to replace the circuit simulation, but the accuracy of the substitution model in estimating the yield is extremely dependent on the condition of the substitution model establishment, and a large number of samples are required for establishing a sufficiently accurate substitution model, so that the problem is particularly prominent in a high-dimensional circuit scene.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a yield analysis method based on a gaussian process substitution model capable of rapidly calculating the failure probability of a circuit in a high yield and high dimensional scenario.
A yield analysis method based on a gaussian process substitution model, the method comprising the steps of:
The method comprises the following steps:
Step one, selecting an initial sample point by using Latin hypercube sampling;
step two, taking the depth Gaussian process model as a substitute model to perform model training;
Thirdly, solving the super parameters of the Gaussian process model through Gibbs sampling to obtain a low-precision depth Gaussian process model;
step four, selecting a proper sample from a sample space by utilizing active learning, adding the sample into a model training set, and training a low-precision depth Gaussian process model to obtain a high-precision depth Gaussian process model;
step five, judging whether the precision of the depth Gaussian process model meets the standard, and turning to step four if the precision of the depth Gaussian process model does not meet the standard; and if the analysis result reaches the standard, outputting an analysis result of the electric Lu Liang rate.
Preferably, the selecting the initial sample point by using Latin hypercube sampling in the first step includes the following specific steps:
step 1-1, dividing each dimension of the whole vector space into a plurality of cells which are not overlapped with each other, so that each cell has the same probability;
step 1-2, randomly sampling in each interval of each dimension;
Step 1-3, randomly extracting selected sample points from each dimension.
Preferably, the depth gaussian process model in the second step is a combination of a convolutional neural network and a gaussian process, the gaussian process is used for replacing a full-connection layer in the convolutional neural network, and an input layer, an output layer, a convolutional layer and a pooling layer in the convolutional neural network are reserved; the depth Gaussian process model is formed by overlapping a plurality of layers of Gaussian process models, different layers are connected with each other, and the output of the upper layer serves as the input of the lower layer.
Preferably, a variance formula of the circuit system fault is defined by taking a depth gaussian process model as a substitute model, as shown in the formula (1):
（1）；
Where Var (P fail) is the circuit system fault variance, P fail is the probability of circuit failure, N is the number of samples, H is the approximate indication function, and c is the expected E (H) of the H function.
Preferably, in the step of selecting a suitable sample from the sample space in the step four, the suitable sample includes:
sample one, the candidate point that minimizes the system fault variance; extracting candidate points which minimize the system fault variance, wherein the candidate points are shown in the formula (2):
（2）；
Where c is the expected E (H) that approximately indicates the function H, x is the candidate point where the system fault variance is the smallest.
Sample two, confidence interval of variance formula of circuit system fault; since the variance formula of the circuit system fault is a random variable, the confidence interval of the 1-alpha level is shown as (3):
（3）；
wherein, For/>The formula (4) can be obtained:
（4）；
wherein, Is the minimum error.
Preferably, the judging condition for judging whether the accuracy of the depth gaussian process model in the fifth step meets the standard is as follows:
According to the set minimum error At each iteration, by calculation/>And/>Obtain/>And (3) judging whether the formula (4) is satisfied, if not, continuing to execute the step four, and if so, stopping active learning.
Preferably, the analysis result of the electric Lu Liang rate in the fifth step is as shown in formula (5):
（5）；
Wherein P fail is the probability of circuit failure.
According to the yield analysis method based on the Gaussian process substitution model, the electric Lu Liang rate can be obtained through rapid analysis under the scene of high dimension and high yield, the yield analysis precision reaches a higher level, and the selected depth Gaussian process model enables the network to obtain strong nonlinear processing capacity through superposition of a plurality of Gaussian processes, and can also obtain a better effect in a high dimension parameter space. And gibbs sampling is added in model solving, so that the acceptance rate of samples is improved to a great extent, and the solving efficiency is greatly improved. When the active learning is utilized to acquire the sample points, besides the sample points close to the failure boundary, the condition for minimizing the system fault variance is added, so that the sample points more meet the requirement of model training, and the convergence of model accuracy is quickened. The method is simple, and the convergence rate of the depth Gaussian process model is effectively improved.
Drawings
FIG. 1 is a flow chart of a yield analysis method based on a Gaussian process substitution model in an embodiment of the invention.
FIG. 2 is a block diagram of a 6T-SRAM cell circuit of embodiment 1 of the present invention.
Fig. 3 is a circuit configuration diagram of a two-stage transconductance operational amplifier according to embodiment 2 of the present invention.
Detailed Description
In this embodiment, a yield analysis method based on a gaussian process substitution model is taken as an example, and the present invention will be described in detail with reference to specific embodiments and drawings.
Referring to fig. 1, a yield analysis method based on a gaussian process substitution model according to an embodiment of the present invention is shown, and the method includes the following steps:
step S10, selecting an initial sample point by using Latin hypercube sampling.
Step S11, each dimension of the whole vector space is divided into a plurality of cells which are not overlapped with each other, so that each cell has the same probability.
Step S12, randomly sampling in each interval of each dimension.
Step S13, randomly extracting selected sample points from each dimension.
Specifically, the Latin hypercube sampling method can ensure that samples are distributed according to proportion in each uniform interval, and avoid excessive concentration of selected samples. Initial sample points of a training Gaussian process model can be obtained through Latin hypercube sampling, and then the reconstruction of input distribution is accurately carried out through sampling with fewer iteration times.
And step S20, taking the depth Gaussian process model as a substitute model to perform model training.
Specifically, the deep Gaussian process model is a combination of a convolutional neural network and a Gaussian process, the Gaussian process is used for replacing a full-connection layer in the convolutional neural network, and an input layer, an output layer, a convolutional layer and a pooling layer in the convolutional neural network are reserved; the depth Gaussian process model is formed by overlapping a plurality of layers of Gaussian process models, different layers are connected with each other, and the output of the upper layer serves as the input of the lower layer.
Specifically, in the present embodiment, the depth gaussian process model (Deep Gaussian Process, DGP) is stacked from 3 layers of gaussian process models, thereby forming a depth model. The Gaussian process model is an algorithm based on transfer learning, which can be understood as taking historical data as source data and new task data as target data, and by designing an objective function, the relation between the source data and the target data is established, and the model based on the source data learning is calibrated by utilizing the target data. In practical applications, different depth gaussian process models are to be built according to different operator types, for example, direct convolution, depth separation convolution and full connection correspond to different depth gaussian process models respectively.
Specifically, the convolutional neural network (Convolutional Neural Networks, CNN) generally includes an input layer, a convolutional layer, a pooling layer, a fully connected layer and an output layer, in this embodiment, the fully connected layer is replaced by a gaussian process, the convolutional layer is used for extracting features of input data to preserve feature quantities of the input data, the pooling layer is used for performing feature selection and information filtering to reduce data dimension, the gaussian process is used for predicting output of an object, and an analog simulation value of a sample point is calculated by analyzing the sample point obtained by the latin hypercube sampling, and is taken as an output value.
Step S21, a variance formula of the circuit system fault is defined by taking the depth Gaussian process model as a substitution model, and the variance formula is shown as a formula (1):
（1）；
Where Var (P fail) is the circuit system fault variance, P fail is the probability of circuit failure, N is the number of samples, H is the approximate indication function, and c is the expected E (H) of the H function.
And step S30, solving the super parameters of the Gaussian process model through Gibbs sampling to obtain a low-precision depth Gaussian process model.
Specifically, the sample points selected from the initial sample points are sampled by gibbs, so that the acceptance rate of the samples can be improved, the solving efficiency of the super parameters can be improved, and the convergence of the model accuracy can be accelerated.
And S40, selecting a proper sample from a sample space by utilizing active learning, adding the sample into a model training set, and training a low-precision deep Gaussian process model to obtain the high-precision deep Gaussian process model.
Specifically, suitable samples include:
sample one, the candidate point that minimizes the system fault variance; extracting candidate points which minimize the system fault variance, wherein the candidate points are shown in the formula (2):
（2）；
Where c is the expected E (H) that approximately indicates the function H, x is the candidate point where the system fault variance is the smallest.
Specifically, candidate pointsA set of x corresponding to the maximum value is obtained for the function f (x).
Sample two, confidence interval of variance formula of circuit system fault; since the variance formula of the circuit system fault is a random variable, the confidence interval of the 1-alpha level is shown as (3):
（3）；
wherein, For/>The formula (4) can be obtained:
（4）；
wherein, Is the minimum error.
Step S50, judging whether the precision of the depth Gaussian process model meets the standard, and if the precision does not meet the standard, turning to step S40; and if the analysis result reaches the standard, outputting an analysis result of the electric Lu Liang rate.
Step S51, according to the set minimum errorAt each iteration, by calculation/>And/>ObtainingWhether the expression (4) is satisfied is determined, and if not, the step four is continued, and if satisfied, the process proceeds to step S52.
Step S52, outputting the analysis result of the electrical Lu Liang rate, as shown in equation (5):
（5）；
Wherein P fail is the probability of circuit failure.
Example 1: yield analysis was performed on 6T-SRAM bitcells with 36 variables.
To demonstrate the efficiency of the present invention, several additional computational methods were employed, including hyperspherical clustering and sampling (HSCS) and Adaptive Importance Sampling (AIS). The SPICE model is a central core international 40nm transistor model. All experiments were performed on a Linux server with Intel Xeon X5675 CPU@3.07.
A schematic diagram of a typical 6T SRAM bit cell is shown in fig. 2. The four transistors MP1, MN2, MP3, and MN4 form two cross-coupled inverters and use two steady states ("0" or "1") to store data in this cell. The other two transistors MN5 and MN6 function as switches to control access to the memory cell during read, write and standby operations.
Taking a read failure as an example, a read failure occurs when the voltage difference between BL and BLB is too small to be captured by the sense amplifier for a certain period of time. The performance of the circuit is characterized by a delay in the discharge of the bit line that should be less than a given threshold for read success. The circuit selects 36-dimensional input process parameters, takes read delay as output performance, and adopts different yield analysis methods to embody the accuracy and efficiency of the invention. The experimental results are shown in the following table:
Example 2: yield analysis was performed on a two-stage transconductance operational amplifier with 84 variables.
To demonstrate the efficiency of the present invention, several most advanced methods have additionally been implemented, including hypersphere clustering and sampling (HSCS) and Adaptive Importance Sampling (AIS). The SPICE model is a central core international 40nm transistor model. All experiments were performed on a Linux server with Intel Xeon X5675 CPU@3.07.
This embodiment verifies that the proposed method is capable of handling problems on analog circuits with multiple performance indicators. Fig. 3 shows a circuit schematic of a two-stage transconductance operational amplifier (OTA) for low supply voltage applications using a master-slave architecture. The slave stage consists of a tail current transistor (MP 5), a differential pair (MP 1 and MP 2) and current mirror loads (MN 1 and MN 2). The master replicates the tail current sources and transconductance transistors of the slave circuits (i.e., MP3, MP4, MP6, and MN3 are copies of MP1, MP2, MP5, and MN1, respectively). MP5 and MP6 operate in the linear region to save voltage margin. The robust OTA design should meet the requirements of multiple specifications. In this experimental setup, various performance specifications were considered, including voltage gain margin, gain bandwidth, phase margin, and 3dB bandwidth. In this case, there are a total of 84 variation parameters. The experimental results are shown in the following table:
| Method of | MC | AIS | HSCS | Our Work |
| Failure rate of | 4.3e-3 | 3.78e-3 | 3.1e-3 | 4.1e-3 |
| Relative error | golden | 12% | 30% | 4.1% |
| Number of simulations | 300000 | 58667 | 11682 | 3122 |
Yield analysis is carried out on the SRAM unit, and the simulation times of the MC method reachThe method can reach 98.5% of precision by only 700 times of simulation, the yield analysis is carried out on the two-stage transconductance operational amplifier, the simulation times of the MC method reach 30 ten thousand times, and the method can reach 95.9% of precision by only 3122 times of simulation.
According to the yield analysis method based on the Gaussian process substitution model, the electric Lu Liang rate can be obtained through rapid analysis under the scene of high dimension and high yield, the yield analysis precision reaches a higher level, and the selected depth Gaussian process model enables the network to obtain strong nonlinear processing capacity through superposition of a plurality of Gaussian processes, and can also obtain a better effect in a high dimension parameter space. And gibbs sampling is added in model solving, so that the acceptance rate of samples is improved to a great extent, and the solving efficiency is greatly improved. When the active learning is utilized to acquire the sample points, besides the sample points close to the failure boundary, the condition for minimizing the system fault variance is added, so that the sample points more meet the requirement of model training, and the convergence of model accuracy is quickened. The method is simple, and the convergence rate of the depth Gaussian process model is effectively improved.
It should be noted that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the present invention, but various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A yield analysis method based on a gaussian process substitution model, the method comprising the steps of:
Step one, selecting an initial sample point by using Latin hypercube sampling;
step two, taking the depth Gaussian process model as a substitute model to perform model training;
Thirdly, solving the super parameters of the Gaussian process model through Gibbs sampling to obtain a low-precision depth Gaussian process model;
step four, selecting a proper sample from a sample space by utilizing active learning, adding the sample into a model training set, and training a low-precision depth Gaussian process model to obtain a high-precision depth Gaussian process model;
step five, judging whether the precision of the depth Gaussian process model meets the standard, and turning to step four if the precision of the depth Gaussian process model does not meet the standard; and if the analysis result reaches the standard, outputting an analysis result of the electric Lu Liang rate.
2. The method for analyzing yield based on the gaussian process substitution model according to claim 1, wherein said selecting an initial sample point using latin hypercube in step one comprises the following steps:
step 1-1, dividing each dimension of the whole vector space into a plurality of cells which are not overlapped with each other, so that each cell has the same probability;
step 1-2, randomly sampling in each interval of each dimension;
Step 1-3, randomly extracting selected sample points from each dimension.
3. The method for analyzing the yield based on the Gaussian process substitution model according to claim 1, wherein the deep Gaussian process model in the second step is a combination of a convolutional neural network and a Gaussian process, the Gaussian process is used for replacing a full connection layer in the convolutional neural network, and an input layer, an output layer, a convolutional layer and a pooling layer in the convolutional neural network are reserved; the depth Gaussian process model is formed by overlapping a plurality of layers of Gaussian process models, different layers are connected with each other, and the output of the upper layer serves as the input of the lower layer.
4. The method for analyzing yield based on a gaussian process substitution model according to claim 3, wherein a variance formula of a circuit system fault is defined by taking a depth gaussian process model as a substitution model, as shown in formula (1):
（1）；
Where Var (P fail) is the circuit system fault variance, P fail is the probability of circuit failure, N is the number of samples, H is the approximate indication function, and c is the expected E (H) of the H function.
5. The method for analyzing yield based on a gaussian process substitution model according to claim 4, wherein said step four of selecting a suitable sample from a sample space to be added to a training set of models comprises:
sample one, the candidate point that minimizes the system fault variance; extracting candidate points which minimize the system fault variance, wherein the candidate points are shown in the formula (2):
（2）；
Where c is the expected E (H) that approximately indicates the function H, x is the candidate point where the system fault variance is the smallest.
Sample two, confidence interval of variance formula of circuit system fault; since the variance formula of the circuit system fault is a random variable, the confidence interval of the 1-alpha level is shown as (3):
（3）；
wherein, For/>The formula (4) can be obtained:
（4）；
wherein, Is the minimum error.
6. The method for analyzing yield based on gaussian process substitution model according to claim 1, wherein the judgment condition for judging whether the accuracy of the depth gaussian process model in the fifth step is up to standard is:
According to the set minimum error At each iteration, by calculation/>And/>Obtain/>And (3) judging whether the formula (4) is satisfied, if not, continuing to execute the step four, and if so, stopping active learning.
7. The method for analyzing yield based on the gaussian process substitution model according to claim 1, wherein the analysis result of the electric Lu Liang rate in the fifth step is as shown in the formula (5):
（5）；
Wherein P fail is the probability of circuit failure.
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