CN117907798A - Integrated circuit testing method, detection device, driving chip and controller - Google Patents

Abstract

The invention belongs to the technical field of power electronics, and particularly relates to an integrated circuit testing method, a detection device, a driving chip and a controller; the first measuring point partitioning step/unit is to set a test point array (920) in a conductor connection area between a gate driving circuit (910) and a driving tube circuit (930) of a chip (999) to be detected and obtain a driving tube gate signal set; the second grid detection step/unit compares the difference between the grid signal set of the driving tube and a preset standard signal and marks an abnormal signal on a corresponding failure position array, so that a corresponding driving tube circuit (930) is determined and used as a target circuit of failure analysis FA (Failure Analysis), and the detection process insensitive to the electrical characteristics is avoided; the third inter-pole detection step/unit and the fourth photoelectric positioning step/unit are combined with the electrical verification process and the processes of the laser beam induced resistance change OBIRCH (Optical Beam Induced RESISTANCE CHANGE), the micro light microscope EMMI (Emission Microscope) and the like, so that the accurate positioning scheme of the FA process is further improved.

Description

Integrated circuit testing method, detection device, driving chip and controller

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to an integrated circuit testing method, a detection device, a driving chip and a controller.

Background

The failure analysis FA (Failure Analysis) of the integrated circuit IC (Integrated Circuit) has wide application, and can identify or position obvious anomalies such as short circuit, open circuit, electric leakage and the like through the detection of a pin current-voltage curve IVC (I-V Curve); the process may also be specifically developed through failure physics analysis PFA (Physical Failure Analysis).

However, when the current-voltage curve IVC of the IC pin is normal and the IC has no output or the waveform of the IC output is abnormal, the positioning process (including the laser beam induced resistance change OBIRCH (Optical Beam Induced RESISTANCE CHANGE), the micro light microscope EMMI (Emission Microscope), and other technical means) cannot capture obvious abnormal symptoms (such as hot spots or light spots), then further analysis of the internal circuit structure of the IC is required to reduce the fault range or give an improvement suggestion.

Disclosure of Invention

The embodiment of the invention discloses an integrated circuit testing method, which comprises a first measuring point partitioning step and a second grid electrode detecting step; the first measuring point partitioning step is to set a test point array PAD in a conductor connection area between a to-be-detected chip grid driving circuit and a driving tube circuit, wherein the test point array PAD is used for collecting characteristic signals, and the characteristic signals form a driving tube grid signal set.

Further, the second gate detection step compares the difference between the driving tube gate signal set and the preset standard signal, marks the abnormal signal on the failure position array corresponding to the test point array PAD, and uses the driving tube circuit corresponding to the failure position array as a target circuit for further failure analysis.

The first measuring point partitioning step can be provided with a first one-to-one electrical verification step; the first one-to-one electrical verification step obtains a current circuit parameter set of a preset measurement port of a chip to be detected, and judges the failure situation by comparing the difference between the current circuit parameter set and a typical parameter set; if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, the corresponding circuit or chip area is considered to have a failure structure or failure risk.

Specifically, the first one-to-one electrical verification step is performed in a lossless manner or the first one-to-one electrical verification step does not invade a designated area and/or an internal area of the chip package structure to be inspected.

Wherein, the test point array PAD can be constructed by adopting a focused ion beam FIB; the test point array PAD is directed via a microprobe MicroProbe to a predetermined detection device and/or probe contact, which may be a voltage detection device and/or a current detection device.

Further, the integrated circuit testing method may further be provided with a third inter-electrode detection step; the third inter-pole detection step is to obtain target current/voltage data or a target curve between a grid electrode and a source electrode/drain electrode of a driving tube in a target circuit; comparing the target current data, the target voltage data and/or the target curve, and judging a failure area in the target circuit; the target curve comprises a voltage-current relation curve I-Vcurve.

The third inter-electrode detection step can be further provided with a third electrical verification step, and the third electrical verification step can also obtain a current circuit parameter set of a preset measurement port of the chip to be detected and compare the difference between the current circuit parameter set and a typical parameter set; and if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, considering that a corresponding circuit or chip area has a failure structure or failure risk.

Further, the integrated circuit testing method may further be provided with a fourth photo-positioning step; and a fourth photoelectric positioning step, namely detecting the target circuit through the laser beam induced resistance change OBIRCH and/or the micro light microscope EMMI, and if the calorific value and/or the light spot parameter of the target circuit exceed the safety threshold, determining that a failure structure or a failure risk exists in the corresponding area.

In particular, the fourth electro-optical positioning step thereof may be further provided with at least one of a delamination/dicing process, an optical inspection process and/or a scanning electron microscopy process; its second gate detection step may also be provided with a physical analysis PFA process/step.

Specifically, the driving tube circuit thereof may be a motor driving circuit; the motor driving circuit can adopt a bridge driving structure; the first measuring point partitioning step and the second grid electrode detecting step can be executed when the chip to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise a plurality of situations such as locked rotor, overvoltage of a power end, power peak, power short circuit and the like.

The motor driving circuit comprises an integrated circuit used in any chip of a brush direct current motor driving circuit BDC, a brushless direct current motor driving circuit BLDC, a stepping motor driving circuit Stepper and/or a permanent magnet motor driving circuit PMSM.

Specifically, the chip to be detected in the integrated circuit testing method may be provided with a diagnosis/protection circuit and/or a control logic circuit; the first rated working current and the first rated working voltage of the diagnosis/protection circuit and the control logic circuit are respectively smaller than a preset current threshold value and a preset voltage threshold value; the second rated working current of the driving tube circuit is N times greater than the first rated working current, the second rated working voltage of the driving tube circuit is M times greater than the first rated working voltage, and M, N is a preset positive integer; the chip to be detected can adopt an NMOS driving tube and/or a PMOS driving tube.

Correspondingly, the embodiment of the invention also discloses a detection device, and the core of the detection device also comprises a first measuring point partition unit and a second grid detection unit; the first measuring point partition unit is used for arranging a test point array PAD in a conductor connection area between a grid driving circuit and a driving tube circuit of a chip to be detected, wherein the test point array PAD is also used for collecting characteristic signals, and the characteristic signals form a grid signal set of the driving tube; the second grid detection unit compares the difference between the grid signal set of the driving tube and a preset standard signal, marks an abnormal signal on a failure position array corresponding to the test point array PAD, and takes a driving tube circuit corresponding to the failure position array as a target circuit needing further failure analysis.

Further, the first measuring point partition unit can be further provided with an electrical verification unit; the electrical verification unit acquires a current circuit parameter set of a preset measurement port of a chip to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, the corresponding circuit or chip area is considered to have a failure structure or failure risk.

The electrical verification unit can be performed in a sampling nondestructive mode or can avoid invading a designated area and/or an internal area of the chip packaging structure to be detected; the test point array PAD can also be constructed by adopting a focused ion beam FIB; the test point array PAD may be led to a predetermined detection device and/or probe tip via a microprobe MicroProbe, which detection device may be a voltage detection device and/or a current detection device.

Further, the detection device may further be provided with a third inter-pole detection unit for acquiring target current/voltage data or a target curve between the gate and the source/drain of the driving tube in the target circuit; judging a failure area in the target circuit by comparing the target current data, the target voltage data and/or the target curve; the target curve comprises a voltage-current relation curve I-Vcurve; the third inter-pole detection unit further comprises the above-mentioned electrical verification unit, and the action mechanism is not repeated.

Further, the detection device may be further provided with a fourth photo-positioning unit; the target circuit may be detected by a laser beam induced resistance change OBIRCH and/or a micro light microscope EMMI, and if the calorific value and/or the light spot parameter of the target circuit exceeds a safety threshold, it is determined that a failure structure or a failure risk exists in the corresponding area.

In addition, the fourth electro-optic positioning unit may also pass at least one of a delamination/dicing process, an optical inspection process, and/or a scanning electron microscopy process; the second gate detection unit can also perform accurate positioning of the failure position by physically analyzing the PFA.

Specifically, the driving tube circuit thereof may be a motor driving circuit; the motor driving circuit can adopt a bridge driving structure; the first measuring point partition unit and the second grid detection unit can be executed when the chip to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise locked rotor, overvoltage of a power end, power peak and power short circuit; the motor drive circuits may be brush direct current motor drive circuit BDC, brushless direct current motor drive circuit BLDC, stepper motor drive circuit Stepper and/or permanent magnet motor drive circuit PMSM.

Further, the chip to be detected of the detection device can be further provided with a diagnosis/protection circuit and/or a control logic circuit; the first rated working current and the first rated working voltage of the diagnosis/protection circuit and the control logic circuit are respectively smaller than a preset current threshold value and a preset voltage threshold value; the second rated working current of the driving tube circuit is N times greater than the first rated working current, the second rated working voltage of the driving tube circuit is M times greater than the first rated working voltage, and M, N is a preset positive integer; the chip to be detected can adopt an NMOS driving tube and/or a PMOS driving tube.

Similarly, the embodiment of the invention also discloses a driving chip and a controller; the drive chip comprises a storage medium body for storing a computer program; the computer program, when executed by the microprocessor, may implement the integrated circuit test method as described above; the controller comprises the detection device and/or the driving chip, and can be used for solving the same technical problems.

In summary, the first measuring point partitioning step/unit of the invention sets a test point array in a conductor connection area between a gate driving circuit and a driving tube circuit of a chip to be detected and obtains a gate signal set of the driving tube; the second grid detection step/unit compares the difference between the grid signal set of the driving tube and a preset standard signal and marks an abnormal signal on a corresponding failure position array, so that a corresponding driving tube circuit is determined and used as a target circuit of failure analysis FA, and the detection process insensitive to electrical characteristics is avoided; the third inter-pole detection step/unit and the fourth photoelectric positioning step/unit are combined with an electrical verification process and a laser beam induced resistance change (OBIRCH), a micro light microscope (EMMI) and other processes, so that the accurate positioning scheme of the FA process is further improved.

It should be noted that, the terms "first", "second", and the like are used herein merely to describe each component in the technical solution, and do not constitute a limitation on the technical solution, and are not to be construed as indicating or implying importance of the corresponding component; elements with "first", "second" and the like mean that in the corresponding technical solution, the element includes at least one.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the technical effects, technical features and objects of the present invention will be further understood, and the present invention will be described in detail below with reference to the accompanying drawings, which form a necessary part of the specification, and together with the embodiments of the present invention serve to illustrate the technical solution of the present invention, but not to limit the present invention.

Like reference numerals in the following drawings represent like parts.

FIG. 1 is a schematic diagram of a product according to an embodiment of the present invention.

FIG. 2 is a flow chart of a method according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the composition structure of an embodiment of the product of the present invention.

FIG. 4 is a second flow chart of the method according to the embodiment of the invention.

Fig. 5 is a schematic diagram of a component structure of an embodiment of the present invention, namely a BDC driving chip test structure.

Fig. 6 is a schematic diagram of a second component structure of the product according to the present invention, namely a BLDC driving chip test structure.

FIG. 7 is a schematic diagram of a third embodiment of the present invention, namely a Stepper driver chip test structure.

FIG. 8 is a second schematic view of the use scenario of the product according to the present invention.

FIG. 9 is a third view of the use of the product according to the present invention.

Wherein:

010-BDC motor power end;

011-half bridge output 1;

012-half bridge output 2;

019-BDC;

020-BLDC motor power;

021-U phase output end;

022-V phase output end;

023-W phase output;

029-BLDC ground;

030-Stpper motor power supply;

031-A bridge output 1;

032-A bridge output 2;

033-B bridge output 1;

034-B bridge output 2;

100-a first measuring point partitioning step;

110-a first electrical verification step;

120-a first two-photon positioning step;

200-a second gate detection step;

210-a circuit analysis step;

220-information synthesis;

300-a third inter-pole detection step;

310-a third electrical verification step;

320-a third photoelectric positioning step;

400-fourth photoelectric positioning step;

410-a fourth delamination/slice analysis step;

420-a fourth optical inspection/scan electrode inspection step;

600-detecting device;

610—a first station partition unit;

620-a second gate detection unit;

630-third inter-pole detection unit;

640-fourth photoelectric positioning unit;

900-vehicle;

901-a controller;

903—a driver chip;

905-sensor;

909-electrical loads, such as motors;

910-gate drive circuitry;

920-array of test spots;

930-drive tube circuit;

940-diagnostic/protection circuitry;

950-control logic;

991-a brush direct current motor driving circuit, namely a first driving chip embodiment BDC;

993-brushless DC motor drive circuit, namely third drive chip embodiment BLDC;

995-Stepper motor drive circuit, fifth drive chip example Stepper;

999-chip to be detected.

Description of the embodiments

The present invention will be described in further detail with reference to the accompanying drawings and examples. Of course, the following specific examples are set forth only to illustrate the technical solution of the present invention, and are not intended to limit the present invention. Furthermore, the parts expressed in the examples or drawings are merely illustrative of the relevant parts of the present invention, and not all of the present invention.

The integrated circuit testing method shown in fig. 2 includes a first station partitioning step 100 and a second gate detecting step 200; the first test point partitioning step 100 sets a test point array 920 in a conductor connection area between the gate driving circuit 910 and the driving tube circuit 930 of the chip 999 to be tested as shown in fig. 1, where the test point array 920 can be used for feature signal collection, and the feature signals form a driving tube gate signal set.

Further, the second gate detection step 200 compares the difference between the set of gate signals of the driving tube and the preset standard signal, marks the abnormal signal on the failure position array corresponding to the test point array 920, and uses the driving tube circuit 930 corresponding to the failure position array as the target circuit for further failure analysis; based on the method, the failure position of the chip can be screened, the investigation range is reduced, and the failure analysis efficiency is improved.

Further, as shown in fig. 4, the first station partitioning step 100 of the integrated circuit testing method further includes a first electrical verification step 110; the first electrical verification step 110 obtains the current circuit parameter set of the preset measurement port of the chip 999 to be detected, and compares the difference between the current circuit parameter set and the typical parameter set; if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, the corresponding circuit or chip area is considered to have a failure structure or failure risk.

In particular, the first one-to-one electrical verification step 110 may be performed in a lossless manner or when the first one-to-one electrical verification step 110 is employed, intrusion into designated areas and/or interior areas of the chip 999 package structure to be inspected is avoided.

Wherein test point array 920 may be constructed using a focused ion beam FIB; the array of test points 920 may be directed via the microprobe MicroProbe to a predetermined detection device and/or probe contact, which detection device may be a voltage detection device and/or a current detection device.

Further, the integrated circuit testing method may further provide a third inter-electrode detecting step 300 shown in fig. 2; the third inter-pole detection step 300 obtains the target current/voltage data or target curve between the gate and the source/drain of the driving tube in the target circuit; comparing the target current data, the target voltage data and/or the target curve, and judging a failure area in the target circuit; the target curve comprises a voltage-current relation curve I-Vcurve.

The third inter-electrode detecting step 300 may also be provided with a third electrical verifying step 310 as shown in fig. 4, where the third electrical verifying step 310 also obtains a current circuit parameter set of a preset measurement port of the chip 999 to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, the corresponding circuit or chip area is considered to have a failure structure or failure risk.

Further, the integrated circuit testing method as shown in fig. 2 is further provided with a fourth photo positioning step 400; the fourth photo-positioning step 400 detects the target circuit by using the laser beam to induce the resistance change OBIRCH and/or the micro-microscope EMMI, and if the calorific value and/or the light spot parameter of the target circuit exceeds the safety threshold, determines that the corresponding area has a failure structure or a failure risk.

Wherein the fourth electro-optic positioning step 400 may further perform accurate positioning of the failure circuit through at least one of a delamination/dicing process, an optical inspection process, and/or a scanning electron microscopy process; the second gate detection step 200 may also improve the detection accuracy by physically analyzing the PFA step.

Specifically, the drive tube circuit 930 may be a motor drive circuit; the motor driving circuit can adopt a bridge driving structure; the first measuring point partitioning step 100 and the second grid electrode detecting step 200 can more accurately perform failure analysis through the execution process when the chip 999 to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise preset scenes such as locked rotor, overvoltage of a power end, power peak, power short circuit and the like.

The motor drive circuit may be a brushed dc motor drive circuit 991, a brushless dc motor drive circuit 993, a stepper motor drive circuit 995, and/or a permanent magnet motor drive circuit 997, among others.

Further, the chip 999 to be tested may also include a diagnosis/protection circuit 940 and/or a control logic circuit 950; the first rated operating current and the first rated operating voltage of the diagnostic/protection circuit 940 and the control logic circuit 950 are less than a preset current threshold and voltage threshold, respectively; the second rated operating current of the driving tube circuit 930 is N times greater than the first rated operating current, the second rated operating voltage of the driving tube circuit 930 is M times greater than the first rated operating voltage, M, N is a preset positive integer; the chip 999 to be tested can adopt an NMOS driving tube and/or a PMOS driving tube.

Accordingly, the core part of the detection device 600 shown in fig. 3 is provided with a first measurement point partition unit 610 and a second gate detection unit 620; the first measurement point partition unit 610 of the device, similarly, a test point array 920 is disposed in a conductor connection area between the gate driving circuit 910 and the driving tube circuit 930 of the chip 999 to be detected as shown in fig. 1, where the test point array 920 is used for collecting characteristic signals, and the characteristic signals form a driving tube gate signal set; the second gate detection unit 620 compares the difference between the set of driving tube gate signals and the preset standard signal, and marks the abnormal signal on the failure location array corresponding to the test point array 920, and uses the driving tube circuit 930 corresponding to the failure location array as a target circuit for further failure analysis.

Wherein, the first measuring point partition unit 610 is further provided with an electrical verification unit; the electrical verification unit acquires a current circuit parameter set of a preset measurement port of a chip 999 to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; if the difference between the corresponding elements of the current circuit parameter set and the typical parameter set is greater than a preset safety threshold, the corresponding circuit or chip area is considered to have a failure structure or failure risk.

Specifically, the electrical verification unit may be performed in a lossless manner or such that the electrical verification unit is prevented from invading the designated area and/or the inner area of the package structure of the chip 999 to be detected; the test point array 920 can be constructed by adopting a Focused Ion Beam (FIB); the test point array 920 is then led via the microprobe MicroProbe to a predetermined test device and/or probe contact, which may likewise be a voltage test device and/or a current test device.

Further, the detecting device 600 as shown in fig. 3 is further provided with a third inter-pole detecting unit 630; the third inter-pole detection unit 630 obtains target current/voltage data or a target curve between the gate and the source/drain of the driving tube in the target circuit; comparing the target current data, the target voltage data and/or the target curve, and judging a failure area in the target circuit; wherein the target curve comprises a voltage-current relation curve I-Vcurve; the third inter-pole detection unit 630 may also be provided with an electrical verification unit as described above.

Further, the detecting device 600 as shown in fig. 3 may be further provided with a fourth photo-positioning unit 640; the fourth photoelectric positioning unit 640 detects the target circuit through the resistance change OBIRCH and/or the micro light microscope EMMI induced by the laser beam, and if the calorific value and/or the light spot parameter of the target circuit exceeds the safety threshold, determines that the corresponding area has a failure structure or a failure risk; the fourth electro-optical positioning unit 640 may be further provided with at least one of a delamination/dicing process, an optical inspection process, and/or a scanning electron microscopy process; the second gate detection unit 620 may also be provided with a physical analysis PFA process.

Specifically, the drive tube circuit 930 thereof includes a motor drive circuit; the motor driving circuit can adopt a bridge driving structure; the first measuring point partition unit 610 and the second grid electrode detection unit 620 can execute operations when the chip 999 to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise locked rotor, overvoltage of a power end, power peak and power short circuit.

The motor drive circuits include a brush dc motor drive circuit 991, a brushless dc motor drive circuit 993, a stepper motor drive circuit 995, and/or a permanent magnet motor drive circuit 997, among others.

In particular, the chip 999 to be detected may also be provided with a diagnosis/protection circuit 940 and/or a control logic circuit 950; the first rated operating current and the first rated operating voltage of the diagnostic/protection circuit 940 and the control logic circuit 950 are less than a preset current threshold and voltage threshold, respectively; the second rated operating current of the driving tube circuit 930 is N times greater than the first rated operating current, the second rated operating voltage of the driving tube circuit 930 is M times greater than the first rated operating voltage, M, N is a preset positive integer; the chip 999 to be tested includes NMOS drive tubes and/or PMOS drive tubes.

Similarly, the driving chip 903 shown in fig. 9 and the controller 901 shown in fig. 8 also employ the same inventive concept; which includes a drive chip 903 for storing a storage medium body of a computer program; the computer program, when executed by the microprocessor, may implement the integrated circuit test method as described above; the controller 901 includes the detection device 600 and/or the driving chip 903 as described above, which can solve the same technical problems.

In practical application, the process shown in fig. 4 can be used for failure analysis and fault circuit positioning of the target chip 999; the target chip can be an integrated motor driving chip, and is particularly suitable for a scene that the related technology cannot detect obvious abnormal fault points.

In the circuit analysis step 210 and the third second photoelectric positioning step 320 shown in fig. 4, when the preprocessing of the first measurement point partitioning step 100 needs to be completed, the detection or analysis can be performed by a global positioning analysis means in the related art, such as OBIRCH or EMMI; otherwise, a clearly abnormal hot spot or luminous spot will not be captured.

Further, the internal circuit structure of the chip needs to be analyzed according to the result of the electrical verification so as to reduce the range of the circuit module where the fault point is located; after the specific circuit structure where the fault is located is locked, the fault can be locally positioned again by combining a positioning analysis means, and the physical position of the fault point on the chip layout is accurately positioned.

The inventor researches and discovers that the probability of failure of the integrated motor driving chip is far higher than that of failure of other internal circuit modules (such as the control logic circuit 950 and the diagnosis/protection circuit 940) because of the specificity of the hardware structure and the application scene, and the output of the internal driving tube is directly connected with an external motor load.

Therefore, for analysis of the abnormal function of the integrated motor driving chip, the working state of the driving tube needs to be focused; a focused ion beam FIB (Focused Ion Beam) can be used to fabricate FIB test spot array 920, i.e., PAD sequence, on the drive tube gate signal metal trace; when the chip is in operation (i.e., loaded), the microprobe MP (Micro Probe) is used to detect the drive tube gate signal to determine the specific location of the failed drive tube.

Specifically, as shown in fig. 5, 6 and 7, three common integrated driving chips are respectively provided; the BDC driving chip needs to respectively manufacture test node PAD sequences on the grid electrodes of the 4 driving tubes of the two-path half bridge; for an integrated BLDC driving chip, test node PAD sequences are required to be respectively manufactured on the grid electrodes of 6 driving tubes of the three-way half bridge; for the integrated Stepper driver chip, test node PAD sequences are required to be fabricated on the gates of the 8 driving transistors of the four-way half bridge.

During the period, after detecting that the gate signal of the driving tube is abnormal by the microprobe technology, the current-voltage curve of the gate and the source drain of the driving tube can be further measured by the second gate detection step 200; if failure modes such as short circuit, open circuit, electric leakage and the like are detected, the specific physical position of the fault point on the layout can be locked by performing OBIRCH or EMMI failure positioning again; in addition, after determining the fault location, further layer-by-layer or slice analysis may be performed to find the damage point through physical analysis PFA (Physical Failure Analysis).

For failure analysis of an integrated motor drive chip, different analysis flows and analysis methods are generally available according to different failure modes; if the chip pin current voltage curve, i.e. I-Vcurve, has obvious anomalies (such as short circuit, open circuit, leakage), then the failure localization and physical analysis of PFA can be accomplished according to the relevant techniques.

However, if the current-voltage curve of the chip pin is normal, but the chip has no output or abnormal output waveform, and the positioning means (for example, the laser beam induced resistance change OBIRCH method (Optical Beam Induced RESISTANCE CHANGE) or the micro light microscope EMMI (Emission Microscope) method) of the related technology cannot capture obvious abnormal hot spots or light spots, the method and the product of the embodiment of the invention need to be adopted to process the internal circuit structure of the chip so as to reduce the fault range.

Because the integrated motor driving chip comprises various circuits such as analog, digital, power and the like, the internal structure is complex; therefore, it is important to make a reasonable detection and analysis scheme, or the success rate of fault diagnosis is greatly improved and the analysis period is shortened.

It should be noted that the foregoing examples are merely for clearly illustrating the technical solution of the present invention, and those skilled in the art will understand that the embodiments of the present invention are not limited to the foregoing, and that obvious changes, substitutions or alterations can be made based on the foregoing without departing from the scope covered by the technical solution of the present invention; other embodiments will fall within the scope of the invention without departing from the inventive concept.

Claims (19)

1. The integrated circuit testing method is characterized by comprising a first measuring point partitioning step (100) and a second grid electrode detecting step (200); wherein: the first measuring point partitioning step (100) is to set a test point array (920) PAD in a conductor connection area between a gate driving circuit (910) and a driving tube circuit (930) of a chip (999) to be detected, wherein the test point array (920) PAD is used for collecting characteristic signals, and the characteristic signals form a driving tube gate signal set; the second gate detection step (200) compares the difference between the driving tube gate signal set and a preset standard signal, marks an abnormal signal on a failure position array corresponding to the test point array (920) PAD, and uses the driving tube circuit (930) corresponding to the failure position array as a target circuit for further failure analysis.

2. The integrated circuit testing method of claim 1, wherein: the first measuring point partitioning step (100) further comprises a first electrical verification step (110); the first one-to-one electrical verification step (110) obtains a current circuit parameter set of a preset measurement port of the chip (999) to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; and if the difference between the current circuit parameter set and the corresponding element of the typical parameter set is greater than a preset safety threshold, considering that a corresponding circuit or chip area has a failure structure or failure risk.

3. The integrated circuit testing method of claim 2, wherein: the first one-to-one electrical verification step (110) is performed in a lossless manner or the first one-to-one electrical verification step (110) does not invade the designated area and/or the inner area of the packaging structure of the chip (999) to be detected.

4. A method of testing an integrated circuit as claimed in any one of claims 1 to 3, wherein: the test point array (920) PAD is constructed by adopting a Focused Ion Beam (FIB); the array of test points (920) PAD is directed via a microprobe MicroProbe to a predetermined detection device and/or probe tip, the detection device including a voltage detection device and/or a current detection device.

5. The integrated circuit testing method of claim 4, further comprising a third inter-pole detection step (300); the third inter-pole detection step (300) obtains target current/voltage data or a target curve between the grid electrode and the source electrode/drain electrode of the driving tube in the target circuit; comparing the target current data, the target voltage data and/or the target curve, and judging a failure area in the target circuit; the target curve includes a voltage-current relationship curve I-Vcurve.

6. The integrated circuit testing method of claim 5, wherein: the third inter-pole detection step (300) further comprises a third electrical verification step (310), wherein the third electrical verification step (310) also obtains a current circuit parameter set of a preset measurement port of the chip (999) to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; and if the difference between the current circuit parameter set and the corresponding element of the typical parameter set is greater than a preset safety threshold, considering that a corresponding circuit or chip area has a failure structure or failure risk.

7. The integrated circuit testing method of any of claims 1 to 3 or 5,6, further comprising a fourth opto-electronic positioning step (400); and the fourth photoelectric positioning step (400) detects the target circuit through laser beam induced resistance change (OBIRCH) and/or a micro light microscope (EMMI), and if the calorific value and/or the light spot parameter of the target circuit exceed a safety threshold, the corresponding area is determined to have a failure structure or a failure risk.

8. The integrated circuit testing method of claim 7, wherein: the fourth electro-optic positioning step (400) further comprises at least one of a delamination/dicing process, an optical inspection process and/or a scanning electron microscopy process; the second gate detection step (200) further includes a physical analysis PFA step.

9. The integrated circuit testing method of any one of claims 1 to 3 or 5, 6, 8, wherein: the drive tube circuit (930) includes a motor drive circuit; the motor driving circuit comprises a bridge driving structure; the first measuring point partitioning step (100) and the second grid electrode detecting step (200) are executed when the chip (999) to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise locked rotor, overvoltage of a power end, power peak and power short circuit.

10. The integrated circuit testing method of claim 9, wherein: the motor drive circuit comprises a brush direct current motor drive circuit (991) BDC, a brushless direct current motor drive circuit (993) BLDC, a stepping motor drive circuit (995) Stepper and/or a permanent magnet motor drive circuit (997) PMSM.

11. The integrated circuit testing method of any one of claims 1 to 3 or 5, 6, 8, 10, wherein: the chip (999) to be detected also comprises a diagnosis/protection circuit (940) and/or a control logic circuit (950); the first rated operating current and the first rated operating voltage of the diagnostic/protection circuit (940) and the control logic circuit (950) are less than a preset current threshold and voltage threshold, respectively; the second rated working current of the driving tube circuit (930) is larger than the first rated working current by N times, the second rated working voltage of the driving tube circuit (930) is larger than the first rated working voltage by M times, and M, N is a preset positive integer; the chip to be detected (999) comprises an NMOS drive tube and/or a PMOS drive tube.

12. A detection device (600) comprises a first measuring point partition unit (610) and a second grid detection unit (620); wherein: the first measuring point partition unit (610) is provided with a test point array (920) PAD in a conductor connection area between a gate driving circuit (910) and a driving tube circuit (930) of a chip (999) to be detected, the test point array (920) PAD is used for collecting characteristic signals, and the characteristic signals form a driving tube gate signal set; the second gate detection unit (620) compares the difference between the driving tube gate signal set and a preset standard signal, marks an abnormal signal on a failure position array corresponding to the test point array (920) PAD, and uses the driving tube circuit (930) corresponding to the failure position array as a target circuit for further failure analysis.

13. The detection apparatus (600) of claim 12, wherein: the first station partition unit (610) further comprises an electrical verification unit; the electrical verification unit obtains a current circuit parameter set of a preset measurement port of the chip (999) to be detected, and compares the difference between the current circuit parameter set and a typical parameter set; if the difference between the current circuit parameter set and the corresponding element of the typical parameter set is greater than a preset safety threshold, considering that a corresponding circuit or chip area has a failure structure or failure risk; the electrical verification unit is performed in a lossless manner or the electrical verification unit does not invade the designated area and/or the inner area of the packaging structure of the chip (999) to be detected; the test point array (920) PAD is constructed by adopting a Focused Ion Beam (FIB); the array of test points (920) PAD is directed via a microprobe MicroProbe to a predetermined detection device and/or probe tip, the detection device including a voltage detection device and/or a current detection device.

14. The detection device (600) of claim 12 or 13, further comprising a third inter-pole detection unit (630); the third inter-pole detection unit (630) acquires target current/voltage data or a target curve between the gate and the source/drain of the driving tube in the target circuit; comparing the target current data, the target voltage data and/or the target curve, and judging a failure area in the target circuit; the target curve comprises a voltage-current relation curve I-Vcurve; the third inter-pole detection unit (630) further comprises the electrical verification unit.

15. The detection apparatus (600) of claim 14, further comprising a fourth electro-optic positioning unit (640); the fourth photoelectric positioning unit (640) detects the target circuit through laser beam induced resistance change (OBIRCH) and/or micro light microscope (EMMI), and if the calorific value and/or the light spot parameter of the target circuit exceeds a safety threshold, the corresponding area is determined to have a failure structure or a failure risk; the fourth electro-optic positioning unit (640) further comprises at least one of a delamination/dicing process, an optical inspection process, and/or a scanning electron microscopy process; the second gate detection unit (620) further includes a physical analysis PFA step.

16. The detection apparatus (600) of claim 12, 13 or 15, wherein: the drive tube circuit (930) includes a motor drive circuit; the motor driving circuit comprises a bridge driving structure; the first measuring point partition unit (610) and the second grid detection unit (620) are executed when the chip (999) to be detected is provided with load equipment; the load equipment comprises a load motor, and the working conditions of the load motor comprise locked rotor, overvoltage of a power end, power peak and power short circuit; the motor drive circuit comprises a brush direct current motor drive circuit (991) BDC, a brushless direct current motor drive circuit (993) BLDC, a stepping motor drive circuit (995) Stepper and/or a permanent magnet motor drive circuit (997) PMSM.

17. The detection apparatus (600) of claim 12, 13 or 15, wherein: the chip (999) to be detected also comprises a diagnosis/protection circuit (940) and/or a control logic circuit (950); the first rated operating current and the first rated operating voltage of the diagnostic/protection circuit (940) and the control logic circuit (950) are less than a preset current threshold and voltage threshold, respectively; the second rated working current of the driving tube circuit (930) is larger than the first rated working current by N times, the second rated working voltage of the driving tube circuit (930) is larger than the first rated working voltage by M times, and M, N is a preset positive integer; the chip to be detected (999) comprises an NMOS drive tube and/or a PMOS drive tube.

18. A drive chip (903) comprising a storage medium body for storing a computer program; the computer program, when executed by a microprocessor, implements the integrated circuit testing method of any one of claims 1 to 11.

19. A controller (901) comprising the detection device (600) of any one of claims 12 to 17 and/or the driver chip (903) of claim 18.