CN1178986A - Storing device and its control method - Google Patents
Storing device and its control method Download PDFInfo
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- CN1178986A CN1178986A CN 97116163 CN97116163A CN1178986A CN 1178986 A CN1178986 A CN 1178986A CN 97116163 CN97116163 CN 97116163 CN 97116163 A CN97116163 A CN 97116163A CN 1178986 A CN1178986 A CN 1178986A
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Abstract
A memory device comprises a differential circuit for outputting a signal corresponding to the difference in value between an input read address signal and an input write address signal, a determination circuit for outputting a decision signal responsive to the output of the differential circuit and an address generating circuit for outputting a generated write address and a generated read address having a given or greater difference in signal value therebetween, based on the input read address signal, the input write address signal and the decision signal.
Description
The present invention relates to a kind of control method of multiport memory of the data delay circuit that is used for video and similar system thereof.
As an example of common multiport memory, dual-ported memory (to call " two-port memory " in the following text) has a read decoder and a write decoder, and can carry out in one-period and read to handle and write processing.
The objective of the invention is to avoid following problem: promptly when supplying with the reading address and write address and on the cycle, differ from one another of storer since read address and write address be consistent (coincidence) destroys the data that are read out or reads and writes generation simultaneously.
According to an aspect of the present invention, provide a kind of memory storage for achieving the above object, having comprised:
A difference channel is used to export a signal, and this signal value is read address signal and the difference of importing writing address signal corresponding to input;
A decision circuit, be used for input signal values when above-mentioned difference channel within certain predetermined value the time this decision circuit output have the decision signal of first level, this decision circuit output has the decision signal of second level when the output signal value of described difference channel exceeds predetermined value.
An address generating circuit, be used to receive the writing address signal of input, input read address signal and decision signal thereof, and export the write address that this circuit generates and read the address, its signal difference is at least greater than predetermined value, and no matter the difference between address signal is read in input writing address signal and input.
A write address code translator is used to decipher the write address of generation;
Read address decoder for one, be used to decipher the address of reading of generation; And
A storer is used in certain address storage input data, and the output that this address produces corresponding to the write address code translator reaches from certain address output data, and this address is corresponding to reading the output that address decoder produces.
Various typical case's inventions of the application have below briefly been described.Can understand the application's various inventions and concrete structure thereof by following description.
Illustrate particularly and pointed out clearly although the conclusion of instructions is claims, be looked at as the main contents of invention, but can believe, by following description and with reference to the accompanying drawing purpose that the present invention may be better understood, feature and further purpose, feature and advantage.Wherein:
Fig. 1 is the logic diagram of two-port memory, is one embodiment of the present of invention;
Fig. 2 is the block scheme of write address generative circuit;
Fig. 3 is a block scheme of reading address generating circuit;
Fig. 4 is the circuit diagram that the address meets (coincidence) testing circuit 8;
Fig. 5 is the circuit diagram of address coincidence detection circuitry 15; And
Fig. 6 is a sequential chart of describing two-port memory, is one embodiment of the present of invention.
Most preferred embodiment of the present invention is described below with reference to accompanying drawings.
Fig. 1 is the schematic block diagram that one embodiment of the present of invention are shown.
Two-port memory comprises that 3, one of 2, one address generating circuits of 1, one decision circuit of a difference channel read 5, one input/output circuitries 6 of 4, one write address code translators of address decoder and internal memory or storage unit 7.
Difference channel 1 is the circuit that is used to export differential signal, and this differential signal represents to import the absolute value of the difference of reading address and input write address.Decision circuit 2 is the circuit that are used to export decision signal, and this decision signal represents that whether difference value signal is greater than certain predetermined value (being 2 in the present embodiment).Specifically, when the differential signal value is bigger than 2, low level decision signal of decision circuit 2 outputs; High level decision signal of output when the differential signal value is little or more equal than 2.Address generating circuit 3 comprises that one is read address generating circuit and a write address generative circuit.Address generating circuit 3 is the circuit that are used for reading according to input the write address of reading an address and a generation of address, input write address, decision signal, a generation of differential signal output.Input/output circuitry 6 is to be used for incoming external data and its data that output to storer 7 and input store 7 outputs are outputed to the outside with it again.Reading address decoder 4 is the circuit that decipher the address of reading that are used for generating.Write address code translator 5 is to be used for circuit that the write address that generates is deciphered.Storer 7 is to be used for output data with input/output circuitry 6 to write by write address code translator 5 determined addresses and will be by the data output of reading to store in the address decoder 4 determined addresses.
Fig. 2 is the circuit diagram of write address generative circuit.
The write address generative circuit comprises an address coincidence detection circuitry 8, NOR circuit 9, counter 10, d type flip flop 12 and 13, latch cicuit 14 and selector switch 11.Address coincidence detection circuitry 8 is the circuit that are used to export a signal A, and this signal A represents whether difference value signal is identical with predefined value " 2 ".Specifically, when the output and the setting value " 2 " of decision circuit 2 is identical, low level signal A of address coincidence detection circuitry 8 outputs, and when the output of decision circuit 2 and setting value " 2 " are inequality, export a high level signal A.D type flip flop 12 is to be used to receive a decision signal and one write clock and export one by decision signal being postponed a circuit of writing the signal B that clock obtains.NOR circuit 9 is used to realize neither-NOR operation and the output signal C of signal A and signal B.When high level signal C enter counter 10, counter 10 is write a rising edge output predetermined transfer address (jumpaddress) " 16 " of clock as Counter Value " 16 " at next.Then, the counter 10 response rising edge of writing clock carries out increment and exports its incremental result the Counter Value of last output.D type flip flop 13 is used to receive the input write address and writes clock and export signal of writing the input write address of clock of a delay.The output of selector switch 11 count pick up devices 10 and the output of d type flip flop 12 and 13 and, response is corresponding to the output signal B of d type flip flop 12, with the some output of counter 10 and d type flip flop 13 write address as generation.Specifically, selector switch 11 when input be low level signal B the time, the output of output d type flip flop 13, and when import be high level signal B the time output counter 10 output.Have between the write address terminal that generates and the selector switch 11 and be electrically connected to receive the write address of generation.Latch cicuit 14 receives write address and the signal C that generates.When in the latch cicuit 14 during input high level signal C, latch cicuit 14 latchs the write address of input this moment generation wherein, and the write address of this generation of latching is exported as signal J.
What Fig. 4 provided is the circuit diagram of address coincidence detection circuitry 8.
Address coincidence detection circuitry 8 comprises 81 at eight EXOR doors, two NOR doors 82 and a NAND door 83.The input end of eight EXOR doors 81 (A7, A6, A5, A4, A3, A2, A1 and A0) is supplied with setting value＜2 with binary format 〉, the binary form of this setting value is shown (00000010).On the other hand, other input end of eight EXOR doors (B7, B6, B5, B4, B3, B2, B1 and B0) is supplied to the differential signal of representing with binary mode.
What Fig. 3 provided is the circuit diagram of reading address generating circuit.This is read address generating circuit and comprises 16, one selector switchs 17 of 15, one counters of an address coincidence detection circuitry and a T trigger 18.
The input of address coincidence detection circuitry 15 is that the address is read in signal J and input.Address coincidence detection circuitry 15 is a kind of like this circuit, when address low level signal of output when inequality is read in the value of signal J and input, and reads the address when identical when the value of signal J and input, then exports a high level signal.
When high level signal a enter counter 16, counter 16 is read a rising edge predetermined transfer address of output (being 16 in this example) of clock as Counter Value 16 at next.Then, counter 16 responses are read the Counter Value of exporting before the rising edge increase of clock and are exported this incremental result.Toggle flip-flop 18 is used for the output signal a of count pick up device 16, and output signal b.Specifically, T trigger 18 is used for the level inversion with last output signal b, and response signal a exports anti-phase level signal from high level to low level negative edge.The output of selector switch 17 count pick up devices 16, the address is read in signal b and input.One in the output of reading address and counter 16 is imported in the level output of selector switch 17 response signal b.Specifically, when input low level signal b selector switch 17 output input read address, the output of selector switch 17 output counters 16 when input high level signal b.The address terminal 20 of reading that generates has the address of reading that is electrically connected and is provided generation with 17 of selector switchs.
Fig. 5 illustrates the circuit diagram of address coincidence detection circuitry 15.
Address coincidence detection circuitry 15 comprises 151, two NAND doors of eight EXNOR doors and a NOR door 153.The input end of eight EXNOR doors 151 (A0, A1, A2, A3, A4, A5, A6 and A7) is supplied to the signal " J " of binary representation.To read other input end (B7, B6, B5, B4, B3, B2, B1 and B0) that the address offers eight EXNOR doors with the input that binary mode is represented.
6 courses of work of describing embodiments of the invention below with reference to accompanying drawings.
Fig. 6 describes is the sequential chart of the two-port memory course of work according to an embodiment of the invention.
According to sequential chart, be the data 10,12,13 of cycle input two-port memory with T ... be delayed and be to export in the 2T cycle with the twice of period T.According to this sequential chart also as can be known, be to repeat in the cycle with 8T owing to a unshowned write address counter, write address are arranged.
The course of work of period 1 two-port memory is at first described.
This cycle is corresponding to such cycle: i.e. input is therebetween read the absolute value of difference of address and input write address greater than 2.Expression value of difference channel 1 output is greater than 2 differential signal.Decision circuit 2 is owing to difference value signal is exported a low level decision signal greater than 2.Because at low level signal B of d type flip flop 12 outputs of this cycle write address generative circuit, so the output of selector switch 11 output d type flip flops 13.That is, address generating circuit 3 output postpones a write address of writing signal that clock obtains as generation by import write address.Furtherly, be reset owing to read the T trigger 18 of address generating circuit, so export a low level signal b, selector switch 17 is exported the address of reading of input.To be address generating circuit 3 read the address with input reads address output as what generate.
The course of work of two-port memory during second round is described below.
Difference channel 1 is read an address " 2 " and an input write address " 0 " and is imported an input and read address " 5 " and one and import and export an expression value between the write address " T " and be less than or equal to 2 differential signal in input of input.Be less than or equal to during 2 the differential signal high level decision signal of decision circuit 2 outputs in difference channel 1 output expression value.At second period, when the output difference value signal of difference channel 1 reached " 2 " for the first time, NOR door 9 received a low level signal A and a low level signal B and exports a high level signal C.Latch cicuit 14 response high level signal C latch the write address " 7 " of the generation of input this moment.The write address of the generation that latch cicuit 14 will latch " 7 " is exported as signal J.Response high level C, counter 10 is exported a predetermined transfer address " 16 " at next rising edge of writing clock as Counter Value " 16 ".Counter 10 responds the rising edge of writing clock then increases last output counter value and output increment result.When selector switch 11 received low level signal B, its output with d type flip flop 13 was exported as the write address that generates.On the other hand, when selector switch 11 received high level signal B, its output with counter 10 was exported as the write address that generates.Then, difference channel 1 receives an input and reads address " 6 " and an input write address " 0 ".In addition, differential signal that value is " 6 " of difference channel 1 output.At this moment, because difference value signal is greater than 2, so low level decision signal of decision circuit 2 outputs.Because d type flip flop 12 is to export after clock is write in one of decision signal delay again, so d type flip flop 12 also is to export after clock is write in one of low level signal B delay after decision signal becomes low level again.When selector switch 11 receives low level signal B, the then output of output trigger 13.That is, signal of address generating circuit 3 output is as the write address that generates, and this signal is write clock and obtained by import one of write address delay.
Owing to the value " 7 " of the value of reading the address in input second round and signal J is unequal, low level signal of address coincidence detection circuitry 15 outputs.Because low level signal b of T trigger 18 outputs is so selector switch 17 is exported the address of reading of input.That is, in the address of reading of address generating circuit 3 output input second round.
The course of work of period 3 two-port memory is described below.
Corresponding one-period like this of this cycle: promptly import the absolute value of the difference of reading address and input and address around here greater than 2.Expression value of difference channel 1 output is greater than 2 differential signal.Decision circuit 2 is owing to difference value signal is exported a low level decision signal more than or equal to 2.Because the d type flip flop 12 of write address generative circuit is exported a low level signal B around here, so the output of selector switch 11 output d type flip flops 13.That is, signal of address generating circuit 3 output is as the write address that generates, and this signal is write clock and obtained by import one of write address delay.When the address coincidence detection circuitry 15 of reading address generating circuit receives input when reading address " 7 ", high level signal a of address coincidence detection circuitry 15 outputs.Then, when the value of reading the address when input becomes the value of non-" 7 ", low level signal of address coincidence detection circuitry 15 outputs.The high level signal a of response address coincidence detection circuitry 15 outputs, the next one of counter 16 behind input high level signal a read predetermined transfer address of rising edge output (be 16 this moment) of clock as Counter Value 16.Then, counter 16 responds the rising edge of reading clock increases last output counter value and output increment result.To low level redirect, T trigger 18 is exported a high level signal b to response signal 9 from high level.The output of selector switch 17 output counter 16 in high level signal b input.
The operation of period 4 two-port memory is described below.
Difference channel 1 is read an address " 2 " and an input write address " 0 " and is imported an input and read address " 5 " and one and import and export a value between the write address " 7 " and be less than or equal to 2 differential signal in input of input.When difference channel 1 output valve is less than or equal to 2 differential signal, high level decision signal of decision circuit 2 outputs.In the period 4, when the difference value signal of difference channel 1 output reached " 2 " for the first time, NOR circuit 9 received a low level signal A and a low level signal B and exports a high level signal C.Response high level signal C, latch cicuit 14 latchs the write address " 7 " of the generation of input this moment, and it is exported as signal J.Behind the input high level signal C, it writes predetermined transfer address of rising edge output (be 16 this moment) of clock as Counter Value " 16 " at the next one in the counter 10.Then, the rising edge of clock is write in counter 10 responses, increases the Counter Value and the output increment result of last output.When selector switch 11 received low level signal B, its output with d type flip flop 13 was exported as the write address that generates.In addition, when selector switch 11 received high level signal B, selector switch 11 was exported the output of counter 10 as the write address that generates.Then, read address " 6 " and input write address when " 0 " when difference channel 1 receives input, export a differential signal, it is worth is " 6 ".At this moment, because difference value signal is greater than 2, low level decision signal of decision circuit 2 outputs.Because d type flip flop 12 one of output have been delayed a decision signal of writing clock, then it is exported one and has been delayed a low level signal B who writes clock after decision signal becomes low level.When selector switch 11 receives low level signal B, the output of output trigger 13.Since in the period 4,18 output a high level signal b, the then outputs of selector switch 17 output counters 16 of T trigger.
The course of work of period 5 two-port memory is described below.
This cycle is read the absolute value of address and the difference of input write address greater than cycle of 2 corresponding to input.Value of difference channel 1 output is greater than 2 differential signal.Decision circuit 2 is owing to difference value signal is exported a low level decision signal greater than 2.Since low level signal B of d type flip flop 12 outputs of write address generative circuit in this cycle, the then output of selector switch 11 output d type flip flops 13.That is, signal of address generating circuit 3 output is as the write address that generates, and this signal is write clock and obtained by import one of write address delay.When address coincidence detection circuitry 15 receives input when reading address value " 7 ", it exports a high level signal.Then, when input is read address value and is become non-" 7 " value, low level signal of address coincidence detection circuitry 15 outputs.Response high level signal a, counter 16 read predetermined transfer address of rising edge output (be 16 this moment) of clock as Counter Value 16 at next behind input high level signal a.Then, counter 16 responds the rising edge of reading clock increases last output counter value and output increment end.To low level redirect, T trigger 18 is exported a low level signal b to response signal a from high level.When low level signal b was input to selector switch 17, exported as the address of reading that generates the address of reading that selector switch will be imported.
From the period 1 to the period 5, write address code translator 5 is the write address decoding that generates, and reads the address decoding of reading that address decoder 4 will generate.Then, storer 7 is storage input data in the address of write address code translator 5 outputs, and the data of storing in the address of output corresponding to the output of reading address decoder 4.
As mentioned above, device is executed in storage according to the two-port of the embodiment of the invention, and the difference of reading address and input write address when input provides two addresses with desirable difference during greater than a predetermined value for storer.Like this, clash this phenomenon, just prevented the maloperation of memory storage owing to avoided offering between the address of storer.Because therefore the control of the address during undebatable use two-port memory can use simple system to constitute.
Although the present invention is described with reference to exemplifying embodiment, the scope that this description is not intended to limit the invention.According to this description exemplifying embodiment and other embodiments of the invention being carried out various modifications, is easy to do for the personnel of knack.Therefore can predict, under the situation that does not exceed essential scope of the present invention, subsidiary claim has covered any this modification and embodiment.
Claims (5)
1. memory storage comprises:
A difference channel is used to export a signal, and the value of this signal is read address signal and the difference of importing writing address signal corresponding to input;
A decision circuit is used for exporting the decision signal with first level when the signal value of exporting from described difference channel is within certain predetermined value, and exports the decision signal with second level when described value surpasses predetermined value;
An address generating circuit is used for receiving the input writing address signal, and address signal and decision signal are read in input, and export the write address that generates and read the address, the difference of this two-address signal value, at least greater than predetermined value, and no matter the difference between the address signal is read in input writing address signal and input;
A write address code translator is used for the write address that generates is deciphered;
Read address decoder for one, be used for the address of reading that generates is deciphered; And
A storer is used in the address of described write address code translator output storage input data, and exports the described output data of storing in the address of address decoder output read.
2. memory storage comprises:
A difference channel is used to export a signal, and the value of this signal is read address signal and the difference of input between the writing address signal corresponding to input;
A decision circuit is used for exporting the decision signal with first level when the signal value of exporting from described difference channel is within certain predetermined value, and exports the decision signal with second level when described value surpasses predetermined value;
An address generating circuit, be used for receiving the input writing address signal, address signal is read in input, and decision signal, and be used for reading address terminal output and read address signal from generation, also be used to respond the decision signal with first level, from generating the signal that the output of write address terminal has first value, this first value is for the input writing address signal and have the difference that first value surpasses the signal of predicted value at least.Also be used to respond decision signal, from generating output of write address terminal and the corresponding signal of input writing address signal with second level;
A write address code translator is used for the output that obtains from generation write address terminal is deciphered;
Read address decoder for one, be used for deciphering read the output that address terminal obtains from generation; And
A storer, be used for from the storage input of the pairing address of the output of described write address code translator data, and be output in the data of storage input in the described pairing address of reading address decoder output.
3. memory storage according to claim 2, wherein from the signal that generates the output of write address terminal corresponding to the input writing address signal, obtain by import the writing address signal delay.
4. according to claim 2 or 3 described memory storages, described address generating circuit wherein is provided, has been used for before the decision signal that described address generating circuit response has first level is exported the signal with first value, immediately storing signal value corresponding to the input write address.This signal is from generating the output of write address terminal, and first value is the input writing address signal and have the difference that first value surpasses the signal of predicted value at least, and this address generating circuit response input is read the address signal value and read address terminal corresponding to the match operation between the retention value of input writing address signal from generation and export signal with the first value address of reading as generation.
5. the method for a control store device may further comprise the steps:
Read address signal when input and during greater than certain predetermined value, provide a signal and a signal of reading address signal corresponding to input corresponding to the input writing address signal to storer with the difference of reading the different input writing address signal of address cycle with input; And
The write address of reading address and generation of a generation is provided to storer when difference is within predetermined value, and this two-address is used for reading and writing data from described storer, and its signal difference surpasses predetermined value at least.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97116163 CN1178986A (en) | 1996-08-07 | 1997-08-06 | Storing device and its control method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP208427/96 | 1996-08-07 | ||
| CN 97116163 CN1178986A (en) | 1996-08-07 | 1997-08-06 | Storing device and its control method |
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| Publication Number | Publication Date |
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| CN1178986A true CN1178986A (en) | 1998-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 97116163 Pending CN1178986A (en) | 1996-08-07 | 1997-08-06 | Storing device and its control method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905059B (en) * | 2000-12-20 | 2011-10-12 | 富士通半导体股份有限公司 | Multi-port memory based on DRAM core and controlling method thereof |
| CN101616068B (en) * | 2008-06-24 | 2013-07-03 | 瑞昱半导体股份有限公司 | Data access device and method applied to communication system |
-
1997
- 1997-08-06 CN CN 97116163 patent/CN1178986A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905059B (en) * | 2000-12-20 | 2011-10-12 | 富士通半导体股份有限公司 | Multi-port memory based on DRAM core and controlling method thereof |
| CN101616068B (en) * | 2008-06-24 | 2013-07-03 | 瑞昱半导体股份有限公司 | Data access device and method applied to communication system |
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