CN117897035A - Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device - Google Patents
Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device Download PDFInfo
- Publication number
- CN117897035A CN117897035A CN202311695566.6A CN202311695566A CN117897035A CN 117897035 A CN117897035 A CN 117897035A CN 202311695566 A CN202311695566 A CN 202311695566A CN 117897035 A CN117897035 A CN 117897035A
- Authority
- CN
- China
- Prior art keywords
- piezoelectric
- layer
- preset
- interface layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 238000002360 preparation method Methods 0.000 title abstract description 22
- 239000002131 composite material Substances 0.000 claims abstract description 24
- 238000009826 distribution Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 40
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 claims description 39
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 33
- 239000010409 thin film Substances 0.000 claims description 33
- 238000000137 annealing Methods 0.000 claims description 26
- 238000002513 implantation Methods 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000002243 precursor Substances 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 19
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 229910052594 sapphire Inorganic materials 0.000 claims description 10
- 239000010980 sapphire Substances 0.000 claims description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 8
- 239000010453 quartz Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 238000010884 ion-beam technique Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021426 porous silicon Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 18
- 238000000427 thin-film deposition Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- -1 hydrogen ions Chemical class 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000002441 X-ray diffraction Methods 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 206010040844 Skin exfoliation Diseases 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000010897 surface acoustic wave method Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
The application relates to a piezoelectric heterogeneous substrate structure, a preparation method and an acoustic wave device, wherein the piezoelectric heterogeneous substrate structure comprises a functional substrate layer and a piezoelectric composite layer arranged on the functional substrate layer; the piezoelectric composite layer comprises a dielectric layer, an interface layer and a piezoelectric film layer which are sequentially arranged along the direction far away from the functional substrate layer, wherein the interface layer is provided with preset element distribution, the concentration of the preset element is larger than a preset threshold value, the interface layer is used for scattering bulk acoustic waves excited by the interdigital electrodes, the reflection of the bulk acoustic waves can be reduced by utilizing the technical scheme provided by the application, and then the situation that the bulk acoustic waves are interfered due to the reflection of the bulk acoustic waves can be avoided, so that the performance of the acoustic wave device can be improved.
Description
Technical Field
The application relates to the technical field of film materials, in particular to a piezoelectric heterogeneous substrate structure, a preparation method and an acoustic wave device.
Background
The piezoelectric composite substrate formed by combining the lithium niobate or lithium tantalate film and the heterogeneous substrate is applied to the acoustic wave device, so that acoustic wave energy in the acoustic wave device can be concentrated in the piezoelectric composite substrate, and further the performance of the acoustic wave device can be improved.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a piezoelectric heterostructure, a preparation method and a technical scheme of an acoustic wave device, wherein an interface layer comprising preset elements is arranged between a dielectric layer and a piezoelectric film layer, and the scattering processing of bulk acoustic waves excited by interdigital electrodes is realized by changing a lattice structure in the interface layer, so that the reflection of the bulk acoustic waves is reduced, the occurrence of interference of the bulk acoustic waves due to the reflection of the bulk acoustic waves is avoided, and the performance of the acoustic wave device is improved.
In one aspect, embodiments of the present application provide a piezoelectric heterogeneous substrate structure including a functional substrate layer and a piezoelectric composite layer disposed on the functional substrate layer;
the piezoelectric composite layer comprises a dielectric layer, an interface layer and a piezoelectric film layer which are sequentially arranged along the direction far away from the functional substrate layer, wherein the interface layer is provided with preset element distribution, the concentration of the preset element is larger than a preset threshold value, and the interface layer is used for carrying out scattering treatment on bulk acoustic waves excited by the interdigital electrodes.
Further, the concentration of the preset element in the interface layer linearly decreases along the direction away from the dielectric layer; or;
The concentration of the preset element in the interface layer is smaller than that of the preset element in the middle of the interface layer at the position close to the dielectric layer and the concentration of the preset element in the position close to the piezoelectric film layer.
Further, the concentration range of the preset element in the interface layer is 0.01% -9.99%, and the material of the interface layer is the same as that of the piezoelectric film layer.
Further, one side of the interface layer, which is close to the dielectric layer, is an interface with high and low fluctuation, and the fluctuation degree of the interface layer with high and low fluctuation is 0-40 nanometers.
Further, the piezoelectric composite layer further includes a charge trapping layer disposed on a side of the dielectric layer remote from the interface layer.
Further, one side of the charge trapping layer close to the dielectric layer is a rough interface or a smooth interface.
Further, the material of the charge trapping layer is polysilicon, amorphous silicon or porous silicon.
Further, the preset element is one or more of hydrogen element, helium element and argon element, the material of the interface layer (22) is at least one of lithium niobate, lithium tantalate, aluminum nitride or quartz material, and the material of the functional substrate layer (1) is at least one of silicon, silicon oxide, silicon on insulator, sapphire and silicon carbide, silicon carbide on insulator, quartz, aluminum nitride, gallium nitride and diamond.
In another aspect, an embodiment of the present application provides a method for preparing a piezoelectric heterostructure, where the method is used to prepare the piezoelectric heterostructure described above, and the method includes:
providing a piezoelectric precursor and a functional substrate, wherein the piezoelectric precursor comprises an interface layer, a dielectric layer and a piezoelectric film layer, the interface layer has preset element distribution, and the concentration of the preset elements is larger than a preset threshold value;
bonding the piezoelectric precursor and the functional substrate to obtain a bonding structure comprising the piezoelectric precursor layer, the piezoelectric film layer, the interface layer, the dielectric layer and the functional substrate layer, wherein the surface of the dielectric layer, which is far away from the interface layer, is a bonding surface;
and carrying out secondary annealing treatment on the bonding structure, and flattening the surface of the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
Further, the piezoelectric precursor is prepared by adopting the following modes:
providing a piezoelectric wafer or a piezoelectric preset structure, wherein the piezoelectric preset structure is a bonding body of the piezoelectric wafer and a silicon oxide material substrate;
performing first ion implantation or ion beam irradiation on one side of the piezoelectric wafer or the piezoelectric preset structure to form an interface layer with preset thickness on the piezoelectric wafer or the piezoelectric preset structure;
Performing secondary ion implantation or grinding on one side of the piezoelectric wafer or the piezoelectric preset structure to obtain the piezoelectric precursor with the piezoelectric film layer and the interface layer;
the implantation energy of the first ion implantation is not greater than the implantation energy of the second ion implantation, the implantation dosage of the first ion implantation is not greater than the implantation dosage of the second ion implantation, and the ions implanted by the first ion implantation and the ions implanted by the second ion implantation are all remained inside the piezoelectric wafer.
Further, after performing the first ion implantation or the ion beam irradiation on one side of the piezoelectric wafer or the piezoelectric preset structure to form an interface layer with a preset thickness on the piezoelectric wafer or the piezoelectric preset structure, the method further comprises:
and carrying out film deposition on one side of the interface layer far away from the piezoelectric wafer or the piezoelectric preset structure so as to form a dielectric layer on the interface layer.
Further, before performing the first ion implantation or the ion beam irradiation on one side of the piezoelectric wafer or the piezoelectric preset structure to form an interface layer with a preset thickness on the piezoelectric wafer or the piezoelectric preset structure, the method further comprises:
And performing thin film deposition on one side of the piezoelectric wafer or the piezoelectric preset structure to form a dielectric layer on the piezoelectric wafer.
Further, after the annealing treatment is performed on the bonding structure, the method further comprises:
and flattening the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
In another aspect, an embodiment of the present application provides an acoustic wave device including the piezoelectric heterostructure described above and an interdigital electrode disposed on a surface of the piezoelectric heterostructure.
By implementing the application, the method has the following beneficial effects:
according to the method, the interface layer comprising the preset elements is arranged between the medium layer and the piezoelectric film layer, and the lattice structure in the interface layer is changed, so that bulk acoustic waves excited by the interdigital electrodes are scattered, the reflection of the bulk acoustic waves is reduced, the occurrence of interference on the acoustic surface waves due to the reflection of the bulk acoustic waves can be avoided, and the performance of the acoustic wave device can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a piezoelectric hetero-substrate structure according to an embodiment of the present application;
FIG. 2 is a graph showing half-width values of X-ray diffraction curves of a piezoelectric thin film layer according to an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for preparing a piezoelectric hetero-substrate structure according to an embodiment of the present application;
FIG. 4 is a graph showing a distribution of hydrogen ion concentration after implanting hydrogen ions with an implantation energy of 110keV and an implantation dose of 3.2E16 ions/cm2 into a lithium tantalate wafer in accordance with an embodiment of the present application;
fig. 5 is a schematic structural diagram of a piezoelectric hetero-substrate structure according to embodiment 1 in the preparation process of the piezoelectric hetero-substrate structure according to the embodiment of the present application;
fig. 6 is a schematic structural diagram of a piezoelectric heterostructure according to example 2 of the present application during fabrication;
fig. 7 is a schematic structural diagram of a piezoelectric heterostructure according to example 3 of the present application during fabrication;
fig. 8 is a schematic structural diagram of a piezoelectric hetero-substrate structure according to embodiment 4 in the preparation process of the piezoelectric hetero-substrate structure according to the embodiment of the present application;
fig. 9 is a schematic structural diagram of a piezoelectric heterostructure according to example 5 of the present application during fabrication;
Fig. 10 is a schematic structural diagram of a piezoelectric hetero-substrate structure according to embodiment 6 in the preparation process of the piezoelectric hetero-substrate structure according to the embodiment of the present application;
fig. 11 is a schematic structural diagram of a piezoelectric hetero-substrate structure according to embodiment 7 in the preparation process of the piezoelectric hetero-substrate structure according to the embodiment of the present application;
wherein, the reference numerals correspond to: 1-a functional substrate layer; 2-a piezoelectric composite layer; 21-a dielectric layer; 22-interfacial layer; 23-a piezoelectric thin film layer; 24-a charge trapping layer; 3-piezoelectric wafer; 4-functional substrate.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1-2, the following describes the technical solution of the present application in detail with reference to fig. 1-2.
The embodiment of the application provides a piezoelectric heterogeneous substrate structure, which specifically comprises a functional substrate layer 1 and a piezoelectric composite layer 2 arranged on the functional substrate layer 1.
The piezoelectric composite layer 2 comprises a dielectric layer 21, an interface layer 22 and a piezoelectric film layer 23 which are sequentially arranged along the direction far away from the functional substrate layer 1, wherein the interface layer 22 has preset element distribution, the concentration of preset elements is greater than a preset threshold value, and the interface layer 22 is used for scattering bulk acoustic waves excited by the interdigital electrodes.
In the embodiment of the application, the interface layer comprising the preset elements is arranged between the dielectric layer and the piezoelectric film layer, and the lattice structure in the interface layer is changed to realize scattering treatment on the bulk acoustic wave excited by the interdigital electrode, so that the reflection of the bulk acoustic wave is reduced, the interference of the reflected signal is further reduced, the deterioration of the device performance is restrained, the occurrence of the condition that the surface acoustic wave is interfered due to the reflection of the bulk acoustic wave is avoided, and the performance of the acoustic wave device is improved.
Specifically, when the bulk acoustic wave in the thickness direction of the material excited by the electrical signal released by the interdigital electrode propagates along the piezoelectric heterogeneous substrate structure, the preset element in the interface layer 22 can scatter the bulk acoustic wave propagated to the interface layer 22, so that the bulk acoustic wave propagates towards multiple directions, and meanwhile, the propagation energy of the bulk acoustic wave can be reduced, and further, the occurrence of the condition that the surface acoustic wave is interfered due to the reflection of the bulk acoustic wave can be avoided, and in a specific embodiment, the preset element in the interface layer 22 can be one or more of hydrogen element, helium element and argon element.
In an alternative embodiment, the concentration of the predetermined element in the interface layer 22 decreases linearly in a direction away from the dielectric layer 21; or; the concentration of the preset element in the interface layer 22 near the dielectric layer 21 and near the piezoelectric thin film layer 23 is smaller than the concentration of the preset element in the middle of the interface layer 22.
In a specific embodiment, the concentration distribution of the preset element in the interface layer 22 linearly decreases from the lower surface of the interface layer 22 near the dielectric layer 21 to the upper surface of the interface layer 22 near the piezoelectric thin film layer 23, and further, the concentration of the preset element in the interface layer 22 is set to linearly decrease along the direction far from the dielectric layer 21 so as to further enhance the scattering capability of the interface layer 22 on the bulk acoustic wave, and further, the performance of the acoustic wave device manufactured by using the piezoelectric heterogeneous substrate structure can be improved, wherein the preset element in the interface layer 22 is obtained by performing ion implantation on one side of the piezoelectric wafer 3 or one side of the piezoelectric preset structure, and further, the concentration value of the preset element in the interface layer 22 can be determined by controlling the energy and the implantation dose of the ion implantation.
In another embodiment, the concentration distribution of the preset element in the interface layer 22 from the lower surface of the interface layer 22 near the dielectric layer 21 to the upper surface of the interface layer 22 near the piezoelectric thin film layer 23 first shows a linearly increasing trend and then shows a linearly decreasing trend, and further, the concentration of the preset element in the interface layer 22 near the dielectric layer 21 and the concentration of the preset element near the piezoelectric thin film layer 23 are set to be smaller than the concentration of the preset element in the middle of the interface layer 22 so as to further enhance the scattering capability of the interface layer 22 on the bulk acoustic wave, wherein the position converted from the linearly increasing trend to the linearly decreasing trend is the middle position of the interface layer 22.
In practical applications, the concentration of the preset element in the interface layer 22 may range from 0.01% to 9.99%, the material of the interface layer 22 is the same as the material of the piezoelectric thin film layer 23, and illustratively, the material of the interface layer 22 and the material of the piezoelectric thin film layer 23 are at least one of lithium niobate, lithium tantalate, aluminum nitride, or quartz materials.
In an alternative embodiment, the side of the interface layer 22 near the dielectric layer 21 is a rough interface, and the rough interface layer 22 has a rough shape of 0 nm-40 nm.
Specifically, the interface of the high and low fluctuation is an irregular high and low fluctuation interface, and further, the side, close to the dielectric layer 21, of the interface layer 22 is set to be an irregular high and low fluctuation interface, so that the scattering capability of the interface layer 22 on bulk acoustic waves is further enhanced, and further, the performance of an acoustic wave device manufactured by using the piezoelectric heterogeneous substrate structure can be improved.
In some embodiments, the relief of the interface layer 22 may also be 1 nm-30 nm, 4 nm-30 nm, 5 nm-30 nm, 8 nm-35 nm, or 8 nm-40 nm, preferably the relief of the interface layer 22 is 1 nm-30 nm.
In practical applications, the half-width values of the X-ray diffraction curves of the interface layer 22 and the piezoelectric thin film layer 23 are respectively plotted, and it is known from the plotting results that the half-width values of the X-ray diffraction curves of the interface layer 22 and the piezoelectric thin film layer 23 differ by 5-15arcsec, and specifically, a plot of the half-width values of the X-ray diffraction curves of the piezoelectric thin film layer 23 can be seen in fig. 2, which is a plot of the half-width values of the X-ray diffraction curves of the piezoelectric thin film layer provided in the embodiments of the present application.
In some embodiments, the material of the interface layer 22 may be at least one of lithium niobate, lithium tantalate, aluminum nitride, or quartz, the thickness of the interface layer 22 may be 5nm-150nm, alternatively, the thickness of the interface layer 22 may be 5nm-50nm, 10nm-100nm, 15nm-120nm, or 5nm-150nm, etc., preferably, the thickness of the interface layer 22 is 10nm-100nm, and in some embodiments, the material of the interface layer 22 is the same as the material of the piezoelectric thin film layer 23, but the thickness of the interface layer 22 may be equal to or different from the thickness of the piezoelectric thin film layer 23, which is not limited in particular herein, and it should be noted that the piezoelectric thin film layer 23 has better crystal quality than the interface layer 22.
In some embodiments, the total thickness of the interface layer 22 and the piezoelectric thin film layer 23 is 50nm-15000nm, alternatively, the total thickness of the interface layer 22 and the piezoelectric thin film layer 23 is 50nm-8000nm, 100nm-10000nm, 150nm-15000nm, or the like, preferably, the total thickness of the interface layer 22 and the piezoelectric thin film layer 23 is 100nm-10000nm.
In some specific embodiments, the material of the dielectric layer 21 may be silicon dioxide or silicon nitride, and the thickness of the dielectric layer 21 may be 100nm to 900nm, and illustratively, the thickness of the dielectric layer 21 may also be 100nm to 800nm, 150nm to 850nm, 200nm to 800nm, or 250nm to 900nm, etc., and preferably, the thickness of the dielectric layer 21 is 200nm to 800nm.
In some specific embodiments, the material of the functional substrate layer 1 may be at least one of silicon, silicon oxide, silicon on insulator, sapphire, silicon carbide on insulator, quartz, aluminum nitride, gallium nitride, and diamond, where it is noted that the functional substrate layer 1 has a polished functional surface so as to prepare the dielectric layer 21 or the charge trapping layer 24 on the functional substrate layer 1.
In an alternative embodiment, the piezo-composite 2 further comprises a charge trapping layer 24, the charge trapping layer 24 being arranged on the side of the dielectric layer 21 remote from the interface layer 22.
Specifically, the charge trapping layer 24 is disposed between the dielectric layer 21 and the functional substrate layer 1, so that the influence of charge impurities on the piezoelectric heterogeneous substrate structure and the performance of the acoustic wave device can be effectively reduced, and the problems that some carrier impurities such as fixed charges and trapped charges are inevitably introduced in the preparation process of the dielectric layer 21, when the acoustic wave device prepared based on the regulation and control layer works at high frequency, the movable carriers move towards the functional substrate layer 1 and form a conductive layer on the surface of the functional substrate layer 1, so that the effective resistivity of the functional substrate layer 1 is reduced, the effective resistivity of the functional substrate layer 1 reacts on the acoustic wave device, the high-frequency loss is increased, the impedance mismatch is caused, the substrate crosstalk is increased, and the like are solved.
In a specific embodiment, the material of the charge trapping layer 24 is polysilicon, amorphous silicon or porous silicon, and in particular, when the material of the charge trapping layer 24 is amorphous silicon or polysilicon, the movable carriers can be pinned through the potential barrier between the grain boundaries due to the high density of defects and interface states between the energy bands of amorphous silicon or polysilicon, and when the material of the charge trapping layer 24 is porous silicon, the porous silicon can capture carriers through the composite pores, so that the influence of the charge impurities on the composite substrate and the device performance can be effectively reduced.
In some embodiments, polysilicon, amorphous silicon, or porous silicon may be prepared on the functional side of the functional substrate layer 1 by chemical vapor deposition or physical vapor deposition to form the charge trapping layer 24 on the functional side of the functional substrate layer 1.
In some embodiments, the thickness of the charge trapping layer 24 may be 150nm to 3000nm, alternatively, the thickness of the charge trapping layer 24 may be 150nm to 1000nm, 180nm to 1500nm, 200nm to 2000nm, or 200nm to 3000nm, etc., and preferably, the thickness of the charge trapping layer 24 is 200nm to 2000nm.
In an alternative embodiment, the charge trapping layer 24 is a rough or smooth interface on the side near the dielectric layer 21.
Specifically, when the surface of the charge trapping layer 24 is a smooth interface, planarization is performed on the upper surface of the charge trapping layer 24 to remove the charge trapping layer 24 with a thickness of 50nm-150nm, so as to reduce the influence of charge impurities on the performance of the piezoelectric hetero-substrate structure and the acoustic wave device, and when the surface of the charge trapping layer 24 is a rough interface, that is, when the surface of the charge trapping layer 24 is a rough interface, a bonding dielectric layer is prepared on the surface of the charge trapping layer 24, so as to reduce the influence of charge impurities on the performance of the piezoelectric hetero-substrate structure and the acoustic wave device.
In some embodiments, the thickness of the bonding dielectric layer is 100nm-200nm, and the material of the thin film layer can be silicon dioxide or silicon nitride.
The technical scheme of the embodiment of the application has the following technical effects:
according to the method, the interface layer comprising the preset elements is arranged between the medium layer and the piezoelectric film layer, and the lattice structure in the interface layer is changed, so that bulk acoustic waves excited by the interdigital electrodes are scattered, the reflection of the bulk acoustic waves is reduced, the occurrence of interference on the acoustic surface waves due to the reflection of the bulk acoustic waves can be avoided, and the performance of the acoustic wave device can be improved.
The embodiment of the application also provides a preparation method of the piezoelectric heterostructure, as shown in fig. 3, which is a schematic flow chart of the preparation method of the piezoelectric heterostructure, and the preparation method includes:
s10: the method comprises the steps of providing a piezoelectric precursor and a functional substrate 4, wherein the piezoelectric precursor comprises an interface layer 22, a dielectric layer 21 and a piezoelectric film layer 23, the interface layer 22 is provided with preset element distribution, and the concentration of preset elements is larger than a preset threshold value.
Wherein, the piezoelectric precursor is prepared by adopting the following modes:
s11: a piezoelectric wafer 3 or a piezoelectric preset structure is provided, and the piezoelectric preset structure is a bonded body of the piezoelectric wafer 3 and a silicon oxide material substrate.
S12: a first ion implantation or ion beam irradiation is performed on one side of the piezoelectric wafer 3 or the piezoelectric preset structure to form an interface layer 22 of a preset thickness on the piezoelectric wafer 3 or the piezoelectric preset structure.
S13: performing secondary ion implantation or grinding on one side of the piezoelectric wafer 3 or the piezoelectric preset structure to obtain a piezoelectric precursor with a piezoelectric film layer 23 and an interface layer 22; the implantation energy of the first ion implantation is not more than the implantation energy of the second ion implantation, the implantation dosage of the first ion implantation is not more than the implantation dosage of the second ion implantation, and the ions implanted by the first ion implantation and the ions implanted by the second ion implantation are all remained in the piezoelectric wafer 3.
S20: bonding the piezoelectric precursor and the functional substrate 4 to obtain a bonding structure comprising a piezoelectric precursor layer, a piezoelectric film layer 23, an interface layer 22, a dielectric layer 21 and a functional substrate layer 1, wherein the surface of the dielectric layer 21 far away from the interface layer 22 is a bonding surface;
s30: and carrying out secondary annealing treatment on the bonding structure, and flattening the surface of the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
Specifically, the piezoelectric wafer 3 may be a lithium niobate wafer or a lithium tantalate wafer, and the material of the functional substrate 4 may be at least one of silicon, silicon oxide, silicon on insulator, sapphire, silicon carbide on insulator, quartz, aluminum nitride, gallium nitride, and diamond, where it is noted that the functional substrate 4 has a polished functional surface so as to prepare the dielectric layer 21 or the charge trapping layer 24 on the functional substrate 4.
In an embodiment, the thickness of the piezoelectric wafer 3 may be 200um-1500um, alternatively, the thickness of the piezoelectric wafer 3 may be 200um-1000um, 300um-1000um, 400um-1500um, and the like, and preferably, the thickness of the piezoelectric wafer 3 is 300um-1000um.
In one embodiment, the piezoelectric preset structure is a structure obtained by bonding, grinding and flattening the piezoelectric wafer 3 and the silicon oxide material substrate.
In some embodiments, the first ion implantation implant ions include one or more of hydrogen ions, helium ions, and argon ions, and the predetermined thickness of the interface layer 22 may be 5nm to 150nm, and preferably, the predetermined thickness of the interface layer 22 is 10nm to 100nm.
In some embodiments, after step S12, it may further include
S13: thin film deposition is performed on the side of the interface layer 22 away from the piezoelectric wafer 3 or the piezoelectric preset structure to form a dielectric layer 21 on the interface layer 22.
Specifically, the piezoelectric wafer 3 or the piezoelectric preset structure with the interface layer 22 is placed in a pure nitrogen environment, and annealing and stripping treatment are performed in the pure nitrogen environment so as to prepare the dielectric layer 2 on the stripping surface of the interface layer 22, wherein the annealing temperature in the pure nitrogen environment is 300-600 ℃, and the annealing treatment time is more than or equal to 3 hours.
In some embodiments, the thin film deposition may be chemical vapor deposition or physical vapor deposition, the material of the thin film deposition is silicon dioxide or silicon nitride, the thickness of the prepared dielectric layer 21 is 300nm-1000nm, and after the dielectric layer 21 with the thickness of 300nm-1000nm is prepared, the dielectric layer 21 is subjected to planarization treatment, wherein the thickness of the planarization treatment is 100nm-200nm, and then the dielectric layer 21 with the thickness of 200nm-800nm is obtained.
It should be noted that, before executing step S13, the method may further include:
s101: the piezoelectric wafer 3 having the interface layer 22 is subjected to chamfering treatment so that the performance of the acoustic wave device manufactured using the piezoelectric hetero-substrate structure can be improved while beautifying the piezoelectric hetero-substrate structure.
Wherein, the width of the edge removed by chamfering is 0.5mm-2.5mm, and the depth of chamfering is 5um-30um.
In some embodiments, the implantation energy of the first ion implantation is less than or equal to the implantation energy of the second ion implantation, so that the ion region implanted by the first ion implantation can be traversed to reach the inside of the piezoelectric wafer 3 during the second ion implantation, so as to perform ion implantation delamination at the position where the implantation damage of the second ion implantation is highest.
In practical applications, as shown in FIG. 4, the implant energy provided in the examples of the present application is 110keV, and the implant dose is 3.2E16 ions/cm 2 As can be seen from fig. 4, the hydrogen ion concentration profile after the hydrogen ion implantation into the lithium tantalate wafer is the peak in fig. 4 where the hydrogen ion implantation damage is highest.
In some embodiments, the ions implanted by the second ion implantation include one or more of hydrogen ions, helium ions and argon ions, the implantation energy of the second ion implantation is 40KeV-400KeV, and the implantation dose is 1E14 ions/cm 2 -1E17 ions/cm 2 。
Further, when the bonding structure is stripped by using the ion implantation stripping mode, secondary annealing treatment is required, wherein the temperature of the primary annealing treatment is 100-200 ℃, the atmosphere of the primary annealing treatment can be nitrogen, argon or vacuum environment, and the like, the temperature of the secondary annealing treatment is 250-650 ℃, the atmosphere of the secondary annealing treatment can be nitrogen, oxygen, argon or vacuum environment, and the like, the purpose of the primary annealing treatment is to realize bonding reinforcement, and the purpose of the secondary annealing treatment is to repair damage caused during the secondary ion implantation.
After the piezoelectric heterogeneous substrate structure is obtained, the residual piezoelectric wafer 3 or the piezoelectric preset structure can be recycled, so that the waste of the piezoelectric wafer 3 and the piezoelectric preset structure is reduced, and the production cost is saved.
In another alternative embodiment, after step S20, the method further includes: and flattening the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
Specifically, the piezoelectric heterostructure and the peeled substrate structure can be obtained by flattening the bonding structure, wherein the substrate structure is an unutilized piezoelectric wafer 3 or a piezoelectric preset structure, and it should be noted that when peeling the piezoelectric heterostructure and the substrate structure is realized by polishing, only one annealing treatment is required for the bonding structure, wherein the purpose of the annealing treatment is to realize bonding reinforcement.
In an alternative embodiment, polysilicon, amorphous silicon or porous silicon may also be prepared on the functional surface of the functional substrate layer 1 by chemical vapor deposition or physical vapor deposition to form the charge trapping layer 24 on the functional surface of the functional substrate layer 1, wherein by disposing the charge trapping layer 24 between the dielectric layer 21 and the functional substrate layer 1, the influence of charge impurities on the performance of the piezoelectric heterostructure and the acoustic wave device may be reduced.
In an alternative embodiment, before step S12, the method may further include:
thin film deposition is performed on one side of the piezoelectric wafer 3 or the piezoelectric preset structure to form a dielectric layer 21 on the piezoelectric wafer 3.
Specifically, the dielectric layer 21 may be formed on the piezoelectric wafer 3 or the piezoelectric preset structure first, and then ion implantation is performed twice to obtain the piezoelectric precursor.
In practical applications, the preparation method may include:
s111: thin film deposition is performed on one side of the piezoelectric wafer 3 or the piezoelectric preset structure to form a dielectric layer 21 on the piezoelectric wafer 3 or the piezoelectric preset structure.
S112: ion implantation is performed twice on the side of the dielectric layer 21 away from the piezoelectric wafer 3 or the piezoelectric preset structure to obtain a piezoelectric precursor having an interface layer 22 and a piezoelectric thin film layer 23.
Specifically, the first ion implantation is to form the interface layer 22, the second ion implantation is to perform ion implantation stripping, and the most damaged part of the second ion implantation is stripped, so that a piezoelectric thin film layer 23 is formed on one side of the interface layer 22 away from the dielectric layer 21, ions implanted by the second ion implantation penetrate through the dielectric layer 21 to reach the inside of the piezoelectric wafer 3 or the piezoelectric preset structure, the retention layer of the ions in the first ion implantation is positioned on one side close to the dielectric layer 21, the retention layer of the ions in the second ion implantation is positioned on one side of the retention layer of the ions in the first ion implantation away from the dielectric layer 21, and a gap with a preset distance exists between the retention layer of the ions in the first ion implantation and the retention layer of the ions in the second ion implantation.
The above preparation method is described in detail with reference to specific examples.
Example 1:
the embodiment discloses a method for preparing a piezoelectric hetero-substrate structure, please refer to fig. 5, fig. 5 is a schematic structural diagram of the piezoelectric hetero-substrate structure in the preparation process corresponding to embodiment 1 provided in the embodiment of the application, and the method comprises the following steps:
s1: a lithium niobate wafer 3 and a silicon monoxide functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium niobate wafer 3 to form an interface layer 22 of a predetermined thickness on the lithium niobate wafer 3.
S3: the lithium niobate wafer 3 having the interface layer 22 is subjected to annealing and peeling treatment, and thin film deposition is performed on the peeled surface of the interface layer 22 away from the lithium niobate wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: a second ion implantation is performed on one side of the lithium niobate wafer 3.
Referring to fig. 5, the arrow direction in fig. 5 is the direction of ion implantation.
S5: the lithium niobate wafer 3 having the dielectric layer 21 and the silicon monoxide functional substrate 4 are bonded to obtain a bonded structure including the lithium niobate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23 and the silicon monoxide functional substrate layer 1.
S6: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium niobate wafer 3.
S7: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 2:
the embodiment discloses a method for preparing a piezoelectric heterostructure, please refer to fig. 6, fig. 6 is a schematic structural diagram of the piezoelectric heterostructure in the preparation process corresponding to embodiment 2 provided in the embodiment of the present application, and the method includes the following steps:
S1: a lithium tantalate wafer 3 and a monocrystalline silicon functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium tantalate wafer 3 to form an interfacial layer 22 of a predetermined thickness on the lithium niobate wafer 3.
S3: the lithium tantalate wafer 3 having the interface layer 22 is annealed and lift-off, and thin film deposition is performed on the lift-off surface of the interface layer 22 away from the lithium tantalate wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: a second ion implantation is performed on one side of the lithium tantalate wafer 3.
Referring to fig. 6, the arrow direction in fig. 6 is the direction of ion implantation.
S5: the functional surface of the single crystal silicon functional substrate 4 is subjected to thin film deposition to form the charge trapping layer 24 on the functional surface of the single crystal silicon functional substrate 4.
Wherein the charge trapping layer 24 has a smooth interface on a side near the dielectric layer 21.
S6: the lithium tantalate wafer 3 having the dielectric layer 21 and the single crystal silicon functional substrate 4 having the charge trapping layer 24 are bonded to obtain a bonded structure including the lithium tantalate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23, the charge trapping layer 24 and the single crystal silicon functional substrate 4.
S7: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium tantalate wafer 3.
S8: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 3:
the embodiment discloses a method for preparing a piezoelectric heterostructure, please refer to fig. 7, fig. 7 is a schematic structural diagram of the piezoelectric heterostructure in the preparation process corresponding to embodiment 3 provided in the embodiment of the present application, and the method includes the following steps:
s1: a lithium niobate wafer 3 and a monocrystalline silicon functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium niobate wafer 3 to form an interface layer 22 of a predetermined thickness on the lithium niobate wafer 3.
S3: the lithium niobate wafer 3 having the interface layer 22 is subjected to annealing and peeling treatment, and thin film deposition is performed on the peeled surface of the interface layer 22 away from the lithium niobate wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: a second ion implantation is performed on one side of the lithium niobate wafer 3.
Referring to fig. 7, the arrow direction in fig. 7 is the direction of ion implantation.
S5: the functional surface of the single crystal silicon functional substrate 4 is subjected to thin film deposition to form the charge trapping layer 24 on the functional surface of the single crystal silicon functional substrate 4.
Wherein, the charge trapping layer 24 is near the dielectric layer 21 and has a rough interface.
S6: a thin film deposition is performed on the side of the charge trapping layer 24 remote from the monocrystalline silicon functional substrate 4 to form a bonding dielectric layer on the charge trapping layer 24 and planarize the bonding dielectric layer.
S7: the lithium niobate wafer 3 having the dielectric layer 21 and the single crystal silicon functional substrate 4 having the charge trapping layer 24 are bonded to obtain a bonded structure including the lithium niobate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23, the charge trapping layer 24, the bonded dielectric layer, and the single crystal silicon functional substrate 4.
S8: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium niobate wafer 3.
S9: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 4:
the embodiment discloses a method for preparing a piezoelectric hetero-substrate structure, please refer to fig. 8, fig. 8 is a schematic structural diagram of the piezoelectric hetero-substrate structure in the preparation process corresponding to embodiment 4 provided in the embodiment of the present application, and the method comprises the following steps:
s1: a lithium tantalate wafer 3 and a silicon monoxide functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium tantalate wafer 3 to form an interfacial layer 22 of a predetermined thickness on the lithium tantalate wafer 3.
S3: the lithium tantalate wafer 3 having the interface layer 22 is annealed and delaminated, and thin film deposition is performed on the delaminated surface of the interface layer 22 away from the piezoelectric wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: the lithium tantalate wafer 3 having the dielectric layer 21 and the silicon monoxide functional substrate 4 are bonded to obtain a bonded structure including the lithium tantalate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23 and the silicon monoxide functional substrate layer 1.
S5: the bonded structure is subjected to an annealing treatment and a grinding treatment to obtain an initial piezoelectric heterosubstrate structure and a stripped unused lithium tantalate wafer 3.
S6: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 5:
the embodiment discloses a method for preparing a piezoelectric heterostructure, please refer to fig. 9, fig. 9 is a schematic structural diagram of the piezoelectric heterostructure in the preparation process corresponding to embodiment 5 provided in the embodiment of the present application, and the method includes the following steps:
S1: a lithium niobate composite structure 3 and a silicon monoxide functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium niobate composite structure 3 to form an interface layer 22 of a predetermined thickness on the lithium niobate composite structure 3.
S3: the lithium niobate composite structure 3 having the interface layer 22 is annealed and peeled off, and thin film deposition is performed on the peeled off face of the interface layer 22 away from the piezoelectric wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: a second ion implantation is performed on one side of the lithium niobate composite structure 3.
Referring to fig. 9, the arrow direction in fig. 9 is the direction of ion implantation.
S5: the lithium niobate composite structure 3 having the dielectric layer 21 and the silicon monoxide functional substrate 4 are bonded to obtain a bonded structure including the lithium niobate composite structure layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23 and the silicon monoxide functional substrate layer 1.
S6: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium niobate composite structure 3.
S7: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 6:
the embodiment discloses a method for preparing a piezoelectric hetero-substrate structure, please refer to fig. 10, fig. 10 is a schematic structural diagram of the piezoelectric hetero-substrate structure in the preparation process corresponding to embodiment 6 provided in the embodiment of the present application, and the method for preparing the piezoelectric hetero-substrate structure comprises the following steps:
s1: a lithium tantalate wafer 3 and a sapphire functional substrate 4 are provided.
S2: a first ion implantation is performed on one side of the lithium tantalate wafer 3 to form an interfacial layer 22 of a predetermined thickness on the lithium tantalate wafer 3.
S3: the lithium tantalate wafer 3 having the interface layer 22 is annealed, stripped, and chamfered, and thin film deposition is performed on the stripped side of the interface layer 22 away from the piezoelectric wafer 3 to form the dielectric layer 21 on the interface layer 22.
S4: a second ion implantation is performed on one side of the lithium tantalate wafer 3.
Referring to fig. 10, the arrow direction in fig. 10 is the direction of ion implantation.
S5: the lithium tantalate wafer 3 having the dielectric layer 21 and the sapphire functional substrate 4 are bonded to obtain a bonded structure including the lithium tantalate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23 and the sapphire functional substrate layer 1.
S6: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium tantalate wafer 3.
S7: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Example 7:
the embodiment discloses a method for preparing a piezoelectric hetero-substrate structure, please refer to fig. 11, fig. 11 is a schematic structural diagram of the piezoelectric hetero-substrate structure in the preparation process corresponding to embodiment 7 provided in the embodiment of the present application, and the method for preparing the piezoelectric hetero-substrate structure comprises the following steps:
s1: a lithium tantalate wafer 3 and a sapphire functional substrate 4 are provided.
S2: thin film deposition is performed on one side of the lithium tantalate wafer 3 to form a dielectric layer 21 on the lithium tantalate wafer 3.
S3: a secondary ion implantation is performed on one side of the lithium tantalate wafer 3 to form an interface layer 22 and a piezoelectric thin film layer 23 of a predetermined thickness on the lithium tantalate wafer 3.
Referring to fig. 11, the arrow direction in fig. 11 is the direction of ion implantation, the implantation energy of the second ion implantation is 10 times or more the implantation energy of the first ion implantation, and the implantation dose of the second ion implantation is equal to or more the implantation dose of the first ion implantation.
S4: the lithium tantalate wafer 3 having the interface layer 22 and the piezoelectric thin film layer 23 is bonded with the sapphire functional substrate 4 to obtain a bonded structure including the lithium tantalate wafer layer, the dielectric layer 21, the interface layer 22, the piezoelectric thin film layer 23 and the sapphire functional substrate layer 1.
S5: and carrying out secondary annealing treatment on the bonding structure, and stripping at the position with the highest damage of the secondary ion implantation to obtain the initial piezoelectric heterostructure and the stripped unused lithium tantalate wafer 3.
S6: and flattening the initial piezoelectric heterostructure to obtain the target piezoelectric heterostructure.
Another aspect of the disclosed embodiments provides an acoustic wave device comprising a piezoelectric heterostructure as described above and an interdigital electrode, wherein the interdigital electrode is disposed on a surface of the piezoelectric heterostructure.
Specifically, the interdigital electrode is provided on the upper surface of the piezoelectric thin film layer 23 so that the surface acoustic wave is excited by releasing an electric signal with the interdigital electrode.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (14)
1. A piezoelectric heterogeneous substrate structure, characterized by comprising a functional substrate layer (1) and a piezoelectric composite layer (2) arranged on the functional substrate layer (1);
The piezoelectric composite layer (2) comprises a dielectric layer (21), an interface layer (22) and a piezoelectric film layer (23) which are sequentially arranged along the direction far away from the functional substrate layer (1), wherein the interface layer (22) has preset element distribution, the concentration of the preset element is larger than a preset threshold value, and the interface layer (22) is used for carrying out scattering treatment on bulk acoustic waves excited by the interdigital electrodes.
2. The piezoelectric heterostructure of claim 1, wherein the concentration of the preset element in the interface layer (22) decreases linearly in a direction away from the dielectric layer (21); or;
the concentration of the preset element in the interface layer (22) is smaller than that of the preset element in the middle of the interface layer (22) at the position close to the dielectric layer (21) and the position close to the piezoelectric film layer (23).
3. The piezoelectric heterosubstrate structure according to claim 1, characterized in that the concentration of the preset elements in the interface layer (22) ranges from 0.01% to 9.99%, the material of the interface layer (22) being the same as the material of the piezoelectric thin film layer (23).
4. A piezoelectric heterosubstrate structure according to any one of claims 1 to 3, characterized in that the interface layer (22) has a height-undulating interface on a side thereof adjacent to the dielectric layer (21), the height-undulating interface layer (22) having a waviness of 0 nm to 40 nm.
5. The piezoelectric heterostructure of claim 1, wherein the piezoelectric composite layer (2) further includes a charge trapping layer (24), the charge trapping layer (24) being disposed on a side of the dielectric layer (21) remote from the interface layer (22).
6. The piezoelectric heterosubstrate structure of claim 5, wherein a side of the charge trapping layer (24) adjacent to the dielectric layer (21) is a rough or smooth interface.
7. The piezoelectric heterostructure of claim 4, wherein the material of the charge trapping layer (24) is polysilicon, amorphous silicon or porous silicon.
8. The piezoelectric heterogeneous substrate structure according to claim 1, wherein the preset element is one or more of hydrogen element, helium element and argon element, the material of the interface layer (22) is at least one of lithium niobate, lithium tantalate, aluminum nitride or quartz material, and the material of the functional substrate layer (1) is at least one of silicon, silicon oxide, silicon on insulator, sapphire, silicon carbide on insulator, quartz, aluminum nitride, gallium nitride and diamond.
9. A method for preparing a piezoelectric heterostructure, characterized in that the method is used for preparing a piezoelectric heterostructure according to any one of claims 1 to 8, the method comprising:
Providing a piezoelectric precursor and a functional substrate (4), wherein the piezoelectric precursor comprises an interface layer (22), a dielectric layer (21) and a piezoelectric film layer (23), the interface layer (22) has preset element distribution, and the concentration of the preset element is larger than a preset threshold value;
bonding the piezoelectric precursor and the functional substrate (4) to obtain a bonding structure comprising the piezoelectric precursor layer, the piezoelectric film layer (23), the interface layer (22), the dielectric layer (21) and the functional substrate layer (1), wherein the surface of the dielectric layer (21) far away from the interface layer (22) is a bonding surface;
and carrying out secondary annealing treatment on the bonding structure, and flattening the surface of the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
10. The method of claim 9, wherein the piezoelectric precursor is prepared by:
providing a piezoelectric wafer (3) or a piezoelectric preset structure, wherein the piezoelectric preset structure is a bonding body of the piezoelectric wafer (3) and a silicon oxide material substrate;
performing a first ion implantation or ion beam irradiation on one side of the piezoelectric wafer (3) or the piezoelectric preset structure to form an interface layer (22) with a preset thickness on the piezoelectric wafer (3) or the piezoelectric preset structure;
Performing a second ion implantation or grinding on one side of the piezoelectric wafer (3) or the piezoelectric preset structure to obtain the piezoelectric precursor with the piezoelectric thin film layer (23) and the interface layer (22);
the implantation energy of the first ion implantation is not more than the implantation energy of the second ion implantation, the implantation dosage of the first ion implantation is not more than the implantation dosage of the second ion implantation, and the ions implanted by the first ion implantation and the ions implanted by the second ion implantation are all remained in the piezoelectric wafer (3).
11. The method according to claim 10, characterized in that after performing a first ion implantation or ion beam irradiation on one side of the piezoelectric wafer (3) or the piezoelectric preset structure to form an interface layer (22) of a preset thickness on the piezoelectric wafer (3) or the piezoelectric preset structure, it further comprises:
film deposition is carried out on the side of the interface layer (22) remote from the piezoelectric wafer (3) or the piezoelectric preset structure so as to form a dielectric layer (21) on the interface layer (22).
12. The method according to claim 10, characterized in that before said subjecting one side of said piezoelectric wafer (3) or said piezoelectric preset structure to a first ion implantation or ion beam irradiation, to form an interface layer (22) of preset thickness on said piezoelectric wafer (3) or said piezoelectric preset structure, it further comprises:
Film deposition is performed on one side of the piezoelectric wafer (3) or the piezoelectric preset structure to form a dielectric layer (21) on the piezoelectric wafer (3).
13. The method of manufacturing according to claim 10, further comprising, after the primary annealing treatment of the bonded structure:
and flattening the bonding structure to obtain the piezoelectric heterogeneous substrate structure.
14. An acoustic wave device comprising a piezoelectric heterostructure according to any one of claims 1 to 8 and an interdigital electrode disposed on a surface of the piezoelectric heterostructure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311695566.6A CN117897035A (en) | 2023-12-11 | 2023-12-11 | Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311695566.6A CN117897035A (en) | 2023-12-11 | 2023-12-11 | Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117897035A true CN117897035A (en) | 2024-04-16 |
Family
ID=90651427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311695566.6A Pending CN117897035A (en) | 2023-12-11 | 2023-12-11 | Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117897035A (en) |
-
2023
- 2023-12-11 CN CN202311695566.6A patent/CN117897035A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10672645B2 (en) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition | |
| EP3221884B1 (en) | High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof | |
| CN100530531C (en) | A method of fabricating a composite substrate | |
| KR101635151B1 (en) | Piezoelectric device and method of manufacturing piezoelectric device | |
| CN110880920B (en) | Preparation method of heterogeneous thin film structure | |
| WO2018080772A1 (en) | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency | |
| EP2270839B1 (en) | Method for manufacturing bonded substrate | |
| CN111865250B (en) | POI substrate, high-frequency acoustic wave resonator and preparation method thereof | |
| CN112260660B (en) | Composite substrate, composite film and preparation method thereof | |
| CN111512549B (en) | Bonded body of piezoelectric material substrate and support substrate and method for manufacturing the same | |
| CN112236853A (en) | Substrate for integrated radio frequency device and manufacturing method thereof | |
| CN117897035A (en) | Piezoelectric heterogeneous substrate structure, preparation method and acoustic wave device | |
| CN116193965A (en) | Preparation method and preparation device of vertical integrated wafer and vertical integrated wafer | |
| CN112688658B (en) | Piezoelectric substrate, preparation method and electronic component | |
| US20240030883A1 (en) | Process for manufacturing a piezoelectric structure for a radiofrequency device and which can be used to transfer a piezoelectric layer, and process for transferring such a piezoelectric layer | |
| CN114214732A (en) | Method for improving polarization reversal phenomenon on surface of composite film and composite film | |
| CN114388688A (en) | Blackened single crystal piezoelectric composite film based on plasma etching and preparation method thereof | |
| CN114122250A (en) | Blackened single crystal piezoelectric composite film and preparation method thereof | |
| CN111492577B (en) | Bonded body of piezoelectric material substrate and support substrate and method for manufacturing the same | |
| CN113540338A (en) | Piezoelectric composite film and preparation method thereof | |
| CN117529209A (en) | Piezoelectric composite structure, preparation method and acoustic wave device | |
| US12003227B2 (en) | Composite substrate, piezoelectric device, and method for manufacturing composite substrate | |
| CN112564662B (en) | Composite substrate, preparation method thereof and electronic component | |
| US20230291377A1 (en) | Process for manufacturing a piezoelectric structure for a radiofrequency device which structure can be used to transfer a piezoelectric layer, and process for transferring such a piezoelectric layer | |
| EP3831988A1 (en) | Composite substrate, piezoelectric element, and method for manufacturing composite substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |