CN117896037A

CN117896037A - Data processing method and data processing device

Info

Publication number: CN117896037A
Application number: CN202211255691.0A
Authority: CN
Inventors: 严增超; 黄科超; 马会肖; 杨小玲
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2024-04-16
Also published as: WO2024078048A1

Abstract

The embodiment of the application provides a data processing method and a data processing device, which are beneficial to reducing the time delay of a receiving end and can adapt to more PMD types. The method comprises the following steps: and respectively decoding the z first data streams to obtain z second data streams, wherein the z first data streams are subjected to Forward Error Correction (FEC) coding, and z is an integer greater than 1. And deconvolution interleaving is respectively carried out on the z second data streams to obtain z third data streams. And respectively performing AM locking on the z third data streams according to the second alignment mark AM set to obtain z fourth data streams, wherein the second AM set is obtained by transforming a first AM set preset by a transmitting end, the first AM set comprises x first AM subsets, x is an integer greater than 1, the second AM set comprises z second AM subsets, and the z second AM subsets are used for respectively performing AM locking with the z third data streams.

Description

Data processing method and data processing device

Technical Field

The present disclosure relates to the field of communications, and in particular, to a data processing method and a data processing apparatus.

Background

Optical communication systems and optical transport networks (optical transport network, OTN) are evolving towards high capacity and ultra-high speed under the continuous push of 5G, cloud computing, big data, artificial intelligence, etc. The transmitted data is error corrected by adopting forward error correction coding (forward error correction, FEC), so that transmission error codes can be solved, and original data sent by a transmitting end can be recovered from received data.

There is currently proposed a transmission scheme of concatenated FEC, where an originating device and an originating processing module are connected by a connection unit interface (attachment unit interface, AUI). The transmitting device performs outer code encoding on the data to be transmitted, and sends the data after outer code encoding to the transmitting processing module. The transmitting end processing module carries out inner code encoding on the data after the outer code encoding, and transmits the data after the inner code encoding to the data receiving end through a channel. Specifically, the originating processing module receives multiple paths of data streams encoded by the outer codes, and performs Alignment Marker (AM) locking, lane Permutation (Lane Permulation) and convolutional interleaving on the multiple paths of data streams, then performs inner code encoding on each path of data stream after convolutional interleaving, and then frames the data stream after inner code encoding to the receiving end after DSP framing processing.

The data stream received by the receiving end is firstly subjected to DSP framing treatment, then is subjected to internal code decoding and deconvolution interleaving, and the deconvolution interleaving data stream is further subjected to De-Lane Permulation. In the scheme, due to the fact that DSP framing processing is set, channels can be aligned by a receiving end, data among the channels are not disordered, however, complexity of the DSP framing processing is high, delay is not reduced, and types of physical medium association layers (Physical Media Dependent, PMD) applicable to the DSP framing processing are single.

Disclosure of Invention

The embodiment of the application provides a data processing method and a data processing device, which are beneficial to reducing the time delay of a receiving end and can adapt to more PMD types.

In a first aspect, an embodiment of the present application provides a data processing method, including the following steps. And respectively decoding the z first data streams to obtain z second data streams, wherein the z first data streams are subjected to Forward Error Correction (FEC) coding, and z is an integer greater than 1. And deconvolution interleaving is respectively carried out on the z second data streams to obtain z third data streams. And respectively performing AM locking on the z third data streams according to a second alignment mark AM set to obtain z fourth data streams, wherein the second AM set is obtained by transforming a first AM set preset by a transmitting end, the first AM set comprises x first AM subsets, x is an integer greater than 1, the second AM set comprises z second AM subsets, and the z second AM subsets are used for respectively performing AM locking with the z third data streams.

In some possible embodiments, x=32, z=32, each of the first AM subsets comprises 12 symbols, each of the second AM subsets comprises 12 symbols, and the first AM set transforms to the second AM set satisfying equation 1 as follows:

AM_out<i,j>＝AM_in<(i+16*Floor(j/2))％32,j>

Wherein am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th second AM subset in the second AM set, floor (j/2) represents a quotient of j divided by 2 rounded down, 16 x Floor (j/2))%32 represents a remainder of 16 x Floor (j/2)) divided by 32, 0.ltoreq.i.ltoreq.31, 0.ltoreq.j.ltoreq.11.

In some possible embodiments, each of the second AM subsets includes 15 bytes, and the 15 bytes of each of the second AM subsets are represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of CM0, CM1, CM2, CM3, CM4, and CM5 in the second AM subset are used to match in order with the total of 6 bytes of 0 th byte, 1 st byte, 2 nd byte, 4 th byte, 5 th byte, and 6 th byte, respectively, in every 7 consecutive bytes of the third data stream for AM locking.

In some possible embodiments, if the number of successful matches in the 6 matches performed by the second AM subset and the third data stream respectively is greater than or equal to P, then one AM valid is achieved; and if the AM is valid for R times, the AM locking condition of the third data stream is achieved. If the number of successful matches in the 6 matches performed by the second AM subset and the third data stream is less than P, one AM failure is realized; and if the AM failure is realized for S times, the AM unlocking condition of the third data stream is achieved. Wherein p=3, 4 or 5, r=1 or 2, s=2, 3, 4 or 5.

In some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and carrying out channel reordering on the z fourth data streams according to the second AM set so as to enable the z fourth data streams to be arranged according to a preset sequence. The z second AM subsets are used for respectively matching with the AM in the z fourth data streams, each second AM subset has a corresponding channel number, and the fourth data streams are arranged according to the channel numbers of the successfully matched second AM subsets.

In some possible embodiments, each of the second AM subsets includes 15 bytes, and the 15 bytes of each of the second AM subsets are represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of UM0, UM1, UM2, UM3, UM4, and UM5 in the second AM subset are used to match 6 bytes of the corresponding location in the AM of the fourth data stream, respectively.

In some possible embodiments, x=32, z=32, and the 32 second AM subsets in the second AM set are in order of channel number:

{0x9A，0x4A，0x26，0xB6，0x65，0xB5，0xD9，0xD9，0x01，0x8E，0xF3，0x26，0xF1，0x71，0xF3}，

{0x9A，0x4A，0x26，0x04，0x65，0xB5，0xD9，0x67，0x5A，0x21，0x7E，0x98，0xAA，0xDE，0x7E}，

{0x9A，0x4A，0x26，0x46，0x65，0xB5，0xD9，0xFE，0x3E，0x0C，0x56，0x01，0xCE，0xF3，0x56}，

{0x9A，0x4A，0x26，0x5A，0x65，0xB5，0xD9，0x84，0x86，0x7F，0xD0，0x7B，0x76，0x80，0xD0}，

{0x9A，0x4A，0x26，0xE1，0x65，0xB5，0xD9，0x19，0x2A，0xAE，0xF2，0xE6，0xDA，0x51，0xF2}，

{0x9A，0x4A，0x26，0xF2，0x65，0xB5，0xD9，0x4E，0x12，0xB0，0xD1，0xB1，0xE2，0x4F，0xD1}，

{0x9A，0x4A，0x26，0x3D，0x65，0xB5，0xD9，0xEE，0x42，0x63，0xA1，0x11，0xB2，0x9C，0xA1}，

{0x9A，0x4A，0x26，0x22，0x65，0xB5，0xD9，0x32，0xD6，0x89，0x5B，0xCD，0x26，0x76，0x5B}，

{0x9A，0x4A，0x26，0x60，0x65，0xB5，0xD9，0x9F，0xE1，0x8C，0x75，0x60，0x11，0x73，0x75}，

{0x9A，0x4A，0x26，0x6B，0x65，0xB5，0xD9，0xA2，0x71，0x3B，0x3C，0x5D，0x81，0xC4，0x3C}，

{0x9A，0x4A，0x26，0xFA，0x65，0xB5，0xD9，0x04，0x95，0x14，0xD8，0xFB，0x65，0xEB，0xD8}，

{0x9A，0x4A，0x26，0x6C，0x65，0xB5，0xD9，0x71，0x22，0x99，0x38，0x8E，0xD2，0x66，0x38}，

{0x9A，0x4A，0x26，0x18，0x65，0xB5，0xD9，0x5B，0xA2，0x09，0x95，0xA4，0x52，0xF6，0x95}，

{0x9A，0x4A，0x26，0x14，0x65，0xB5，0xD9，0xCC，0x31，0x68，0xC3，0x33，0xC1，0x97，0xC3}，

{0x9A，0x4A，0x26，0xD0，0x65，0xB5，0xD9，0xB1，0xCA，0x04，0xA6，0x4E，0x3A，0xFB，0xA6}，

{0x9A，0x4A，0x26，0xB4，0x65，0xB5，0xD9，0x56，0xA6，0x45，0x79，0xA9，0x56，0xBA，0x79}，

{0x9A，0x4A，0x26，0xB6，0x65，0xB5，0xD9，0xD9，0xFE，0x71，0x0C，0x26，0x0E，0x8E，0x0C}，

{0x9A，0x4A，0x26，0x04，0x65，0xB5，0xD9，0x67，0xA5，0xDE，0x81，0x98，0x55，0x21，0x81}，

{0x9A，0x4A，0x26，0x46，0x65，0xB5，0xD9，0xFE，0xC1，0xF3，0xA9，0x01，0x31，0x0C，0xA9}，

{0x9A，0x4A，0x26，0x5A，0x65，0xB5，0xD9，0x84，0x79，0x80，0x2F，0x7B，0x89，0x7F，0x2F}，

{0x9A，0x4A，0x26，0xE1，0x65，0xB5，0xD9，0x19，0xD5，0x51，0x0D，0xE6，0x25，0xAE，0x0D}，

{0x9A，0x4A，0x26，0xF2，0x65，0xB5，0xD9，0x4E，0xED，0x4F，0x2E，0xB1，0x1D，0xB0，0x2E}，

{0x9A，0x4A，0x26，0x3D，0x65，0xB5，0xD9，0xEE，0xBD，0x9C，0x5E，0x11，0x4D，0x63，0x5E}，

{0x9A，0x4A，0x26，0x22，0x65，0xB5，0xD9，0x32，0x29，0x76，0xA4，0xCD，0xD9，0x89，0xA4}，

{0x9A，0x4A，0x26，0x60，0x65，0xB5，0xD9，0x9F，0x1E，0x73，0x8A，0x60，0xEE，0x8C，0x8A}，

{0x9A，0x4A，0x26，0x6B，0x65，0xB5，0xD9，0xA2，0x8E，0xC4，0xC3，0x5D，0x7E，0x3B，0xC3}，

{0x9A，0x4A，0x26，0xFA，0x65，0xB5，0xD9，0x04，0x6A，0xEB，0x27，0xFB，0x9A，0x14，0x27}，

{0x9A，0x4A，0x26，0x6C，0x65，0xB5，0xD9，0x71，0xDD，0x66，0xC7，0x8E，0x2D，0x99，0xC7}，

{0x9A，0x4A，0x26，0x18，0x65，0xB5，0xD9，0x5B，0x5D，0xF6，0x6A，0xA4，0xAD，0x09，0x6A}，

{0x9A，0x4A，0x26，0x14，0x65，0xB5，0xD9，0xCC，0xCE，0x97，0x3C，0x33，0x3E，0x68，0x3C}，

{0x9A，0x4A，0x26，0xD0，0x65，0xB5，0xD9，0xB1，0x35，0xFB，0x59，0x4E，0xC5，0x04，0x59}，

{0x9A，0x4A，0x26，0xB4，0x65，0xB5，0xD9，0x56，0x59，0xBA，0x86，0xA9，0xA9，0x45，0x86}。

In some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and performing de-channel replacement on the z fourth data streams to obtain z fifth data streams.

In some possible embodiments, z=32, each of the fourth data streams includes a plurality of symbol sets, each of the fifth data streams includes a plurality of symbol sets, each of the symbol sets includes two consecutive symbols, the first symbol set and the second symbol set in each of the fourth data streams are adjacent, and the first symbol set and the second symbol set in each of the fifth data streams are adjacent. The first symbol set in the fifth data stream a is from the first symbol set in the fourth data stream a, the first symbol set in the fifth data stream a is the same as the first symbol set in the fourth data stream a, the second symbol set in the fifth data stream a is from the second symbol set in the fourth data stream (a+16)% 32, the second symbol set in the fifth data stream a is the same as the second symbol set in the fourth data stream (a+16)% 32, wherein 0.ltoreq.a is no more than 31, and (a+16)% 32 represents the remainder after dividing a+16 by 32.

In some possible embodiments, x=32, z=8, each of the first AM subsets comprises 480 bits, each of the second AM subsets comprises 480 bits, and the first AM set transforms to the second AM set satisfying equation 2 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

wherein am_in < i, j > represents the j-th bit of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th bit of the i-th second AM subset in the second AM set, floor ((j% 4)/2) represents the quotient of (j% 4)/2 rounded down, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor (j/4) represents the quotient of j/4 rounded down, 0.ltoreq.i.ltoreq.7, 0.ltoreq.j.ltoreq.479.

In some possible embodiments, the 8 second AM subsets in the second AM set are in order of channel number:

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0x50,0x0F,0x55,0x50,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0xAF,0x5A,0xA5,0x5F,0x96,0x93,0x39,0x39,0x69,0x66,0x93,0x63,0x39,0x66,0x33,0x93,0x50,0xA5,0x5A,0xA0,0x69,0x6C,0xC6,0xC6,0x96,0x99,0x6C,0x9C,0xC6,0x99,0xCC,0x6C}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0xF0,0xA5,0x0A,0x0F,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0x50,0x5F,0x55,0xF5,0xC3,0x6C,0x66,0x93,0x99,0xCC,0x99,0x39,0x9C,0xC9,0xC3,0x63,0xAF,0xA0,0xAA,0x0A,0x3C,0x93,0x99,0x6C,0x66,0x33,0x66,0xC6,0x63,0x36,0x3C,0x9C}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0xA5,0x00,0xFA,0xFF,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0xA5,0xFA,0x05,0x0A,0xC3,0x63,0x69,0x33,0x63,0x66,0xC9,0xC3,0x96,0xCC,0x93,0x33,0x5A,0x05,0xFA,0xF5,0x3C,0x9C,0x96,0xCC,0x9C,0x99,0x36,0x3C,0x69,0x33,0x6C,0xCC}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0xA5,0x55,0xF5,0x00,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0xF0,0x55,0xFA,0x55,0xC3,0x39,0x39,0x9C,0x6C,0x93,0x63,0x96,0x63,0x6C,0x96,0x96,0x0F,0xAA,0x05,0xAA,0x3C,0xC6,0xC6,0x63,0x93,0x6C,0x9C,0x69,0x9C,0x93,0x69,0x69}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0xAA,0xA0,0xF0,0x0F,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0xF5,0x55,0xA5,0xF0,0x3C,0x33,0xC9,0x6C,0x99,0xC6,0x99,0x63,0xC9,0x63,0x33,0xC9,0x0A,0xAA,0x5A,0x0F,0xC3,0xCC,0x36,0x93,0x66,0x39,0x66,0x9C,0x36,0x9C,0xCC,0x36}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0x50,0xFA,0xF5,0x5F,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0x0A,0x05,0xAA,0x0A,0x96,0x36,0x96,0x63,0x39,0x96,0x3C,0x93,0xCC,0x3C,0x63,0x99,0xF5,0xFA,0x55,0xF5,0x69,0xC9,0x69,0x9C,0xC6,0x69,0xC3,0x6C,0x33,0xC3,0x9C,0x66}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0x00,0x5A,0x0F,0x00,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0x55,0xFA,0x05,0xAF,0x69,0x33,0xC9,0x63,0x36,0xC3,0x93,0x39,0x63,0xC9,0xC9,0x36,0xAA,0x05,0xFA,0x50,0x96,0xCC,0x36,0x9C,0xC9,0x3C,0x6C,0xC6,0x9C,0x36,0x36,0xC9}，

{0xF0,0xF0,0x0F,0xF0,0xF0,0xF0,0x00,0x0F,0xF0,0x0F,0xF0,0x00,0x00,0x0A,0xAF,0xF5,0x0F,0x0F,0xF0,0x0F,0x0F,0x0F,0xFF,0xF0,0x0F,0xF0,0x0F,0xFF,0xA5,0x0A,0x5F,0x5A,0xC3,0x69,0x93,0xC6,0x39,0x3C,0x33,0x39,0x96,0x69,0x36,0x96,0x5A,0xF5,0xA0,0xA5,0x3C,0x96,0x6C,0x39,0xC6,0xC3,0xCC,0xC6,0x69,0x96,0xC9,0x69}。

in some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and carrying out bit demultiplexing on each fourth data stream to obtain 4 fifth data streams so as to obtain 32 fifth data streams in total.

In some possible embodiments, x=32, z=8, each of the first AM subsets comprises 48 symbols, each of the second AM subsets comprises 48 symbols, and the first AM set transforms to the second AM set satisfying equation 3 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

Wherein am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th second AM subset in the second AM set, floor ((j% 4)/2) represents the integer down of the quotient of (j% 4)/2, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor (j/4) represents the integer down of the quotient of j/4, 0.ltoreq.i.ltoreq.7, 0.ltoreq.j.ltoreq.48.

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x62,0x0B,0x21,0xB6,0x10,0x96,0x51,0x66,0x19,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0x76,0xDA,0x67,0xA7,0x7D,0xED,0x5B,0xD9,0x81,0x69,0xC7,0xE9,0x8D,0x63,0x21,0xF3,0xFA,0xC1,0x60,0x20,0x49,0x98,0x9A,0xB8,0x59,0xE0,0x54,0xF8,0xB1,0x7A,0x32,0x10,0xD8,0xFC,0x7E}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x62,0x88,0x26,0x86,0x68,0x95,0x55,0x56,0x59,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB6,0xDB,0x64,0xBB,0x4D,0x1F,0x60,0xFE,0x3E,0x1A,0xCF,0x07,0x08,0x83,0x7F,0x56,0x41,0x9F,0xDA,0xCB,0x80,0x7B,0x06,0x84,0x97,0xC3,0xE0,0xCF,0xF3,0x01,0xA4,0xF6,0xB2,0x95,0xD0}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x12,0x8A,0x2C,0xA1,0xC8,0x97,0x5D,0x76,0xD9,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0x76,0xDA,0x6E,0xA7,0xED,0x51,0x51,0x1B,0x2A,0x49,0x47,0xFD,0x84,0x2B,0xB0,0xF2,0x46,0xD7,0xA0,0x4B,0xB9,0xB2,0x92,0x17,0xDB,0xE2,0x06,0xDC,0x91,0x3F,0x36,0xE8,0x92,0x7C,0xD1}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0xD2,0x8B,0x28,0xBD,0x88,0x94,0x51,0x46,0x19,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB6,0xDB,0x62,0xBB,0x2D,0xDE,0x4F,0xEA,0xC2,0x58,0x72,0x62,0xD7,0xD8,0x89,0xA1,0x6D,0xE5,0x15,0x69,0x84,0xCC,0x46,0xF4,0x9C,0x34,0x76,0xB2,0x9C,0xD8,0x79,0x49,0x6A,0x68,0x5B}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x02,0xCA,0x2A,0xA0,0xAC,0x95,0x55,0x56,0x59,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xF6,0xDB,0x62,0xBF,0x2D,0xE9,0xA9,0x93,0xA1,0xC6,0xCC,0x49,0x3C,0x63,0x3B,0x75,0xF0,0xA4,0xC8,0x70,0x58,0x5C,0x81,0xF9,0xE5,0xCE,0xDC,0x1E,0x33,0x12,0x2A,0x32,0x5C,0xDD,0x3C}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0xA2,0x0B,0x2B,0xBA,0xB0,0x97,0x55,0x76,0x59,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0x36,0xD9,0x61,0x93,0x1D,0xA0,0x5E,0x07,0xD5,0x89,0xAD,0x6F,0x26,0x05,0x99,0xD8,0xE3,0x78,0xF2,0xB1,0x7E,0x8D,0xE2,0xEB,0xD8,0x49,0x49,0x66,0x6B,0x9B,0x9C,0x78,0x3C,0x76,0x38}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x82,0x09,0x25,0x98,0x50,0x94,0x51,0x46,0x19,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xF6,0xDA,0x6C,0xAF,0xCD,0xD5,0xB1,0x53,0x22,0xC7,0xD9,0x7F,0x69,0x02,0x68,0x95,0x0C,0xAF,0x06,0xCF,0xA9,0x30,0x91,0x36,0xE3,0x9A,0x0C,0x5A,0x36,0x5F,0xA8,0xC5,0x73,0xA5,0xC3}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x02,0x09,0x2D,0x90,0xD0,0x97,0x59,0x76,0x99,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0x76,0xD8,0x66,0x87,0x6D,0x5B,0x57,0xB6,0x4A,0x99,0xEC,0xA7,0x3B,0x81,0x45,0xA6,0xE6,0x95,0xA5,0x61,0x93,0xAA,0x36,0x95,0x9A,0x4C,0x68,0x31,0x7B,0xE9,0x64,0x65,0xB8,0xA9,0x79}。

in some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and performing symbol demultiplexing on each fourth data stream to obtain 4 fifth data streams, so as to obtain 32 fifth data streams in total.

In some possible embodiments, x=32, z=4, each of the first AM subsets comprises 96 symbols, each of the second AM subsets comprises 96 symbols, and the first AM set transforms to the second AM set satisfying equation 4 as follows:

AM_out<i,j>＝AM_in<i*4+Floor((j％4)/2)*16+j％2+Floor((j％8)/4)*2,Floor(j/8)>

wherein am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th second AM subset in the second AM set, floor ((j% 4)/2) represents the quotient of (j% 4)/2 rounded down, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor ((j% 8)/4) represents the quotient of (j% 8)/4 rounded down, j%8 represents the remainder of j divided by 8, floor (j/8) represents the quotient of j/8 rounded down, 0.ltoreq.i.ltoreq.3, 0.ltoreq.j.ltoreq.96.

In some possible embodiments, the 4 second AM subsets in the second AM set are in order of channel number:

{x9A,0x6A,0xAA,0xA9,0xA6,0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x92,0x49,0x26,0x99,0x64,0x62,0x0B,0x21,0xB6,0x10,0x62,0x88,0x26,0x86,0x68,0x96,0x51,0x66,0x19,0x65,0x95,0x55,0x56,0x59,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB5,0xD5,0x56,0x5B,0x6D,0x76,0xDA,0x67,0xA7,0x7D,0xB6,0xDB,0x64,0xBB,0x4D,0xED,0x5B,0xD9,0x81,0x69,0x1F,0x60,0xFE,0x3E,0x1A,0xC7,0xE9,0x8D,0x63,0x21,0xCF,0x07,0x08,0x83,0x7F,0xF3,0xFA,0xC1,0x60,0x20,0x56,0x41,0x9F,0xDA,0xCB,0x49,0x98,0x9A,0xB8,0x59,0x80,0x7B,0x06,0x84,0x97,0xE0,0x54,0xF8,0xB1,0x7A,0xC3,0xE0,0xCF,0xF3,0x01,0x32,0x10,0xD8,0xFC,0x7E,0xA4,0xF6,0xB2,0x95,0xD0}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x92,0x49,0x26,0x99,0x64,0x12,0x8A,0x2C,0xA1,0xC8,0xD2,0x8B,0x28,0xBD,0x88,0x97,0x5D,0x76,0xD9,0x65,0x94,0x51,0x46,0x19,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB5,0xD5,0x56,0x5B,0x6D,0x76,0xDA,0x6E,0xA7,0xED,0xB6,0xDB,0x62,0xBB,0x2D,0x51,0x51,0x1B,0x2A,0x49,0xDE,0x4F,0xEA,0xC2,0x58,0x47,0xFD,0x84,0x2B,0xB0,0x72,0x62,0xD7,0xD8,0x89,0xF2,0x46,0xD7,0xA0,0x4B,0xA1,0x6D,0xE5,0x15,0x69,0xB9,0xB2,0x92,0x17,0xDB,0x84,0xCC,0x46,0xF4,0x9C,0xE2,0x06,0xDC,0x91,0x3F,0x34,0x76,0xB2,0x9C,0xD8,0x36,0xE8,0x92,0x7C,0xD1,0x79,0x49,0x6A,0x68,0x5B}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x92,0x49,0x26,0x99,0x64,0x02,0xCA,0x2A,0xA0,0xAC,0xA2,0x0B,0x2B,0xBA,0xB0,0x95,0x55,0x56,0x59,0x65,0x97,0x55,0x76,0x59,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB5,0xD5,0x56,0x5B,0x6D,0xF6,0xDB,0x62,0xBF,0x2D,0x36,0xD9,0x61,0x93,0x1D,0xE9,0xA9,0x93,0xA1,0xC6,0xA0,0x5E,0x07,0xD5,0x89,0xCC,0x49,0x3C,0x63,0x3B,0xAD,0x6F,0x26,0x05,0x99,0x75,0xF0,0xA4,0xC8,0x70,0xD8,0xE3,0x78,0xF2,0xB1,0x58,0x5C,0x81,0xF9,0xE5,0x7E,0x8D,0xE2,0xEB,0xD8,0xCE,0xDC,0x1E,0x33,0x12,0x49,0x49,0x66,0x6B,0x9B,0x2A,0x32,0x5C,0xDD,0x3C,0x9C,0x78,0x3C,0x76,0x38}，

{0x9A,0x6A,0xAA,0xA9,0xA6,0x9A,0x6A,0xAA,0xA9,0xA6,0x92,0x49,0x26,0x99,0x64,0x92,0x49,0x26,0x99,0x64,0x82,0x09,0x25,0x98,0x50,0x02,0x09,0x2D,0x90,0xD0,0x94,0x51,0x46,0x19,0x65,0x97,0x59,0x76,0x99,0x65,0xB5,0xD5,0x56,0x5B,0x6D,0xB5,0xD5,0x56,0x5B,0x6D,0xF6,0xDA,0x6C,0xAF,0xCD,0x76,0xD8,0x66,0x87,0x6D,0xD5,0xB1,0x53,0x22,0xC7,0x5B,0x57,0xB6,0x4A,0x99,0xD9,0x7F,0x69,0x02,0x68,0xEC,0xA7,0x3B,0x81,0x45,0x95,0x0C,0xAF,0x06,0xCF,0xA6,0xE6,0x95,0xA5,0x61,0xA9,0x30,0x91,0x36,0xE3,0x93,0xAA,0x36,0x95,0x9A,0x9A,0x0C,0x5A,0x36,0x5F,0x4C,0x68,0x31,0x7B,0xE9,0xA8,0xC5,0x73,0xA5,0xC3,0x64,0x65,0xB8,0xA9,0x79}。

in some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and performing symbol demultiplexing on each fourth data stream to obtain 8 fifth data streams, so as to obtain 32 fifth data streams in total.

In some possible embodiments, before decoding the z first data streams to obtain z second data streams, the method further includes: receiving n demodulation data streams from n channels respectively, wherein n is more than 1 and less than or equal to z; and respectively carrying out de-distribution and inverse mapping on the n demodulated data streams to obtain the z first data streams.

In some possible embodiments, after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the method further includes: and carrying out channel deviation correction on the z fourth data streams.

In some possible embodiments, before decoding the z first data streams to obtain z second data streams, the method further includes: and respectively carrying out code word synchronization on the z first data streams so as to align symbols in the z first data streams.

In a second aspect, embodiments of the present application provide a data processing apparatus. The data processing apparatus includes: a decoding unit, a deconvolution interleaving unit and a pair Ji Biaoshi AM locking unit. The decoding unit is used for respectively decoding the z first data streams to obtain z second data streams, wherein the z first data streams are all subjected to Forward Error Correction (FEC) coding, and z is an integer greater than 1. And the deconvolution interleaving unit is used for respectively deconvoluting and interleaving the z second data streams to obtain z third data streams. The AM locking unit is used for respectively carrying out AM locking on the z third data streams according to a second AM set to obtain z fourth data streams, wherein the second AM set is obtained by converting a first AM set preset by a transmitting end, the first AM set comprises x first AM subsets, x is an integer larger than 1, the second AM set comprises z second AM subsets, and the z second AM subsets are used for carrying out AM locking on the z third data streams respectively.

AM_out<i,j>＝AM_in<(i+16*Floor(j/2))％32,j>

In some possible embodiments, the data processing apparatus further comprises a channel reordering unit. After the z third data streams are respectively AM-locked according to the second AM set to obtain z fourth data streams, the channel reordering unit is configured to reorder the channels of the z fourth data streams according to the second AM set, so that the z fourth data streams are arranged according to a preset sequence, where the z second AM subsets are used to match with the AMs in the z fourth data streams respectively, each second AM subset has a corresponding channel number, and the fourth data streams are arranged according to the channel numbers of the successfully matched second AM subsets.

In some possible implementations, the data processing apparatus further includes a de-lane permute unit. And after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the de-channel replacement unit is used for performing de-channel replacement on the z fourth data streams to obtain z fifth data streams.

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

in some possible embodiments, the data processing apparatus further comprises a bit demultiplexing unit. And after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the bit demultiplexing unit is further configured to perform bit demultiplexing on each fourth data stream to obtain 4 fifth data streams, so as to obtain 32 fifth data streams in total.

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

in some possible embodiments, the data processing apparatus further comprises a symbol demultiplexing unit. And after performing AM locking on the z third data streams respectively according to the second AM set to obtain z fourth data streams, the symbol demultiplexing unit is used for performing symbol demultiplexing on each fourth data stream to obtain 4 fifth data streams so as to obtain 32 fifth data streams in total.

in some possible embodiments, the data processing apparatus further comprises a symbol demultiplexing unit. And after performing AM locking on the z third data streams respectively according to the second AM set to obtain z fourth data streams, the symbol demultiplexing unit is used for performing symbol demultiplexing on each fourth data stream to obtain 8 fifth data streams so as to obtain 32 fifth data streams in total.

In some possible implementations, the data processing apparatus further includes a de-distribution and inverse mapping unit. Before decoding the z first data streams to obtain z second data streams, the de-distribution and inverse mapping unit is configured to: n demodulated data streams from n channels are received, where n is greater than 1 and less than or equal to z. And respectively carrying out de-distribution and inverse mapping on the n demodulated data streams to obtain the z first data streams.

In some possible embodiments, the data processing apparatus further comprises a channel deskewing unit. And after the third data streams are respectively AM locked according to the second AM set to obtain fourth data streams, the channel correction unit is used for carrying out channel correction on the fourth data streams.

In some possible embodiments, the data processing apparatus further comprises a codeword synchronization unit. Before the z first data streams are decoded respectively to obtain z second data streams, the codeword synchronization unit is configured to perform codeword synchronization on the z first data streams respectively, so that symbols in the z first data streams are aligned.

As can be seen from the description of the above embodiments, the receiving end decodes and deconvolves the received data stream in sequence, and performs AM locking on the data stream. And an AM locking is designed at the receiving end, so that channel rectification (Deskew) and channel reordering (Lane Reorder) are conveniently carried out under the AM locking condition, and channel de-substitution can be better realized. Therefore, the receiving end does not need to set DSP framing processing, the time delay is reduced, and the applicable PMD types are more. And after deconvolution interleaving, AM locking is designed, so that the processing complexity is reduced, and the time delay is further reduced.

Drawings

Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a process for data transmission in the communication system of FIG. 1;

FIG. 3 is a schematic diagram of an optical module in a data center scenario;

fig. 4 is a schematic diagram of a first process flow of the transceiver end in the embodiment of the present application;

FIG. 5 is a schematic diagram of AM in a channel data stream;

FIG. 6 is a schematic flow chart of channel replacement according to an embodiment of the present application;

FIG. 7 (a) is a schematic diagram of a first configuration of a convolutional interleaver according to an embodiment of the present application;

FIG. 7 (b) is a schematic diagram of a second configuration of a convolutional interleaver according to an embodiment of the present application;

FIG. 8 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure;

FIG. 9 (a) is a diagram of a first embodiment of codeword synchronization;

fig. 9 (b) is a schematic diagram of a second embodiment of codeword synchronization;

FIG. 10 is a schematic flow chart of a solution channel permutation in the embodiment of the present application;

FIG. 11 is a schematic diagram of a second process flow of the transceiver end in the embodiment of the present application;

FIG. 12 is a flow chart of bit distribution and mapping;

FIG. 13 is a flow chart of the bit distribution and inverse mapping;

FIG. 14 is a schematic flow chart of another solution channel permutation in the embodiment of the present application;

Fig. 15 is a schematic diagram of a third process flow of the transceiver end in the embodiment of the present application;

fig. 16 is a schematic diagram of a fourth process flow of the transceiver end in the embodiment of the present application;

fig. 17 is a schematic diagram of a fifth process flow of the transceiver end in the embodiment of the present application;

fig. 18 is a schematic diagram of a sixth process flow of the transceiver end in the embodiment of the present application;

FIG. 19 is a schematic view of a data processing apparatus according to an embodiment of the present application;

FIG. 20 is a schematic diagram of another structure of a data processing apparatus according to an embodiment of the present application;

fig. 21 is a schematic diagram of another structure of the data processing apparatus in the embodiment of the present application.

Detailed Description

The embodiment of the application provides a data processing method and a data processing device, which are beneficial to reducing the time delay of a receiving end and can adapt to more PMD types. It should be noted that the terms "first," "second," and the like in the description and claims herein and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are capable of operation in sequences other than described of illustrated herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of a communication system applied in an embodiment of the present application. As shown in fig. 1, the communication system includes an originating device 01, an originating processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, the originating device 01 and the receiving device 05 may be devices such as a switch or a router, where the originating device 01 is also referred to as a host chip located at an originating end, the receiving device 05 is also referred to as a client chip located at a receiving end, and the channel transmission medium 03 may be an optical fiber. The client-side chip is sometimes also referred to as a client-side device (host device). The originating device 01 and the originating processing module 02 may be connected through a connection unit interface (attachment unit interface, AUI), and the receiving device 05 and the receiving processing module 04 may be connected through the AUI. The originating processing module 02 and the receiving processing module 04 may be optical modules (optical modules), electrical modules, connectors (connectors), or other modules that process data during data transmission. For example, the processing module may be an 800LR module (800 LR module), a coherent light module. In addition, the originating device 01, the originating processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system may support bidirectional transmission or unidirectional transmission, which is not limited herein.

Fig. 2 is a schematic diagram illustrating a data transmission process in the communication system shown in fig. 1. As shown in fig. 2, in transmitting data from an originating device 01 to a receiving device 05, the originating device 01 is configured to perform outer code encoding on the data, and then transmit the outer code encoded data to an originating processing module 02. The originating processing module 02 is configured to perform inner code encoding on the data encoded by the outer code, obtain data encoded by the outer code and encoded by the inner code, and transmit the data encoded by the outer code and encoded by the inner code to the channel transmission medium 03. The channel transmission medium 03 is used for transmitting the data encoded by the outer code and the inner code to the receiving end processing module 04. The receiving end processing module 04 is configured to perform inner code decoding on the data subjected to outer code encoding and inner code encoding, and transmit the data subjected to inner code decoding to the receiving end device 05. The receiving device 05 is configured to perform outer code decoding on the data subjected to inner code decoding.

It should be appreciated that the "inner" of the inner code and the "outer" of the outer code are merely distinguished based on how far apart the executing body is from the channel transmission medium 03 that is operating on the data. The execution body operating on the inner code is closer to the channel transmission medium, and the execution body operating on the outer code is farther from the channel transmission medium. In the embodiment of the present application, since data is transmitted to the channel transmission medium 03 through the originating processing module 02 after being sent out from the originating device 01, and then transmitted to the receiving device 05 from the channel transmission medium 03 through the receiving processing module 04. The data encoded by the originating device 01 is farther from the channel transmission medium 03 than the data encoded by the originating processing module 02, and the data encoded by the receiving device 05 is farther from the channel transmission medium 03 than the data encoded by the receiving processing module 04. Therefore, the data encoded by the originating device 01 is referred to as outer code encoded data, the data encoded by the originating processing module 02 is referred to as inner code encoded data, the data decoded by the receiving device 05 is referred to as outer code decoded data, and the data decoded by the receiving processing module 04 is referred to as inner code decoded data. In one possible implementation, the inner code encoding and the outer code encoding are both implemented by adopting FEC encoding, so as to form a transmission scheme of concatenated FEC. For example, the originating device 01 may perform outer code encoding using an RS code, and the originating processing module 02 may perform inner code encoding using a Hamming (Hamming) code. For another example, the originating device 01 may perform outer code encoding using an RS code, and the originating processing module 02 may perform inner code encoding using a Bose-Chaudhuri-Hocquenghem (BCH) code.

It should be noted that the foregoing is an exemplary description of the application scenario in the embodiment of the present application, and does not constitute a limitation of the application scenario in the present application, and those skilled in the art can know that, as the service requirement changes, the application scenario can be adjusted according to the application requirement, which is not specifically recited in the embodiment of the present application.

The method and the device can be used for application scenes of short-distance interconnection, cloud storage, cloud computing, 5G base station backbone networks and the like of the data center, wherein the application scenes are large in flow and short in delay. As an example, the present application may be implemented by an optical module. Fig. 3 is a schematic diagram of an optical module in a data center scenario. As shown in fig. 3, the device side refers to a switch, in particular a network port of the switch, and the module side refers to an optical module or an electrical module. The equipment side and the optical module are electrically connected through an AUI interface. The device side is a network architecture main body of the data center, the network of the data center is divided into three layers of networks, in fig. 3, a convergence layer, a switching layer of frames (TOR) and servers are sequentially shown from Top to bottom, communication between the servers needs to be uploaded to the convergence layer, and then the convergence layer is routed to other servers, so that data transmission and exchange between the servers are realized. It should be appreciated that the present application may be primarily applicable to module-side physical medium access sublayers (Physical Medium Attachment Sublayer, PMA) or Inner-FEC layers.

Fig. 4 is a schematic diagram of a first process flow of the transceiver end in the embodiment of the present application. The following first describes the processing flow of the transmitting end in the embodiment of the present application with reference to fig. 4.

Specifically, the transmitting end sequentially performs Alignment Marker (AM) locking, channel Deskew (Deskew) and channel reordering (Lane Reorder) on the z channel data streams, so that the data streams correctly correspond to the channel sequence numbers. The z channel data streams may be physical coding sublayer (Physical Coding Sublayer, PCS) channel data streams as shown in fig. 4, or the z channel data streams may be FEC channel data streams, which is not limited herein. It should be appreciated that the z channel data streams are all first FEC encoded data streams, i.e. the outer code encoded data streams described above, wherein z is an integer greater than 1.

Fig. 5 is a schematic diagram of AM in a channel data stream. As shown in fig. 5, AM occurs periodically on each channel data stream, for example, the length of AM is 120 bits, and AM occurs once per 5440×8192×2/32= 2785280 bits in the channel data stream. In the AM locking operation, the channel data stream is first bit-slid to find the AM position, so that the AM in the channel data stream is AM locked with the preset first AM set.

It should be appreciated that the first AM set is generated by the PCS layer at the transmitting end, and that the AM corresponding to the PCS channel is inserted periodically after being processed by the AM mapping function in order to support correction and reordering of the individual PCS channels at the receiving PCS. The AM mapping function compensates for the operation of the symbol distribution function and rearranges the AM so that they appear intact on the PCS channel and are displayed in the desired order. This preserves the properties of the AM (e.g., DC balance, transition density) and provides a deterministic pattern for synchronization purposes. For a 200GBASE-R PCS, the first AM set consists of the AM of all 8 PCS channels plus an additional 65-bit pad (pad) and a 3-bit status field to produce a block of four 257 bits of data. For 400GBASE-R PCS, the first AM set consists of the alignment flags for all 16 PCS channels plus an additional 133 bit pad and a 3 bit status field to produce a value equivalent to 8 257 bit blocks. The first AM set aligns to the beginning of both FEC messages and interrupts any already ongoing data transmission. The pad bit at the end of the alignment mark group should be set to the free-running PRBS9 pattern. There is one common portion (designated CM0 to CM 5) in AM for all PCS channels, each PCS channel specific portion (designated UM0 to UM 5), and finally each PCS channel specific pad (designated UP0 to UP 2). Common synchronization logic, independent of the received PCS channel number, may be used with the common portion of the AM. The only pad (UP 0 to UP 2) in the AM and the PRBS9 pad at the end of the first AM set are ignored at the time of reception.

As an example, the first AM set is shown in table 1 below, where the first AM set includes x first AM subsets, and x is an integer greater than 1, and for convenience of description, x=32 is described below as an example. For example, the number of channel data streams is 32, and the first AM set has a first subset of AM corresponding to each channel data stream. Taking a first AM subset corresponding to one channel data stream in the first AM set as an example, the first AM subset includes 15 bytes for 120 bits, where the 15 bytes are sequentially expressed as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.

TABLE 1

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In one possible implementation, the first AM set has 6 bytes CM0, CM1, CM2, CM3, CM4, and CM5 for matching in order with the 0 th byte, 1 st byte, 2 nd byte, 4 th byte, 5 th byte, and 6 th byte of every consecutive 7 bytes of the channel data stream for AM locking. As an example, 48 bits (6 bytes) are divided into 12 groups for comparison one by one with 4 bits (nibbles) as a comparison granularity. If at least 9 groups of 12 groups of comparison can be matched, AM locking is realized for 1 time, then AM locking is performed on the next AM in the channel data stream in the same mode, and if AM locking is realized for 2 continuous AMs in the channel data stream, an AM locking condition is achieved. Correspondingly, if 12 groups are compared with less than 9 groups and can be matched, 1 AM unlocking is realized, and if continuous 5 AMs in the channel data stream realize AM unlocking, an AM unlocking condition is achieved.

It should be appreciated that after all of the channel data streams have achieved the AM lock condition, channel Deskew (Deskew) may be performed according to the lock time interval between the channel data streams to remove data skew on the channel data streams and obtain aligned z channel data streams. Further, channel reordering (Lane Reorder) is performed on the z-channel data streams according to AM so that the z-channel data streams can be arranged in a specified order.

After sequentially performing AM locking, channel Deskew (Deskew) and channel reordering (Lane Reorder) on the z data streams, the transmitting end further performs channel replacement (Lane Permulation) on the z data streams respectively. It should be appreciated that channel permutation may be used to place the data in the z data streams. Channel permutation may also be referred to as a channel arrangement, which refers to periodically selecting a certain segment of a data stream among data streams between virtual channels, and exchanging the data blocks between the virtual channels. The present application is not limited to a specific implementation of channel replacement, and one possible channel replacement method is provided below.

Fig. 6 is a schematic flow chart of channel replacement in the embodiment of the present application. As shown in fig. 6, 32 rows represent 32 data streams, respectively, and 16 columns represent 16 symbols in each data stream, respectively. Wherein a symbol may comprise one bit or a plurality of bits, and is not limited herein. For example, the outer code is a KP4 RS (544,514) code used, and the code length n=544 symbols, one symbol containing 10 bits. Specifically, with each continuous 4 columns of the data stream as one period, the positions of the first two columns of symbols in each period before and after channel replacement are kept unchanged, and the positions of the second two columns of symbols in each period before and after channel replacement are changed. Taking fig. 6 as an example, the last two columns of symbols in each period in data stream 0 exchange positions with the last two columns of symbols in the corresponding period in data stream 16, the last two columns of symbols in each period in data stream 1 exchange positions with the last two columns of symbols in the corresponding period in data stream 17, and so on, the last two columns of symbols in each period in data stream 14 exchange positions with the last two columns of symbols in the corresponding period in data stream 30, and the last two columns of symbols in each period in data stream 15 exchange positions with the last two columns of symbols in the corresponding period in data stream 31.

After the transmitting end performs channel replacement on the z data streams respectively, the transmitting end further performs convolution interleaving on the z data streams subjected to channel replacement respectively to obtain z data streams with disordered sequences. It should be appreciated that channel permutation may be effective to reduce the delay of convolutional interleaving or to increase the interleaving depth. It should be noted that each convolutional interleaver performs convolutional interleaving on the input data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays an input data stream according to the p delay lines. Wherein p is an integer greater than 1, each delay line includes a different number of memory cells, the delay line with the smallest number of memory cells includes 0 memory cells, the difference between the numbers of memory cells in each two adjacent delay lines is Q, and each memory cell is used for storing d symbols. The symbols in each data stream are sequentially input into p delay lines according to the serial numbers of the p delay lines, d symbols are input into each delay line at a time and d symbols are output at a time, and the continuous p×d symbols in the output data stream comprise d symbols output by each delay line. Wherein Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, p delay lines respectively include 0 memory cells, Q memory cells, 2Q memory cells, …, (p-1) Q memory cells, each memory cell is configured to store d symbols, and then p delay lines respectively correspond to p delay values, where the delay values include 0 symbols, q×d symbols, 2q×d symbols, …, (p-1) q×d symbols. It should be noted that, in this application, the delay value is counted in units of symbols, where a symbol may include one or more bits. The greater the number of symbols included in the delay value of the delay line, the longer the delay (also referred to as delay) of the delay line to the data stream. It should be appreciated that when the delay line does not contain memory cells, the delay of the delay line is 0 symbols, i.e., no delay transparent.

The specific structure of the convolutional interleaver is described below with reference to the accompanying drawings.

Fig. 7 (a) is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application. As shown in fig. 7 (a), the number of memory cells in the p delay lines is sequentially decreased according to the serial numbers of the p delay lines. That is, delay line 0 has (p-1) Q memory cells, each delay line sequentially decreasing by Q memory cells, and delay line p-1 has 0 memory cells. Fig. 7 (b) is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application. As shown in fig. 7 (b), the number of memory cells in the p delay lines increases sequentially according to the serial numbers of the p delay lines. I.e. delay line 0 has 0 memory cells, each delay line is sequentially increased by Q memory cells, and delay line p-1 has (p-1) Q memory cells.

It should be noted that, at the same time, the switch (switch) for inputting and outputting the convolutional interleaver is located on the same delay line, after the current delay line inputs d symbols once and outputs d symbols, the switch is switched to the next delay line, so as to ensure that the symbols in each channel data stream are sequentially input to p delay lines according to the serial numbers of p delay lines, and the continuous p×d symbols in the first data stream include d symbols output by each delay line. The specific data read-write operation is as follows: the d symbols are read from the memory cell of the current delay line closest to the output port. And transferring d symbols stored in each storage unit in the current delay line to a next storage unit. And d symbols are written into a storage unit closest to the input port in the current delay line. Thereafter, the next delay line is switched to and the above operation is repeated, and so on.

It should be understood that the convolutional interleaving process of fig. 7 (a) and the convolutional interleaving process of fig. 7 (b) are inverse operations of each other when the same parameters p, Q, and d are employed. That is, when the originating processing module adopts the convolutional interleaving structure shown in fig. 7 (a), the convolutional de-interleaving corresponding to the receiving processing module adopts the structure shown in fig. 7 (b). Similarly, when the transmitting processing module adopts the convolution interleaving structure shown in fig. 7 (b), the convolution de-interleaving corresponding to the receiving processing module adopts the structure shown in fig. 7 (a).

It should also be appreciated that any one of the z convolutional interleavers may employ one of fig. 7 (a) or fig. 7 (b) described above. In practical applications, the structure shown in fig. 7 (a) may be used for all the z convolutional interleavers; alternatively, the z convolutional interleavers may each have the structure shown in fig. 7 (b); alternatively, a part of the convolutional interleavers may be configured as shown in fig. 7 (a), and the rest of the convolutional interleavers may be configured as shown in fig. 7 (b).

After the transmitting end carries out convolution interleaving on the z data streams respectively, the transmitting end further carries out inner code coding on the z data streams after convolution interleaving, and then carries out bit distribution and mapping on the z data streams after inner code coding, so that the data streams after bit distribution and mapping are transmitted to the receiving end through n physical channels. Wherein n is an integer greater than or equal to 1. It should be understood that bit distribution and mapping refers to the operation of multiplexing (mux) or demultiplexing (demux) bit data such that data locations are mapped from virtual PCS channels onto corresponding physical channels, bit distribution and mapping may also be symbol granularity distribution and mapping, bit distribution and mapping may also be referred to as channel interleaving or data distribution, etc.

It should be noted that, the data processing flow of the transmitting end is described above, and the data processing method of the receiving end provided in the present application is described below.

Fig. 8 is a schematic flow chart of a data processing method according to an embodiment of the present application.

801. And respectively decoding the z first data streams to obtain z second data streams.

In this embodiment, the receiving end receives the data streams transmitted by the transmitting end through n physical channels, and then performs bit-decoding distribution and inverse mapping on the received data streams to obtain z first data streams. Next, the receiving end performs codeword synchronization on the z first data streams respectively, so as to achieve symbol alignment between the z first data streams. And then, the receiving end respectively decodes the z first data streams after the code word synchronization to obtain z second data streams. It should be understood that, the bit distribution and inverse mapping performed by the receiving end is the inverse operation of the bit distribution and mapping performed by the transmitting end, and the decoding performed by the receiving end is the inverse operation of the inner code encoding performed by the transmitting end, which is known to those skilled in the art, and will not be described herein.

It should also be appreciated that since the transmitting end performs inner code encoding on each channel data stream, each data stream after inner code encoding includes a plurality of codewords. If the inner code adopts hamming code, the codeword can be called hamming block. Several possible implementations of codeword synchronization are described below.

Fig. 9 (a) is a schematic diagram of a first embodiment of codeword synchronization. As shown in fig. 9 (a), for example, the length of the codeword obtained by hamming encoding is 128 bits, wherein 120 bits are information bits and 8 bits are check bits. Specifically, the window is slid for 128 times, 1 bit is slid for each time, whether the Hamming syndrome value in the 128-bit window is zero is calculated, and pre-synchronization is performed. And after the Hamming syndrome value is found to be zero in the sliding window, pre-synchronizing and locking, and then carrying out Hamming block synchronization. The hamming block synchronization takes 128 bits of the hamming codeword length as an interval, calculates whether the hamming syndrome value is zero each time, and counts the T times of calculation results altogether. And if the number of the found syndrome values is zero within T times, the number is more than or equal to Q, and the Hamming block is synchronously locked. Otherwise, the operation is re-executed until the number of the found zero syndrome values is more than or equal to Q in T times, and the Hamming block locking is completed. For example, t=16, q=13. For another example, t=14, q=13. As another example, t=12, q=10.

Fig. 9 (b) is a schematic diagram of a second embodiment of codeword synchronization. As shown in fig. 9 (b), a hamming code is taken as an example, and the length of the codeword is 128 bits, wherein 120 bits are information bits and 8 bits are check bits. Specifically, the window is slid for 128 times, 1 bit is slid for each time, whether the Hamming syndrome value in the 128-bit window is zero is calculated, and pre-synchronization is performed. And after the Hamming syndrome value is found to be zero in the sliding window, pre-synchronizing and locking, and then carrying out Hamming block synchronization. The hamming block synchronization calculates whether the continuous T hamming syndrome values are all zero with 128 bits of hamming codeword length as an interval. If the T continuous syndrome values are all zero, the Hamming block is synchronously locked. Otherwise, the operation is re-executed until the T continuous syndrome values are all zero, and the Hamming block locking is completed. For example, t=14, 13, 12, 11, or 10.

It should be noted that, after the hamming block is locked, the data segment for hamming block synchronization may be removed first and then hamming decoding may be performed. After hamming decoding, the check bit of each hamming codeword is removed, and then the decoded data stream is output. In practical applications, the operations of codeword synchronization and decoding may be implemented by two different modules, or may be implemented by a decoder, which is not limited herein.

802. And deconvolution interleaving is respectively carried out on the z second data streams to obtain z third data streams.

It should be understood that the deconvolution interleaving performed by the receiving end is the inverse operation of the deconvolution interleaving performed by the transmitting end, and specific implementation manner will be known to those skilled in the art, and will not be described herein.

803. And respectively performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams.

It should be noted that each third data stream includes AM, and the AM in each third data stream occurs periodically, which may be similar to that shown in fig. 5. The second AM set comprises z second AM subsets, the z second AM subsets are in one-to-one correspondence with the z third data streams, and each second AM subset is used for matching with the corresponding third data stream so as to realize AM locking.

It should be appreciated that the second set of AMs is transformed based on the first set of AMs. As one example, each first subset of AM in the first set of AM's comprises 12 symbols (as shown in table 1 above), and correspondingly, each second subset of AM in the second set of AM's comprises 12 symbols, each symbol comprising 10 bits. The first AM set is transformed to obtain a second AM set satisfying the following equation 1:

AM_out<i,j>＝AM_in<(i+16*Floor(j/2))％32,j>

where am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th second AM subset in the second AM set, floor (j/2) represents a downward rounding of the quotient of j divided by 2, 16 x Floor (j/2))%32 represents the remainder of 16 x Floor (j/2)) divided by 32, 0.ltoreq.i.ltoreq.31, 0.ltoreq.j.ltoreq.11.

The second set of AM's obtained in the manner described above may be as shown in table 2 below. Taking one of the second AM subsets of table 2 as an example, the second AM subset includes a total of 120 bits of 15 bytes, which are represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}. It should be appreciated that since the transmitting end also performs channel replacement after performing AM locking, the second AM set used by the receiving end for AM locking is different from the first AM set used by the transmitting end for AM locking. The second set of AM's provided in table 2 below was designed based on the channel replacement method described in the above embodiments, and if the channel replacement method is changed, the second set of AM's is changed accordingly. That is, the method for channel replacement between the second AM set and the transmitting end provided in the present application corresponds, and except for the examples provided in the present application, those skilled in the art may perform flexible transformation with reference to the examples, which are not described herein.

TABLE 2

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In one possible implementation, 6 bytes of CM0, CM1, CM2, CM3, CM4, and CM5 in the second AM set are used to match up with 6 bytes of 0 th byte, 1 st byte, 2 nd byte, 4 th byte, 5 th byte, and 6 th byte, respectively, of every 7 consecutive bytes of the third data stream in order for AM locking. Specifically, with 8 bits (one byte) as contrast granularity, 48 bits (6 bytes) are divided into 6 groups to be compared one by one. If at least P groups in the 6 groups of comparison can be matched, 1 time of AM is effective, and then 6 bytes at corresponding positions in the next group of continuous 7 bytes in the third data stream are matched in the same mode, and if R times of AM is effective, an AM locking condition is achieved. Correspondingly, if the comparison of 6 groups is less than that of P groups, the AM failure is realized for 1 time, and if the AM failure is realized for S times, the AM unlocking condition is achieved. As one example, p=3, 4, or 5, r=1 or 2, s=2, 3, 4, or 5.

In another possible implementation, the comparison granularity is 4 bits (nibbles), and the comparison is performed by dividing 48 bits (6 bytes) into 12 groups one by one. If at least P groups in the 12 groups of comparison can be matched, 1 time of AM is effective, and if R times of AM is effective, an AM locking condition is achieved. Correspondingly, if the comparison of 12 groups is less than that of P groups, the AM failure is realized for 1 time, and if the AM failure is realized for S times, the AM unlocking condition is achieved. As one example, p=9, 10 or 11, r=1 or 2, s=2, 3, 4 or 5.

Therefore, the receiving end can achieve the AM locking condition by realizing the AM effective at least once, and the time required by AM locking is reduced.

It should be noted that, before the receiving end matches the z third data streams according to the second AM set, the receiving end determines the positions of the AMs in the third data streams. Different from the mode of determining the AM position through a bit sliding window in the sending process, as the receiving end realizes symbol alignment among data streams through codeword synchronization, the receiving end uses symbols as granularity to carry out sliding window to determine the position of each AM in the third data stream, the number of times of sliding window needed by the receiving end for AM locking is reduced, and the time for AM locking is reduced. As an example, the starting position of AM in the third data stream is fixed at bit 0, bit 40 or bit 80 of the codeword, so the sliding window can be performed with granularity of 4 symbols (40 bits) in addition to granularity of 1 symbol (10 bits).

804. And carrying out channel deviation correction on the z fourth data streams.

In some possible embodiments, after the receiving end performs AM locking on the z third data streams to obtain z fourth data streams, channel deviation correction (Deskew) is performed on the z fourth data streams, so that data deviation among the z fourth data streams is removed, and aligned z fourth data streams are obtained. The specific implementation of channel correction (Deskew) is known to those skilled in the art and will not be described in detail herein.

805. And channel reordering the z fourth data streams according to the second AM set.

In some possible embodiments, after the receiving end performs channel Deskew (Deskew) on the z fourth data streams, channel reordering (Lane Reorder) is performed on the z fourth data streams, so that the z fourth data streams are arranged in a preset order. Specifically, z second AM subsets in the second AM set are used for matching with AM in z fourth data streams, where each second AM subset has a corresponding channel number, and the fourth data streams are arranged according to the channel numbers of the successfully matched second AM subsets.

In one possible implementation, the second AM set may be as shown in table 2 above, where a total of 6 bytes UM0, UM1, UM2, UM3, UM4, and UM5 in table 2 are used to match 6 bytes in the corresponding location in the AM of the fourth data stream, respectively. As an example, 6 bytes at corresponding positions in AM of one fourth data stream are 0x95,0x14,0xd8,0x65,0xeb,0xd8, respectively, and the fourth data stream is arranged corresponding to the pattern number 10 as can be seen from table 2.

In table 2, each byte is represented in hexadecimal, and the sequence corresponding to the number 0 is exemplified by the sequence of 0x01,0x8e,0xf3,0xf1,0x71,0xf3, from left to right, the left is LSB, and the right is MSB. Wherein, the transmission bit expressed by 0x01 is from the 0 th bit to the 7 th bit of the transmission from left to right, and the binary expression is '10000000'. Similarly, 0x8E binary is denoted as "01111001",0xF3 binary is denoted as "11001111",0xF1 binary is denoted as "10001111",0x71 binary is denoted as "10001110", and 0xF3 binary is denoted as "11001111". Thus, the sequence corresponding to number 0 is represented in binary as "1000,0000,0111,1001,1100,1111,1000,1111,1000,1110,1100,1111".

806. And performing de-channel replacement on the z fourth data streams to obtain z fifth data streams.

In some possible embodiments, after the sender performs AM locking, channel Deskew (Deskew) and channel reordering (Lane Reorder) on the z data streams in sequence, channel Permutation (Lane Permutation) is further performed on the z data streams respectively. Therefore, the receiving end needs to perform De-channel Permutation (De-Lane Permulation) on the z fourth data streams to obtain z fifth data streams. It should be understood that the channel de-substitution is the inverse operation of the channel substitution, and the data stream form before the channel substitution performed by the transmitting end can be recovered after the receiving end performs the channel de-substitution. The channel replacement operation described in fig. 6 is described below as an example, and the channel replacement operation corresponding thereto is described.

Fig. 10 is a schematic flow chart of a solution channel permutation in the embodiment of the present application. As shown in fig. 10, 32 rows represent 32 data streams, respectively, and 16 columns represent 16 symbols in each data stream, respectively. Specifically, with each continuous 4 columns of the data stream as one period, the positions of the first two columns of symbols in each period before and after the channel de-permutation are kept unchanged, and the positions of the second two columns of symbols in each period before and after the channel de-permutation are changed. Taking fig. 10 as an example, the last two columns of symbols in each period in data stream 0 exchange positions with the last two columns of symbols in the corresponding period in data stream 16, the last two columns of symbols in each period in data stream 1 exchange positions with the last two columns of symbols in the corresponding period in data stream 17, and so on, the last two columns of symbols in each period in data stream 14 exchange positions with the last two columns of symbols in the corresponding period in data stream 30, and the last two columns of symbols in each period in data stream 15 exchange positions with the last two columns of symbols in the corresponding period in data stream 31.

The solution channel permutation flow shown in fig. 10 above can also be understood as: each fourth data stream comprises a plurality of symbol sets, each fifth data stream comprises a plurality of symbol sets, each symbol set comprising two consecutive symbols. The first symbol set and the second symbol set in each fourth data stream are adjacent, and the first symbol set and the second symbol set in each fifth data stream are adjacent. The first symbol set in the fifth data stream of the a-th data stream is from the first symbol set in the fourth data stream of the a-th data stream, and the first symbol set in the fifth data stream of the a-th data stream is the same as the first symbol set in the fourth data stream of the a-th data stream. The second symbol set in the fifth data stream of a is from the second symbol set in the fourth data stream of (a+16)% 32, and the second symbol set in the fifth data stream of a is the same as the second symbol set in the fourth data stream of (a+16)% 32. Wherein 0.ltoreq.a.ltoreq.31, (a+16)% 32 represents the remainder of dividing a+16 by 32. It should be understood that the same position of two symbol sets may be considered as the same column number for both symbol sets.

Fig. 11 is a schematic diagram of a second process flow of the transceiver end in the embodiment of the present application. Unlike the process flow shown in fig. 4 described above, the data stream may be transmitted through multiple physical channels in this embodiment. In the 200G per encoded data stream scene of 800GE, n is fixed to 4, i.e. 32 encoded data streams are fixedly transmitted through 4 physical channels. For ease of description, the data streams transmitted through the n physical channels are referred to as modulated data streams. Grouping 32 coded data streams, wherein the coded data streams 0 to 3 are a first group of coded data streams, which are called G0; the encoded data streams 4 to 7 are a second group of encoded data streams, called G1; encoded data streams 8 through 11 are a third set of encoded data streams, referred to as G2; encoded data streams 12 through 15 are a fourth set of encoded data streams, referred to as G3; encoded data streams 16 through 19 are the fifth set of encoded data streams, referred to as G4; encoded data streams 20 through 23 are a sixth set of encoded data streams, referred to as G5; encoded data streams 24 through 27 are a seventh set of encoded data streams, referred to as G6; the encoded data streams 28 to 31 are eighth group encoded data streams, which are called G7.

The size of the split data blocks on each group is defined as 4*W, W represents the bit width of each data block split from the encoded data stream, and W takes on a value of 1,2,4,5,8,10,20 or 40. W=1 denotes slicing a block of 4*1 from a set of encoded data streams; w=2 denotes slicing one 4*2 (4×1pam4 symbols) block from a set of encoded data streams; w=10 denotes slicing a 4×10 (4×1rs symbols) data block from a set of encoded data streams; w=20 denotes slicing a 4×20 (4×2rs symbols) data block from a set of encoded data streams.

Fig. 12 is a flow chart of bit distribution and mapping. As shown in fig. 12, taking w=20 as an example, block_g < i, j > represents the j-th data block of the i-th encoded data stream, and block < i, j > represents the j-th data block of the i-th modulated data stream. As an example, a data block block_g <0,0> with a size of 4×20 (4×2rs symbols) is interleaved with a data block block_g <4,0> with a size of 4×20 (4×2rs symbols) by taking the symbols as granularity, and the data blocks block <0,0> with a size of 4×40 (4×4rs symbols) are combined; data block_g <1,0> with the size of 4 x 20 (4 x 2rs symbols) and data block_g <5,0> with the size of 4 x 20 (4 x 2rs symbols) are interleaved according to the symbol as granularity, and are combined into data block <1,0> with the size of 4 x 40 (4 x 4rs symbols); data block_g <2,0> with the size of 4 x 20 (4 x 2rs symbols) and data block_g <6,0> with the size of 4 x 20 (4 x 2rs symbols) are interleaved according to the symbol as granularity, and are combined into data block <2,0> with the size of 4 x 40 (4 x 4rs symbols); data blocks block_g <3,0> with the size of 4 x 20 (4 x 2rs symbols) and data blocks block_g <7,0> with the size of 4 x 20 (4 x 2rs symbols) are interleaved according to the symbol as granularity, and are combined into data blocks block <3,0> with the size of 4 x 40 (4 x 4rs symbols). Similarly, bit distribution and mapping can be performed on 8 groups of encoded data streams to obtain 4 modulated data streams.

Fig. 13 is a flow chart of the de-bit distribution and inverse mapping. As shown in fig. 13, the receiving end receives 4 demodulated data streams from 4 physical channels, and performs de-distribution and inverse mapping on the 4 demodulated data streams to obtain 32 first data streams, respectively. It can be seen that the 32 first data streams include 8 data stream sets, each data stream set includes 4 consecutive first data streams, and 8 first data streams among the b-th data stream set and the b+4-th data stream set are from the b-th demodulated data stream, 0.ltoreq.b.ltoreq.3. It should be understood that the bit distribution and inverse mapping shown in fig. 13 is the inverse operation of the bit distribution and mapping shown in fig. 12, and those skilled in the art may derive the specific implementation of fig. 13 based on the description of fig. 12, which is not repeated here.

It should be noted that, as shown in fig. 13, there is an out-of-order and skew between the 4 demodulated data streams due to the difference of the transmission mediums. The receiving end respectively performs de-distribution and inverse mapping on the 4 demodulated data streams to obtain 32 first data streams, wherein 8 first data streams from the same demodulated data stream in the 32 first data streams do not have disorder and skew, and first data streams from different demodulated data streams in the 32 first data streams have disorder and skew. It should be understood that, since the receiving and transmitting ends are specified according to the protocol, the receiving end can know which channels have no skew and no disorder, and the receiving end can also know the corresponding relationship between the virtual channels and the physical channels, so that the receiving end knows the positions of the physical channels, and can know the correct sequence and channel serial number of the corresponding virtual channels. It is clear that, unlike the process flow shown in fig. 4, in the process flow shown in fig. 11, the receiving end may not perform channel Deskew (Deskew) or channel Reorder (Lane Reorder).

Fig. 14 is a schematic flow chart of another solution channel permutation in the embodiment of the present application. As shown in fig. 14, 32 rows represent 32 data streams, respectively, and 16 columns represent 16 symbols in each data stream, respectively. Specifically, with each continuous 4 columns of the data stream as one period, the positions of the first two columns of symbols in each period before and after the channel de-permutation are kept unchanged, and the positions of the second two columns of symbols in each period before and after the channel de-permutation are changed. Taking fig. 10 as an example, the last two columns of symbols in each period in data stream 0 exchange positions with the last two columns of symbols in the corresponding period in data stream 16, the last two columns of symbols in each period in data stream 1 exchange positions with the last two columns of symbols in the corresponding period in data stream 17, and so on, the last two columns of symbols in each period in data stream 14 exchange positions with the last two columns of symbols in the corresponding period in data stream 30, and the last two columns of symbols in each period in data stream 15 exchange positions with the last two columns of symbols in the corresponding period in data stream 31.

It should be noted that, in addition to the above-described 200G per encoded data stream scene of 800GE, the process flow shown in fig. 11 may also be applied to other scenes such as 200G per lane of 1.6TbE, for example, in the 200G per lane scene of 1.6TbE, n is fixed to 8, that is, 32 encoded data streams are fixedly transmitted through 8 physical channels. The specific implementation of bit distribution and mapping, bit de-distribution and inverse mapping, and de-lane permutation in the 200G per lane scenario of 1.6TbE can be deduced by those skilled in the art based on the above description of the 200G per scenario of 800GE, and will not be repeated here.

Fig. 15 is a schematic diagram of a third process flow of the transceiver end in the embodiment of the present application. Unlike the embodiment shown in fig. 4, the embodiment shown in fig. 15 is mainly directed to a hash (break) scenario. In a possible implementation manner, when the transmitting end performs channel reordering on the data streams, the first AM set corresponding to 800GE described above may be used to match the 32 data streams respectively. If the 32 data streams cannot be matched with the sequences of UM0, UM1, UM2, UM3, UM4 and UM5 in each of the first AM sets, an AM set corresponding to 200GE can be adopted for respectively matching the 32 data streams, and if the sequences of UM0, UM1, UM2, UM3, UM4 and UM5 in the AM set corresponding to 200GE can be matched, the transmitting end can not execute channel replacement operation. Similarly, when the receiving end reorders the channels of the data streams, the second AM set corresponding to 800GE described above may be used to match the 32 data streams respectively. If the sequences of the 32 data streams including UM0, UM1, UM2, UM3, UM4, UM5 in the second AM set cannot be matched, the matching of the 32 data streams with the AM set corresponding to 200GE may be attempted, and if the sequences including UM0, UM1, UM2, UM3, UM4, UM5 in the AM set corresponding to 200GE can be matched, the receiving end may not perform the operation of channel de-permutation. It should be understood that the AM set corresponding to 200GE is defined in the existing standard and is not specifically described herein. Through the mode, the framework provided by the application can be suitable for a break scene, and the expansibility of the scheme is improved.

Fig. 16 is a schematic diagram of a fourth process flow of the transceiver end in the embodiment of the present application. Unlike the embodiment shown in fig. 4, in this embodiment, the sender performs bit multiplexing (bit multiplexing) on 32 data streams before performing AM locking. And carrying out bit multiplexing on every 4 data streams in the 32 data streams to obtain 1 data stream, so as to obtain 8 total data streams after the bit multiplexing. Then, AM locking, convolutional interleaving, inner code encoding and other operations are respectively carried out on the 8 data streams. Correspondingly, after the receiving end performs AM locking on the 8 data streams respectively, the receiving end further performs bit demultiplexing (De-bit multiplexing) on the 8 data streams respectively. And carrying out bit demultiplexing on each data stream to obtain 4 data streams, so that 32 data streams are recovered after the bit demultiplexing. In this embodiment, the transmitting end and the receiving end perform AM locking according to the same AM set, and this embodiment marks the AM set as a third AM set, where the third AM set is obtained by transforming based on the first AM set.

In one possible implementation, the first AM set transforms to a third AM set satisfying equation 2 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

Wherein am_in < i, j > represents the j-th bit of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th bit of the i-th third AM subset in the third AM set, floor ((j% 4)/2) represents the quotient of (j% 4)/2 rounded down, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor (j/4) represents the quotient of j/4 rounded down, 0.ltoreq.i.ltoreq.7, 0.ltoreq.j.ltoreq.479.

That is, am_in corresponding to am_out < i=0, j=0 > is am_in < i=0, j=0 >,

am_in corresponding to am_out < i=0, j=1 > is am_in < i=1, j=0 >,

am_in corresponding to am_out < i=0, j=2 > is am_in < i=16, j=0 >,

am_in corresponding to am_out < i=0, j=3 > is am_in < i=17, j=0 >.

The four together can be written as:

the second set of AM's obtained in the manner described above may be as shown in table 3 below. Since the transmitting end performs the AM locking after performing the bit multiplexing on the 32 data streams to obtain 8 data streams, the third AM set includes 8 third AM subsets, and each third AM subset is composed of 480 bits in total of { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5 }. CM0 is 32 bits long, CM1 is 32 bits long, …, UM5 is 32 bits long.

TABLE 3 Table 3

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Fig. 17 is a schematic diagram of a fifth process flow of the transceiver end in the embodiment of the present application. Unlike the embodiment shown in fig. 4, in this embodiment, the transmitting end performs symbol multiplexing (symbol multiplexing) on 32 data streams before performing AM locking. And carrying out symbol multiplexing on every 4 data streams in the 32 data streams to obtain 1 data stream, so as to obtain 8 total data streams after symbol multiplexing. Then, AM locking, convolutional interleaving, inner code encoding and other operations are respectively carried out on the 8 data streams. Correspondingly, after the receiving end performs AM locking on the 8 data streams, the receiving end further performs symbol demultiplexing (De-symbol multiplexing) on the 8 data streams, respectively. And performing symbol demultiplexing on each data stream to obtain 4 data streams, so that 32 data streams are recovered after symbol demultiplexing. In this embodiment, the transmitting end and the receiving end perform AM locking according to the same AM set, and this embodiment marks the AM set as a fourth AM set, where the fourth AM set is obtained by transforming based on the first AM set described above.

In one possible implementation, the first AM set transforms to a fourth AM set satisfying equation 3 below:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

Wherein am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th fourth AM subset in the fourth AM set, floor ((j% 4)/2) represents the quotient of (j% 4)/2 rounded down, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor (j/4) represents the quotient of j/4 rounded down, 0.ltoreq.i.ltoreq.7, 0.ltoreq.j.ltoreq.48.

The fourth set of AM's obtained in the manner described above may be as shown in table 4 below. Since the transmitting end performs symbol multiplexing on 32 data streams to obtain 8 data streams and then performs AM locking, the fourth AM set includes 8 fourth AM subsets, and each fourth AM subset is composed of 48 symbols in total { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5 }. CM0 is 32 bits long, CM1 is 32 bits long, …, UM5 is 32 bits long.

TABLE 4 Table 4

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It should be noted that the embodiment shown in fig. 17 is mainly applied to the 800GE scenario. In some possible embodiments, the system architecture shown in fig. 17 may also be applied to the scenario of 1.6TbE, where implementation manners of symbol multiplexing, symbol demultiplexing, and AM locking are similar, and details are not repeated here.

Fig. 18 is a schematic diagram of a sixth process flow of the transceiver end in the embodiment of the present application. Unlike the embodiment shown in fig. 4, in this embodiment, the transmitting end performs symbol multiplexing (symbol multiplexing) on 32 data streams before performing AM locking. And carrying out symbol multiplexing on every 8 data streams in the 32 data streams to obtain 1 data stream, so that 4 total data streams are obtained after symbol multiplexing. Then, the operations of AM locking, convolution interleaving, inner code encoding and the like are respectively carried out on the 4 data streams. Correspondingly, after the receiving end performs AM locking on the 4 data streams respectively, the receiving end further performs symbol demultiplexing (De-symbol multiplexing) on the 4 data streams respectively. And performing symbol demultiplexing on each data stream to obtain 8 data streams, so that 32 data streams are recovered after symbol demultiplexing. In this embodiment, the transmitting end and the receiving end perform AM locking according to the same AM set, and this embodiment marks the AM set as a fifth AM set, where the fifth AM set is obtained by transforming the first AM set.

In one possible implementation, the first AM set transforms to a fifth AM set satisfying equation 4 below:

Where am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th fifth AM subset in the fifth AM set, floor ((j% 4)/2) represents the quotient of (j% 4)/2 rounded down, j%4 represents the remainder of j divided by 4, j%2 represents the remainder of j divided by 2, floor ((j% 8)/4) represents the quotient of (j% 8)/4 rounded down, j%8 represents the remainder of j divided by 8, floor (j/8) represents the quotient of j/8 rounded down, 0.ltoreq.i.ltoreq.3, 0.ltoreq.j.ltoreq.96.

The fifth set of AM's obtained in the manner described above may be as shown in table 5 below. Since the transmitting end performs symbol multiplexing on 32 data streams to obtain 4 data streams and then performs AM locking, the fifth AM set includes 4 fifth AM subsets, and each fifth AM subset is composed of 96 symbols { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5 }. CM0 is 64 bits long, CM1 is 64 bits long, …, UM5 is 64 bits long.

TABLE 5

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The data processing device provided in the present application is described below.

Fig. 19 is a schematic structural diagram of a data processing apparatus in an embodiment of the present application. As shown in fig. 19, the data processing apparatus includes a decoding unit 101, a deconvolution interleaving unit 102, and an alignment mark locking unit 103. The decoding unit 101 is configured to perform the operation of step 801 described above. The deconvolution interleaving unit 102 is configured to perform the operation of step 802 described above. The alignment mark locking unit 103 is used to perform the operation of step 803 described above. In some possible embodiments, the data processing apparatus further includes a de-lane permuting unit 104, a lane deskewing unit 105, and a lane reordering unit 106. The de-lane permuting unit 104 is configured to perform the operation of step 806. The channel correction unit 105 is configured to perform the operation of step 804 described above. The channel reordering unit 106 is configured to perform the operation of step 805 described above. It should be understood that the specific operations performed by the data processing apparatus may be described with reference to the embodiment shown in fig. 8, which is not described herein.

Fig. 20 is a schematic diagram of another structure of the data processing apparatus in the embodiment of the present application. As shown in fig. 20, in other possible embodiments, the data processing apparatus further includes a bit demultiplexing unit 107 (symbol demultiplexing unit 107). The operations performed by the bit demultiplexing unit 107 (symbol demultiplexing unit 107) may be described with reference to the embodiments shown in fig. 16-18, and are not described herein.

It should be understood that the apparatus provided in this application may be implemented in other manners. For example, the unit division in the above apparatus is only one logic function division, and there may be another division manner when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or may be each independent physical unit, or may be two or more functional units integrated in one processing unit. The integrated units may be implemented in hardware or in software functional units.

Fig. 21 is a schematic diagram of another structure of the data processing apparatus in the embodiment of the present application. As shown in fig. 21, the data processing apparatus includes a processor 201, a memory 202, and a transceiver 203. The processor 201, memory 202 and transceiver 203 are interconnected by wires. Wherein the memory 202 is used to store program instructions and data. Specifically, the transceiver 203 is configured to receive a data stream from a transmitting end, and the processor 201 is configured to perform a data processing method provided in the present application. In one possible implementation, the processor 201 may include the decoding unit 101, the deconvolution interleaving unit 102, the alignment mark locking unit 103, the de-lane replacing unit 104, the lane deskewing unit 105, and the lane reordering unit 106 described above with reference to fig. 19. In another possible embodiment, the processor 201 may include the decoding unit 101, the deconvolution interleaving unit 102, the alignment mark locking unit 103, and the bit demultiplexing unit 107 (symbol demultiplexing unit 107) shown in fig. 20 described above.

It should be noted that the processor shown in fig. 21 may be a general-purpose central processing unit (Central Processing Unit, CPU), a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The memory shown in FIG. 21 described above may store an operating system and other application programs. When the technical solution provided in the embodiments of the present application is implemented by software or firmware, program codes for implementing the technical solution provided in the embodiments of the present application are stored in a memory and executed by a processor. In one embodiment, the processor may include memory within. In another embodiment, the processor and the memory are two separate structures.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

Those of ordinary skill in the art will appreciate that all or a portion of the steps implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing the relevant hardware, where the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a random access memory, etc. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

When implemented in software, the method steps described in the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

Claims

1. A method of data processing, comprising:

decoding z first data streams respectively to obtain z second data streams, wherein the z first data streams are subjected to Forward Error Correction (FEC) coding, and z is an integer greater than 1;

deconvolution interleaving is respectively carried out on the z second data streams to obtain z third data streams;

and respectively performing AM locking on the z third data streams according to a second alignment mark AM set to obtain z fourth data streams, wherein the second AM set is obtained by transforming a first AM set preset by a transmitting end, the first AM set comprises x first AM subsets, x is an integer greater than 1, the second AM set comprises z second AM subsets, and the z second AM subsets are used for respectively performing AM locking with the z third data streams.

2. The method of claim 1, wherein x = 32 and z = 32, each of the first subset of AMs comprises 12 symbols and each of the second subset of AMs comprises 12 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 1 as follows:

AM_out<i,j>＝AM_in<(i+16*Floor(j/2))％32,j>

3. The method according to claim 1 or 2, wherein each of the second AM subsets comprises 15 bytes, the 15 bytes of each of the second AM subsets being represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of CM0, CM1, CM2, CM3, CM4, and CM5 in the second AM subset are used to match in order with the total of 6 bytes of 0 th byte, 1 st byte, 2 nd byte, 4 th byte, 5 th byte, and 6 th byte, respectively, in every 7 consecutive bytes of the third data stream for AM locking.

4. The method of claim 3, wherein an AM is enabled if the number of matches successful in the 6 matches of the second subset of AMs with the third data stream, respectively, is greater than or equal to P; if the AM is valid for R times, the AM locking condition of the third data stream is achieved;

if the number of successful matches in the 6 matches performed by the second AM subset and the third data stream is less than P, one AM failure is realized; if the AM failure is realized for S times, the AM unlocking condition of the third data stream is achieved;

wherein p=3, 4 or 5, r=1 or 2, s=2, 3, 4 or 5.

5. The method according to any one of claims 1 to 4, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, the method further comprises:

and reordering channels of the z fourth data streams according to the second AM set so that the z fourth data streams are arranged according to a preset sequence, wherein the z second AM subsets are used for respectively matching with the AM in the z fourth data streams, each second AM subset has a corresponding channel number, and the fourth data streams are arranged according to the channel numbers of the successfully matched second AM subsets.

6. The method of claim 5, wherein each of the second subset of AMs comprises 15 bytes, the 15 bytes of each of the second subset of AMs being represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of UM0, UM1, UM2, UM3, UM4, and UM5 in the second AM subset are used to match 6 bytes of the corresponding location in the AM of the fourth data stream, respectively.

7. The method according to any one of claims 1 to 6, wherein z = 32, and the 32 second AM subsets in the second set of AM are in channel numbering order:

8. The method according to any one of claims 1 to 7, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, the method further comprises:

and performing de-channel replacement on the z fourth data streams to obtain z fifth data streams.

9. The method of claim 8, wherein z = 32, each of the fourth data streams comprises a plurality of symbol sets, each of the fifth data streams comprises a plurality of symbol sets, each of the symbol sets comprises two consecutive symbols, each of the fourth data streams has a first symbol set adjacent to a second symbol set, and each of the fifth data streams has a first symbol set adjacent to a second symbol set;

the first symbol set in the fifth data stream a is from the first symbol set in the fourth data stream a, the first symbol set in the fifth data stream a is the same as the first symbol set in the fourth data stream a, the second symbol set in the fifth data stream a is from the second symbol set in the fourth data stream (a+16)% 32, the second symbol set in the fifth data stream a is the same as the second symbol set in the fourth data stream (a+16)% 32, wherein 0.ltoreq.a is no more than 31, and (a+16)% 32 represents the remainder after dividing a+16 by 32.

10. The method of claim 1, wherein x = 32, z = 8, each of the first subset of AMs comprises 480 bits, each of the second subset of AMs comprises 480 bits, the first set of AMs transformed to the second set of AMs satisfying equation 2 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

11. The method of claim 10, wherein the 8 second AM subsets in the second AM set are in channel numbering order:

12. the method according to claim 10 or 11, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, the method further comprises:

and carrying out bit demultiplexing on each fourth data stream to obtain 4 fifth data streams so as to obtain 32 fifth data streams in total.

13. The method of claim 1, wherein x = 32, z = 8, each of the first subset of AMs comprises 48 symbols, each of the second subset of AMs comprises 48 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 3 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

14. The method of claim 13, wherein the 8 second AM subsets in the second AM set are in channel numbering order:

15. the method according to claim 13 or 14, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, the method further comprises:

and performing symbol demultiplexing on each fourth data stream to obtain 4 fifth data streams, so as to obtain 32 fifth data streams in total.

16. The method of claim 1, wherein x = 32, z = 4, each of the first subset of AMs comprises 96 symbols, each of the second subset of AMs comprises 96 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 4 as follows:

am_out < i, j > = am_in < i > = 4+floor ((j% 4)/2) = 16+j%2+floor ((j% 8)/4) = 2, floor (j/8) >, wherein am_in < i, j > represents the j-th symbol of the i-th first AM subset in the first AM set, am_out < i, j > represents the j-th symbol of the i-th second AM subset in the second AM set, floor ((j% 4)/2) represents a downward rounding of the quotient of (j% 4)/2, j%4 represents a remainder of division of j by 4, j%2 represents a remainder of division of j by 2, floor ((j% 8)/4) represents a downward rounding of the quotient of (j% 8)/4, j%8 represents a downward rounding of the quotient of j/8, floor (j/8) represents a downward rounding of 0.ltoreq.i.ltoreq.3, 0.ltoreq.j 96.

17. The method of claim 16, wherein the 4 second AM subsets in the second AM set are in channel numbering order:

18. the method according to claim 16 or 17, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, the method further comprises:

And performing symbol demultiplexing on each fourth data stream to obtain 8 fifth data streams, so as to obtain 32 fifth data streams in total.

19. The method according to any one of claims 1 to 18, wherein before decoding the z first data streams to obtain z second data streams, respectively, the method further comprises:

receiving n demodulation data streams from n channels respectively, wherein n is more than 1 and less than or equal to z;

and respectively carrying out de-distribution and inverse mapping on the n demodulated data streams to obtain the z first data streams.

20. The method according to any one of claims 1 to 19, wherein after AM locking the z third data streams according to the second AM set to obtain z fourth data streams, respectively, the method further comprises:

and carrying out channel deviation correction on the z fourth data streams.

21. The method according to any one of claims 1 to 20, wherein before decoding the z first data streams to obtain z second data streams, the method further comprises:

and respectively carrying out code word synchronization on the z first data streams so as to align symbols in the z first data streams.

22. A data processing apparatus, comprising: a decoding unit, a deconvolution interleaving unit and a pair Ji Biaoshi AM locking unit;

The decoding unit is used for respectively decoding z first data streams to obtain z second data streams, wherein the z first data streams are subjected to Forward Error Correction (FEC) coding, and z is an integer greater than 1;

the deconvolution interleaving unit is used for respectively deconvoluting and interleaving the z second data streams to obtain z third data streams;

the AM locking unit is used for respectively carrying out AM locking on the z third data streams according to a second AM set to obtain z fourth data streams, the second AM set is obtained by converting a first AM set preset by a transmitting end, the first AM set comprises x first AM subsets, x is an integer greater than 1, the second AM set comprises z second AM subsets, and the z second AM subsets are used for respectively carrying out AM locking on the z third data streams.

23. The data processing apparatus of claim 22, wherein x = 32, z = 32, each of the first subset of AMs comprises 12 symbols, each of the second subset of AMs comprises 12 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 1 as follows:

AM_out<i,j>＝AM_in<(i+16*Floor(j/2))％32,j>

24. A data processing apparatus according to claim 22 or 23, wherein each of said second AM subsets comprises 15 bytes, the 15 bytes of each of said second AM subsets being represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of CM0, CM1, CM2, CM3, CM4, and CM5 in the second AM subset are used to match in order with the total of 6 bytes of 0 th byte, 1 st byte, 2 nd byte, 4 th byte, 5 th byte, and 6 th byte, respectively, in every 7 consecutive bytes of the third data stream for AM locking.

25. The data processing apparatus according to claim 24, wherein one AM valid is achieved if a number of successful matches among 6 matches performed by the second subset of AM and the third data stream, respectively, is greater than or equal to P; if the AM is valid for R times, the AM locking condition of the third data stream is achieved;

wherein p=3, 4 or 5, r=1 or 2, s=2, 3, 4 or 5.

26. The data processing apparatus according to any one of claims 22 to 25, wherein the data processing apparatus further comprises a lane reordering unit;

after the z third data streams are respectively AM-locked according to the second AM set to obtain z fourth data streams, the channel reordering unit is configured to reorder the channels of the z fourth data streams according to the second AM set, so that the z fourth data streams are arranged according to a preset sequence, where the z second AM subsets are used to match with the AMs in the z fourth data streams respectively, each second AM subset has a corresponding channel number, and the fourth data streams are arranged according to the channel numbers of the successfully matched second AM subsets.

27. The data processing apparatus of claim 26, wherein each of the second subset of AMs comprises 15 bytes, the 15 bytes of each of the second subset of AMs being represented in turn as: { CM0, CM1, CM2, UP0, CM3, CM4, CM5, UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}, the total of 6 bytes of UM0, UM1, UM2, UM3, UM4, and UM5 in the second AM subset are used to match 6 bytes of the corresponding location in the AM of the fourth data stream, respectively.

28. The data processing apparatus according to any one of claims 22 to 27, wherein z = 32, the 32 second AM subsets of the second AM set being in channel number order:

29. the data processing apparatus according to any one of claims 22 to 28, wherein the data processing apparatus further comprises a de-lane permuting unit;

and after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the de-channel replacement unit is used for performing de-channel replacement on the z fourth data streams to obtain z fifth data streams.

30. The data processing apparatus of claim 29, wherein z = 32, each of the fourth data streams includes a plurality of symbol sets, each of the fifth data streams includes a plurality of symbol sets, each of the symbol sets includes two consecutive symbols, the first symbol set and the second symbol set in each of the fourth data streams are adjacent, and the first symbol set and the second symbol set in each of the fifth data streams are adjacent;

31. The data processing apparatus of claim 22, wherein x = 32, z = 8, each of the first subset of AMs comprises 480 bits, each of the second subset of AMs comprises 480 bits, the first set of AMs transformed to the second set of AMs satisfying equation 2 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

32. The data processing apparatus of claim 31, wherein the 8 second AM subsets in the second AM set are in order of channel number:

33. the data processing apparatus according to claim 31 or 32, wherein the data processing apparatus further comprises a bit demultiplexing unit;

and after performing AM locking on the z third data streams according to the second AM set to obtain z fourth data streams, the bit demultiplexing unit is further configured to perform bit demultiplexing on each fourth data stream to obtain 4 fifth data streams, so as to obtain 32 fifth data streams in total.

34. The data processing apparatus of claim 22, wherein x = 32, z = 8, each of the first subset of AMs comprises 48 symbols, each of the second subset of AMs comprises 48 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 3 as follows:

AM_out<i,j>＝AM_in<i*2+Floor((j％4)/2)*16+j％2,Floor(j/4)>

35. The data processing apparatus of claim 34, wherein the 8 second AM subsets in the second AM set are in order of channel number:

36. the data processing apparatus according to claim 34 or 35, wherein the data processing apparatus further comprises a symbol demultiplexing unit;

and after performing AM locking on the z third data streams respectively according to the second AM set to obtain z fourth data streams, the symbol demultiplexing unit is used for performing symbol demultiplexing on each fourth data stream to obtain 4 fifth data streams so as to obtain 32 fifth data streams in total.

37. The data processing apparatus of claim 22, wherein x = 32, z = 4, each of the first subset of AMs comprises 96 symbols, each of the second subset of AMs comprises 96 symbols, the first set of AMs transformed to the second set of AMs satisfying equation 4 as follows:

38. The data processing apparatus of claim 37, wherein the 4 second AM subsets in the second AM set are in order of channel number:

39. the data processing apparatus according to claim 37 or 38, wherein the data processing apparatus further comprises a symbol demultiplexing unit;

And after performing AM locking on the z third data streams respectively according to the second AM set to obtain z fourth data streams, the symbol demultiplexing unit is used for performing symbol demultiplexing on each fourth data stream to obtain 8 fifth data streams so as to obtain 32 fifth data streams in total.

40. The data processing apparatus according to any one of claims 22 to 39, further comprising a de-distribution and inverse mapping unit;

before decoding the z first data streams to obtain z second data streams, the de-distribution and inverse mapping unit is configured to:

41. The data processing apparatus according to any one of claims 22 to 40, further comprising a channel deskewing unit;

and after the third data streams are respectively AM locked according to the second AM set to obtain fourth data streams, the channel correction unit is used for carrying out channel correction on the fourth data streams.

42. The data processing apparatus according to any one of claims 22 to 41, further comprising a codeword synchronization unit;

Before the z first data streams are decoded respectively to obtain z second data streams, the codeword synchronization unit is configured to perform codeword synchronization on the z first data streams respectively, so that symbols in the z first data streams are aligned.