CN117895943A

CN117895943A - Analog signal processing circuit, method, chip and device for high-precision ADC

Info

Publication number: CN117895943A
Application number: CN202410072646.4A
Authority: CN
Inventors: 苏萌; 侯佳力; 原义栋; 胡毅; 赵天挺; 李振国; 王亚彬; 宋海飞
Original assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2024-01-18
Filing date: 2024-01-18
Publication date: 2024-04-16

Abstract

The present disclosure relates to the technical field of integrated circuits, and in particular, to an analog signal processing circuit, method, chip and device for a high-precision ADC, where the circuit includes: a main amplifier module, a main ADC module, an auxiliary amplifier module, and an auxiliary ADC module, and a first switch; the auxiliary ADC module is used for converting the conditioned analog signals to be converted and outputting a first converted digital code through the digital output end; the main ADC module is used for establishing the input voltage of the main ADC module to the target precision according to the conditioned analog signal to be converted and the first digital code so as to realize sampling of the analog signal. When the input voltage of the main ADC module is changed in a large swing, the circuit protects the main amplifier module from being interfered by quick charge, and the power consumption and the area cost of the auxiliary ADC and the auxiliary amplifier are small, so that the power consumption and the area cost of the analog signal processing circuit are saved.

Description

Analog signal processing circuit, method, chip and device for high-precision ADC

Technical Field

The disclosure relates to the technical field of integrated circuits, and in particular relates to an analog signal processing circuit, an analog signal processing method, an analog signal processing chip and an analog signal processing device for a high-precision ADC.

Background

An analog-to-digital converter (Analogue to Digital Converter, ADC) is a device that converts a continuously varying analog signal into a discrete digital signal, and is used in various data acquisition systems. The charge sharing successive approximation (successive approximation register, SAR) ADC is a common ADC architecture for realizing high-precision conversion, has the characteristics of high conversion efficiency, small occupied area, good instantaneity and the like, and is widely applied to the fields of industry, measurement, medical treatment and the like.

For a traditional SAR ADC, an analog signal to be converted needs to be adjusted to a proper range through an amplifier, and the driving capability of the signal is increased, so that a sampling circuit of the ADC can be effectively driven. However, during the charging of the sampling capacitor inside, especially in a multiplexing system or in a discrete time sampling condition, since a large voltage step is generated at the input node of the SAR ADC, the amplifier or the input signal source is greatly disturbed, and increasing the bandwidth of the amplifier to increase the signal establishment speed causes an increase in noise. In order to solve the problem, the high-precision ADC input signal processing circuit in the related art is configured by adding an additional auxiliary amplifier module and connecting the inverting input terminal and the output terminal of the auxiliary amplifier module, so that in the ADC sampling stage, the input terminal voltage of the ADC can be quickly established to be close to the output terminal voltage of the main amplifier module by means of the buffer, and then, when the output terminal of the main amplifier module is directly connected to the input terminal of the ADC, the input terminal voltage of the ADC can be accurately established, so that the output terminal voltage of the main amplifier module is still kept in a stable state and is not disturbed by charging of the sampling capacitor, and the signal sampled by the ADC has lower noise due to the smaller bandwidth of the main amplifier module.

However, in the sampling phase of the above circuit, the process of precharging the sampling capacitor is completely performed by the precharge buffer, and if the precharge time is to be made as short as possible, the amplifier as the precharge buffer needs to have a large slew rate and a large bandwidth, the amplifier itself generates large power consumption, and occupies a large area, resulting in large power consumption and area overhead of the circuit.

Disclosure of Invention

In order to solve the problems in the related art, the embodiments of the present disclosure provide an analog signal processing circuit, method, chip, and apparatus for a high-precision ADC.

In a first aspect, embodiments of the present disclosure provide an analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a main ADC module, an auxiliary amplifier module, and an auxiliary ADC module, and a first switch;

The input end of the auxiliary amplifier module is connected with the input signal end, the output end of the auxiliary amplifier module is connected with the analog input end of the auxiliary ADC module, and the auxiliary amplifier module is used for conditioning the analog signal to be converted which is input by the input signal end and outputting a first conditioned analog signal to be converted through the output end;

The digital output end of the auxiliary ADC module is connected with the digital input end of the main ADC module, and the auxiliary ADC module is used for converting a first conditioned analog signal to be converted and outputting a first converted digital code through the digital output end, wherein the first digital code contains information of the analog signal to be converted;

The input end of the main amplifier module is connected with the input signal end, the output end of the main amplifier module is connected with the first wiring end of the first switch, and the main amplifier module is used for conditioning the analog signal to be converted which is input by the input signal end and outputting a second conditioned analog signal to be converted through the output end;

the analog input end of the main ADC module is connected with the second terminal of the first switch, and the main ADC module is used for establishing the input voltage of the main ADC module to the input voltage meeting the target precision requirement according to the second conditioned analog signal received by the analog input end and the first digital code received by the digital input end so as to realize sampling of the analog signal under the input voltage;

The number of bits of the main ADC module is larger than that of the auxiliary ADC module.

In a possible implementation manner of the present disclosure, when the main ADC module is in a sampling stage and the first switch is in an off state, the main ADC module is configured to perform an action according to information of the analog signal to be converted included in the first digital code, so as to generate a sampling precharge voltage; the difference between the sampling precharge voltage and the voltage of the output end of the main amplifier module is smaller than or equal to a preset error threshold value.

In a possible implementation manner of the present disclosure, when the first switch is switched from an open state to a closed state, the main ADC module is configured to charge according to the analog signal to be converted after the second conditioning based on the sampled precharge voltage, so that an input voltage of the main ADC module is the same as a voltage of an output end of the main amplifier module.

In a possible implementation of the disclosure, the main ADC module includes: the sampling device comprises a sampling capacitor array, a sampling switch array corresponding to the sampling capacitor array, a second switch, a comparator and a control logic module;

The upper polar plate of each sampling capacitor in the sampling capacitor array is connected together and connected with the first wiring end of the second switch and the reverse input end of the comparator, and the lower polar plate of each sampling capacitor is respectively connected with the first wiring end of the corresponding sampling switch;

the second wiring end of each sampling switch in the sampling switch array is connected together and connected with a first voltage input end, and the first voltage input end is connected with the second wiring end of the first switch;

The third wiring end of each sampling switch is connected together and connected with the second voltage input end; the second voltage input end is used for inputting a first reference voltage;

the fourth wiring terminal of each sampling switch is connected together and connected with the third voltage input terminal; the third voltage input end is used for inputting a grounding voltage;

a second terminal of the second switch is connected to the fourth voltage input terminal;

The positive input end of the comparator is connected with the fifth voltage input end, and the output end of the comparator is connected with the first input end of the control logic module; wherein the fourth voltage input end and the fifth voltage input end are used for inputting a second reference voltage;

The output end of the control logic module is connected with the sampling switch array, and the second input end of the control logic module is connected with the digital output end of the auxiliary ADC module; the connection direction between the auxiliary ADC module and the control logic module is from the output end of the auxiliary ADC module to the second input end of the control logic module.

In a possible implementation manner of the present disclosure, when the first switch is in an open state and the second switch is in a closed state, the control logic module is configured to control, according to the first digital code, a connection state of sampling switches in the sampling switch array, so that logic states of M sampling capacitors in a high position in the sampling capacitor array are consistent with the first digital code, and then control a first terminal and a second terminal of each sampling switch to be connected, so that the sampling capacitor array generates a sampling precharge voltage; wherein, the value of M is the same as the digit of the first digital code, and M is a positive integer.

In a possible implementation manner of the present disclosure, when the first switch is switched from an open state to a closed state, the sampling capacitor array is configured to charge according to the analog signal to be converted after the second conditioning based on the sampling precharge voltage, so that the voltages of the lower plates of the M sampling capacitors are established to be the same as the voltages of the output ends of the main amplifier module.

In a possible implementation manner of the present disclosure, the sampling capacitor array is any one of the following: single-ended capacitive array, differential capacitive array.

In a second aspect, embodiments of the present disclosure provide an analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a third switch, a main ADC module, and an auxiliary ADC module;

The input end of the main amplifier module is connected with the input signal end, the output end of the main amplifier module is connected with the first wiring end of the third switch and the analog input end of the auxiliary ADC module, and the main amplifier module is used for conditioning the analog signal to be converted which is input by the input signal end and outputting the conditioned analog signal to be converted through the output end;

The digital output end of the auxiliary ADC module is connected with the digital input end of the main ADC module, and the auxiliary ADC module is used for converting the conditioned analog signals to be converted and inputting a converted second digital code through the digital output end;

The analog input end of the main ADC module is connected to the second terminal of the third switch, and the main ADC module is used for establishing the input voltage of the main ADC module to the input voltage meeting the target precision requirement according to the conditioned analog signal to be converted received through the analog input end and the second digital code received through the digital input end so as to realize sampling of the analog signal under the input voltage;

In a third aspect, embodiments of the present disclosure provide an analog signal processing method for a high-precision ADC, applied to a circuit according to any one of the implementations of the first aspect, the method including:

acquiring an analog signal to be converted when a main ADC module in the circuit is in a sampling stage;

The analog signals to be converted are conditioned through a main amplifier module and an auxiliary amplifier module in the circuit, the analog signals to be converted conditioned by the auxiliary amplifier module are converted through the auxiliary ADC module in the circuit, a conversion result is obtained, and the conversion result is sent to the main ADC module;

And according to the analog signals to be converted conditioned by the main amplifier module and the conversion result, establishing the input voltage of the main ADC module to the input voltage meeting the target precision requirement so as to realize sampling of the analog signals under the input voltage.

In a possible implementation manner of the disclosure, the establishing the input voltage of the main ADC module to the input voltage meeting the target precision requirement according to the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to sample the analog signal under the input voltage, includes:

When a first switch between the main ADC module and the main amplifier module is in an off state, according to the conversion result, the logic states of M sampling capacitors which are positioned at high positions in the main ADC module are adjusted to be consistent with the conversion result, and the lower polar plates of all the sampling capacitors in the main ADC module are short-circuited to generate sampling precharge voltage; the difference value between the sampling precharge voltage and the voltage of the output end of the main amplifier module is smaller than or equal to a preset error threshold value; the value of M is the same as the bit number of the conversion result, and M is a positive integer;

Switching the first switch to a closed state;

And charging a sampling capacitor in the main ADC module according to the analog signal to be converted conditioned by the main amplifier module, so that the input voltage of the main ADC module is established to be the same as the voltage of the output end of the main amplifier module from the sampling precharge voltage.

In a fourth aspect, in an embodiment of the present disclosure, there is provided an analog signal processing method for a high-precision ADC, applied to the circuit as set forth in any one of the implementations of the second aspect, the method including:

The analog signals to be converted are conditioned through a main amplifier module in the circuit, the conditioned analog signals to be converted are converted through an auxiliary ADC module in the circuit, a conversion result is obtained, and the conversion result is sent to the main ADC module;

And according to the conditioned analog signals to be converted and the conversion result, establishing the input voltage of the main ADC module to the input voltage meeting the target precision requirement so as to realize sampling of the analog signals under the input voltage.

In a fifth aspect, embodiments of the present disclosure provide a chip comprising circuitry as in any of all possible implementations of the first and second aspects above.

In a sixth aspect, embodiments of the present disclosure provide an electronic device including a chip as described in the fifth aspect.

An analog signal processing circuit for a high-precision ADC provided according to an embodiment of the disclosure, the circuit including: a main amplifier module, a main ADC module, an auxiliary amplifier module and an auxiliary ADC module, and a first switch. The circuit structure forms two parallel signal links, can control the first switch to be disconnected and rapidly convert analog signals through the link of the auxiliary amplifier module and the auxiliary ADC module so as to obtain digital signals, and transmits the digital signals to the main ADC module, so that rapid precharge inside the main ADC module is realized to generate sampling precharge voltage, the first switch is controlled to be conducted, and the input voltage of the main ADC module is accurately established on the basis of precharge. Therefore, through the circuit, when the input voltage of the main ADC module is changed in a large swing, the main amplifier module is protected from being interfered by quick charge, and compared with an amplifier serving as a precharge buffer in a traditional circuit, the circuit provided by the embodiment of the disclosure has the advantages of large slew rate and bandwidth, low number of auxiliary ADC bits, small power consumption and area cost, small load for the auxiliary amplifier, and high-speed design of the auxiliary amplifier under the condition of small working current, so that the power consumption and area cost of the circuit are saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

Other features, objects and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

FIG. 1 shows one of the schematic diagrams of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 2 shows a second schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 3 shows a third schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 4 shows a fourth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 5 shows a fifth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 6 shows a sixth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

FIG. 7 shows a flow chart of an analog signal processing method for a high-precision ADC according to an embodiment of the present disclosure;

fig. 8 shows a flowchart of yet another analog signal processing method for a high-precision ADC according to an embodiment of the disclosure.

Detailed Description

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, portions irrelevant to description of the exemplary embodiments are omitted in the drawings.

In this disclosure, it should be understood that terms such as "comprises" or "comprising," etc., are intended to indicate the presence of features, numbers, steps, acts, components, portions, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, acts, components, portions, or combinations thereof are present or added.

In addition, it should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In the present disclosure, if an operation of acquiring user information or user data or an operation of presenting user information or user data to another person is referred to, the operations are all operations authorized, confirmed, or actively selected by the user.

As mentioned above, the analog-to-digital converter (Analogue to Digital Converter, ADC) is a device for converting a continuously variable analog signal into a discrete digital signal, and is used in various data acquisition systems. The charge sharing successive approximation (successive approximation register, SAR) ADC is a common ADC architecture for realizing high-precision conversion, has the characteristics of high conversion efficiency, small occupied area, good instantaneity and the like, and is widely applied to the fields of industry, measurement, medical treatment and the like.

For a traditional SAR ADC, an analog signal to be converted needs to be adjusted to a proper range through an amplifier, so that the driving capability of the signal is increased, and the sampling circuit of the ADC can be effectively driven. However, during the charging of the sampling capacitor inside, especially in a multiplexing system or in discrete time sampling conditions, since a large voltage step is generated at the input node of the SAR ADC, the amplifier or the input signal source is greatly disturbed, and increasing the bandwidth of the amplifier to increase the signal establishment speed leads to increased noise. In order to solve the problem, the high-precision ADC input signal processing circuit in the related art is configured by adding an additional auxiliary amplifier module and connecting the inverting input terminal and the output terminal of the auxiliary amplifier module, so that in the ADC sampling stage, the input terminal voltage of the ADC can be quickly established to be close to the output terminal voltage of the main amplifier module by means of the buffer, and then, when the output terminal of the main amplifier module is directly connected to the input terminal of the ADC, the input terminal voltage of the ADC can be accurately established, so that the output terminal voltage of the main amplifier module is still kept in a stable state and is not disturbed by charging of the sampling capacitor, and the signal sampled by the ADC has lower noise due to the smaller bandwidth of the main amplifier module.

Based on the technical drawbacks described above, an analog signal processing circuit for a high-precision ADC according to an embodiment of the disclosure includes: a main amplifier module, a main ADC module, an auxiliary amplifier module and an auxiliary ADC module, and a first switch. The circuit structure forms two parallel signal links, can control the first switch to be disconnected and rapidly convert analog signals through the link of the auxiliary amplifier module and the auxiliary ADC module so as to obtain digital signals, and transmits the digital signals to the main ADC module, so that rapid precharge inside the main ADC module is realized to generate sampling precharge voltage, the first switch is controlled to be conducted, and the input voltage of the main ADC module is accurately established on the basis of precharge. Therefore, through the circuit, when the input voltage of the main ADC module is changed in a large swing, the main amplifier module is protected from being interfered by quick charge, and compared with an amplifier serving as a precharge buffer in a traditional circuit, the circuit provided by the embodiment of the disclosure has the advantages of large slew rate and bandwidth, low number of auxiliary ADC bits, small power consumption and area cost, small load for the auxiliary amplifier, and high-speed design of the auxiliary amplifier under the condition of small working current, so that the power consumption and area cost of the circuit are saved.

Fig. 1 illustrates an analog signal processing circuit for a high-precision ADC according to an embodiment of the disclosure. As shown in fig. 1, the analog signal processing circuit includes a main amplifier module 100, a main ADC module 200, an auxiliary amplifier module 300, and an auxiliary ADC module 400, and a first switch 500;

The input end L ₁ of the auxiliary amplifier module 300 is connected to the input signal end L ₂, the output end L ₃ is connected to the analog input end L ₄ of the auxiliary ADC module, and the auxiliary amplifier module 300 is configured to condition an analog signal to be converted input by the input signal end and output a first conditioned analog signal to be converted through the output end L ₃;

The digital output end L ₅ of the auxiliary ADC module 400 is connected to the digital input end L ₆ of the main ADC module, and the auxiliary ADC module 400 is configured to convert the conditioned analog signal to be converted and output a converted first digital code through the digital output end L ₅, where the first digital code includes information of the analog signal to be converted;

The input end L ₇ of the main amplifier module 100 is connected to the input signal end L ₂, the output end L ₈ is connected to the first terminal L ₉ of the first switch 500, and the main amplifier module 100 is configured to condition the analog signal to be converted input by the input signal end L ₂, and output a second conditioned analog signal to be converted through the output end L ₈;

The analog input end L ₁₀ of the main ADC module 200 is connected to the second terminal L ₁₁ of the first switch, and the main ADC module 200 is configured to establish an input voltage of the main ADC module 200 to an input voltage meeting a target accuracy requirement according to the second conditioned analog signal received through the analog input end L ₁₀ and the first digital code received through the digital input end L ₆, so as to sample the analog signal under the input voltage;

wherein the number of bits of the main ADC block 100 is greater than the number of bits of the auxiliary ADC block 400.

In an embodiment of the present disclosure, each ADC module includes a sampling stage and a conversion stage. In the embodiments of the present disclosure, only the sampling phase and the conversion phase of the auxiliary ADC module and the sampling phase of the main ADC module are involved, and the conversion phase of the main ADC module is not limited.

In one embodiment of the present disclosure, the main amplifier module has a high-precision characteristic, and the bandwidth requirement is not limited.

In one embodiment of the present disclosure, the main ADC module is typically a charge-sharing successive approximation ADC, which has high precision, and the number of bits of the main amplifier module is typically 14-20 bits, but is not limited to 14-20 bits.

In one embodiment of the present disclosure, the auxiliary amplifier module has the characteristics of higher speed and lower precision requirement, and the input range of the auxiliary amplifier module is consistent with the input range of the main amplifier module.

In an embodiment of the present disclosure, the auxiliary ADC module may be a successive approximation ADC, a Flash ADC, a pipelined ADC, or the like, which has a smaller number of bits, i.e., relatively low accuracy.

In an embodiment of the present disclosure, the first switch may be a transmission gate switch, a metal-oxide-Semiconductor Field-Effect Transistor (MOSFET) switch, or the like.

In an embodiment of the present disclosure, the input signal end is connected to an external signal source and is used for inputting an analog signal to be converted, where the input signal end may be a single-ended input, a differential input or a pseudo-differential input, which is not limited by the embodiment of the present application.

It should be understood that, after the analog signal to be converted is conditioned by the auxiliary amplifier, the obtained first conditioned analog signal to be converted is matched with the input range of the auxiliary ADC module, so that the auxiliary ADC module is sufficiently driven to convert the signal. Similarly, the function of the main amplifier module is also the same, and the embodiments of the present application will not be repeated.

In an embodiment of the disclosure, when the main ADC module is in a sampling stage and the first switch is in an off state, the main ADC module is configured to perform an action according to information of the analog signal to be converted included in the first digital code, so as to generate a sampling precharge voltage; the difference between the sampling precharge voltage and the voltage of the output end of the main amplifier module is smaller than or equal to a preset error threshold value.

In this embodiment, in the sampling stage of the main ADC module, when the first switch is turned off, the auxiliary amplifier module 300 drives the auxiliary ADC to convert the signal on the analog signal input end thereof to obtain the first digital code, the first digital code includes the information of the analog signal to be converted, and the number of bits of the first digital code is the same as the number of bits of the auxiliary ADC, and the first digital code is sent to the main ADC module. In the above process, since the auxiliary amplifier module and the auxiliary ADC module have low accuracy and high speed, it takes a short time to perform rough conversion on the input analog signal to be converted, so as to obtain a conversion result.

And after the primary ADC module receives the first digital code, a circuit in the primary ADC module acts according to the first digital code and charges a sampling capacitor in the primary ADC module to generate a sampling precharge voltage. It should be noted that, the difference between the sampled precharge voltage and the voltage at the output end of the main amplifier module is within V _fs/2^m; wherein V _fs is the analog signal input range of the main ADC module, and m is the number of bits of the first digital code. I.e. the preset error threshold may be set to V _fs/2^m or less than V _fs/2^m.

It should be noted that, when the auxiliary amplifier module, the auxiliary ADC module and the first switch start charging the internal sampling capacitor of the main ADC, the first switch is in an off state, so that the function of isolating the main ADC module and the main amplifier module is performed, so that when the input voltage on the main ADC module changes in a large swing, the main amplifier module can be protected from the interference of the capacitor rapid charging process.

In an embodiment of the disclosure, when the first switch is switched from an open state to a closed state, the main ADC module is configured to charge according to the analog signal to be converted after the second conditioning based on the sampled precharge voltage, so that an input voltage of the main ADC module is the same as a voltage of an output terminal of the main amplifier module.

In this embodiment, when the first switch is switched from the open state to the closed state, the main amplifier module starts charging the sampling capacitor in the main ADC module, whereas the input voltage of the main ADC module has been previously established as the sampling precharge voltage, so that the input voltage of the main ADC module can be established to be the same as the voltage of the output terminal of the main amplifier module on the basis of the sampling precharge voltage. And finally, ending the sampling phase of the main ADC module.

In the above process, before the main amplifier module is directly connected with the main ADC module, since the input voltage of the main ADC module, that is, the sampled precharge voltage, is already very close to the voltage at the output end of the main ADC module, on one hand, when the input voltage of the main ADC module is built to a sufficient accuracy, a large voltage step will not be generated at the output end of the main ADC module, so as to avoid the disturbance of the internal circuit of the high-accuracy amplifier by the capacitor charging process, and on the other hand, even if the bandwidth of the main ADC module is small, it will not take a long time to build the final input voltage of the main ADC module to a sufficient accuracy.

In this embodiment, since the number of bits of the auxiliary ADC module is low, the power consumption and area overhead of itself are also small, and the load provided to the auxiliary amplifier module is also small, the auxiliary amplifier module can realize a high-speed design with small power consumption and area overhead.

In an embodiment of the present disclosure, if the conversion step of the auxiliary ADC module is started before the conversion of the main ADC module is completed, the auxiliary amplifier module and the auxiliary ADC module may not occupy the sampling time of the main ADC module, so that the speed requirement of the auxiliary amplifier module may be further reduced.

Fig. 2 shows a schematic diagram of yet another analog signal processing circuit for a high-precision ADC according to an embodiment of the disclosure. Wherein the main ADC module 200 includes: a sampling capacitor array 201, a sampling switch array 202 corresponding to the sampling capacitor array, a second switch 203, a comparator 204, and a control logic module 205.

Wherein, the upper polar plate of each sampling capacitor in the sampling capacitor array is connected together and connected to the first terminal of the second switch 203 and the inverting input terminal of the comparator 204, and the lower polar plate of each sampling capacitor is connected to the first terminal of the corresponding sampling switch;

The second terminal of each sampling switch in the array of sampling switches is connected together and to a first voltage input 111, the first voltage input 111 being connected to the second terminal L ₁₁ of the first switch;

The third terminal of each of the sampling switches is connected together and to the second voltage input 112; wherein the second voltage input terminal 112 is used for inputting a first reference voltage;

The fourth terminal of each of the sampling switches is connected together and to a third voltage input 113; the second voltage input end is used for inputting a grounding voltage;

a second terminal of the second switch 203 is connected to the fourth voltage input 114;

The positive input end of the comparator 204 is connected to the fifth voltage input end 115, and the output end is connected to the first input end L ₁₂ of the control logic module; wherein the fourth voltage input end and the fifth voltage input end are used for inputting a second reference voltage;

The output end L ₁₃ of the control logic module 205 is connected to the sampling switch array, and the second input end L ₁₄ is connected to the output end L ₅ of the auxiliary ADC module; the connection direction between the auxiliary ADC module and the control logic module is from the output end of the auxiliary ADC module to the second input end of the control logic module.

In an embodiment of the present disclosure, the number of sampling capacitors in the sampling capacitor array is the same as the number of sampling switches in the sampling switch array, i.e. each sampling capacitor corresponds to one sampling switch, and the number of sampling capacitors in the sampling capacitor array determines the number of bits of the main ADC module. In the above-described schematic diagram 2, the number of bits of the main ADC block is 8 bits, and the number of bits of the auxiliary ADC block is 4 bits, but the number of bits is not limited in the actual circuit.

In an embodiment of the present disclosure, the sampling capacitor array may be a binary capacitor array, a segmented capacitor array, a binary capacitor array with redundancy, or a non-binary capacitor array.

In one embodiment of the present disclosure, the connection direction between the control logic module and the sampling switch array is from the output end to the sampling switch array, so the control logic module is used to control the opening and closing actions of the sampling switches in the sampling switch array.

In an embodiment of the present disclosure, an output terminal of the control logic module may be connected to each sampling switch in the sampling switch array, and the connection state of the sampling switch is controlled according to the output of the output terminal of the control logic module. Of course, a controller may be disposed in the sampling switch array, and the controller may be connected to the control logic module, for controlling the connection state of the sampling switch according to the output of the output end of the control logic module. It should be noted that, the above is an exemplary description, and the connection between the output end of the control logic module and the sampling switch array may be specifically determined according to the actual situation, which is not limited by the embodiment of the present disclosure.

Taking fig. 2 as an example, the number of bits of the auxiliary ADC module is 4, and the number of bits of the main ADC module is 8. The sampling capacitor array as in fig. 2 comprises sampling capacitors 121, 122, 123, 124, 125, 126, 127, 128 and the sampling switch array comprises sampling switches 131, 132, 133, 134, 135, 136, 137, 138. The capacitor array formed by the sampling capacitors 121 to 128 is a binary capacitor array, that is, the capacitance of the higher-order capacitor is 2 times the capacitance of the adjacent lower-order capacitor. The sampling capacitor 121 is the highest capacitor, the capacitor size is 2 ^n-1C_u, the capacitors of the sampling capacitors 122 to 128 are 2^n-2C_u、2^n-3C_u、2ⁿ ^-4C_u、2^n-5C_u、2^n-6C_u、2^n-7C_u、2^n-8C_u; respectively, wherein n is the number of bits of the main ADC module, and C _u is the unit capacitor.

The upper polar plates of the sampling capacitors 121-128 are connected together and connected with the first wiring end of the second switch and the reverse input end of the comparator, and the lower polar plates of the sampling capacitors 121-128 are respectively connected with the first wiring ends of the corresponding sampling switches 131-138; the second terminals of the sampling switches 131 to 138 are connected together and to the first voltage input terminal 111, and the first voltage input terminal 111 is connected to the second terminal of the second switch; the third terminals of the sampling switches 131-138 are connected together and connected with the second voltage input end 112, and the first reference voltage input by the second voltage input end 112 is V _REF; the fourth terminals of the sampling switches 131 to 138 are connected together and to the third voltage input terminal 113, and the ground voltage input to the third voltage input terminal is GND. The second terminal of the second switch is connected to the fourth voltage input terminal 114, and the second reference voltage input by the fourth voltage input terminal 114 is V _CM; the positive input of the comparator block is connected to the fifth voltage input 115 and the output 116 is connected to the first input L ₁₂ of the control logic block 205; a second input L ₁₄ of the control logic block 205 is connected to the digital output of the auxiliary ADC block.

For the above-mentioned fig. 2, in the sampling stage of the main ADC, when the first switch is turned off, the auxiliary amplifier module drives the auxiliary ADC module to convert the first conditioned analog signal to be converted, so as to obtain a corresponding 4-bit digital code, i.e. the first digital code, and send the first digital code to the second input end of the control logic module.

In an embodiment of the disclosure, the control logic module is configured to control, when the first switch is in an open state and the second switch is in a closed state, a connection state of sampling switches in the sampling switch array according to the first digital code, so that logic states of M sampling capacitors in a high position in the sampling capacitor array are consistent with the first digital code, and then control a first terminal and a second terminal of each sampling switch to be connected, so that the sampling capacitor array generates a sampling precharge voltage; wherein, the value of M is the same as the digit of the first digital code, and M is a positive integer.

Still taking fig. 2 as an example, after the main ADC module receives the 4-bit first digital code, the second switch 204 is closed, and at this time, the upper electrode plates of the sampling capacitors 121 to 128 are connected to the voltage V _CM, and the connection states of the sampling switches 131 to 134 corresponding to the high-order sampling capacitors are controlled according to the first digital code.

Specifically, if the highest bit of the first digital code is 1, the sampling switch 131 connected to the highest bit sampling capacitor 121 is connected to the voltage input terminal 112, so that the voltage of the lower plate of the sampling capacitor 121 is switched to the first reference voltage V _REF; if the highest bit of the first digital code is 0, the sampling switch 131 connected to the highest bit sampling capacitor 121 is connected to the voltage input terminal 113, so that the lower plate voltage of the sampling capacitor 121 is switched to the ground voltage GND. Thus, bits 2 to 4 of the first digital code correspond to the states of the sampling capacitors 122 to 124 and the sampling switches 132 to 134, respectively, and can be operated as described above.

Fig. 3 shows a schematic diagram of a further analog signal processing circuit for a high-precision ADC, as shown in fig. 3, if the first digital code is 1010, the voltage of the lower plate of the sampling capacitor 121 may be switched to the first reference voltage V _REF, the sampling switch 132 connected to the sampling capacitor 122 is connected to the voltage input 113, and so on, until the logic state of the upper 4-bit sampling capacitor in the main ADC module is adjusted to be the same as the first digital code.

After the logic state of the upper 4-bit sampling capacitor in the main ADC block is the same as the first digital code, the sampling switches 131 to 138 are turned on with the first voltage input 111. Since the first switch is in an off state, the lower plates of the sampling capacitors 121 to 128 are shorted together to generate a sampling precharge voltage. At this time, the charge of the sampling capacitor is not changed, and the following formula is given according to the conservation of charge:

Wherein V _precharge represents a sampling precharge voltage, C _i is an i-th sampling capacitor in the main ADC module, and in this embodiment, the sampling capacitors 121 to 128 are n-th to (n-7) -th sampling capacitors (from high to low) of the main ADC respectively; d _i is a logic state of a sampling switch connected to the lower plate of the ith sampling capacitor, D _i =1 indicates that the sampling switch is connected to V _REF, D _i =0 indicates that the sampling switch is connected to GND, the upper 4 bits in D _i are conversion results of the auxiliary ADC module, and the remaining bits in D _i may be kept in a state of the last conversion result of the main ADC module, or may be any value, which is not limited in the embodiment of the present disclosure; c _total is the total capacitance of the sampling capacitor array in the main ADC, n is the number of sampling capacitors, and the value is 8. The total capacitance of the sampling capacitance array in the main ADC also satisfies the following relation:

Combining the above formula (1) and formula (2) yields the following formula:

According to the principle that the main ADC is a successive approximation ADC, the voltage V _charge at the output of the main amplifier module can be expressed by the following formula:

Wherein V _res is the difference between the voltage corresponding to the n-bit analog-to-digital conversion result of the SAR ADC and the input analog voltage, and V _res≤V_REF/2ⁿ exists.

Since the upper 4 bits of D _i are the conversion result of the auxiliary ADC block, i.e., correspond to the first digital code, there is D _n＝D'_n,D_n-1＝D'_n-1,D_n-2＝D'_n-2,D_n-3＝D'_n-3. Subtracting the formula (4) and the formula (3) to obtain the following formula:

In the embodiment of the present disclosure, C _i＝2^(n-i)C_u, substituted into the above formula (5), the following can be obtained:

|V_charge-V_precharge|≤V_REF·2^-4

In this way, after the lower plates of the sampling capacitors 121 to 128 are shorted, the difference between the sampling precharge voltage generated on the lower plates and the voltage of the output end of the main amplifier module is within V _REF/2⁴, that is, the sampling precharge voltage is relatively close to the voltage of the output end of the main amplifier module, so that even if the bandwidth of the main amplifier is small, a long time is not required to be taken to establish enough precision, meanwhile, because the voltage variation swing of the output end of the main amplifier is very small in the charging process, the output transistor of the amplifier can be kept at a relatively stable working point, and the problem that the internal circuit of the high-precision amplifier is disturbed by the capacitor charging process and additional time is required to be established to restore the precision is avoided.

In an embodiment of the disclosure, when the first switch is switched from an open state to a closed state, the sampling capacitor array is configured to charge according to the analog signal to be converted after the second conditioning based on the sampling precharge voltage, so that voltages of the lower plates of the M sampling capacitors are established to be the same as voltages of the output ends of the main amplifier module.

Fig. 4 is a schematic diagram of still another analog signal processing circuit for a high-precision ADC according to an embodiment of the disclosure, with reference to fig. 2 and 3. As shown in fig. 4, when the first switch 500 is closed, the second conditioned analog signal obtained by the main amplifier module 100 charges the sampling capacitors 121 to 128 in the main ADC module 200 to establish the voltage of the upper 4-bit capacitor lower plate to be the same as the voltage of the output terminal of the main amplifier module, even if the final input voltage of the main ADC module is established to an input voltage satisfying the requirement of sufficient accuracy.

In an embodiment of the disclosure, the sampling capacitor array is any one of the following: single-ended capacitive array, differential capacitive array.

Fig. 2 is an exemplary illustration of a sampling capacitor array as a single-ended capacitor array. Fig. 5 shows a schematic diagram of yet another analog signal processing circuit for a high-precision ADC provided by an embodiment of the disclosure. As shown in fig. 5, when the sampling capacitor array is a differential capacitor array, the precharged information is transmitted to the control logic module in the main ADC module through the output digital signal of the auxiliary ADC module, and the control logic module simultaneously controls the two capacitor arrays, that is, the precharging process is implemented by the original circuit structure in the main ADC, and the overhead of the signal processing circuit is not increased compared with the case of the single-ended capacitor array.

Compared with the prior art using the conventional precharge buffer method, when the sampling capacitor array is a differential capacitor array, two buffer modules are added between the main amplifier and the main ADC in the conventional precharge buffer method, but the precharge of the analog signal processing circuit provided by the embodiment of the application is realized by the original circuit structure in the main ADC, and only one group of auxiliary amplifier and auxiliary ADC are needed, i.e. no additional device is added, so that the analog signal processing circuit provided by the embodiment of the application has more remarkable power consumption and area advantages.

Fig. 6 shows a schematic diagram of another analog signal processing circuit for a high-precision ADC provided by an embodiment of the application. The analog signal processing circuit includes: an amplifier module 101, a third switch 102, a main ADC module 103, and an auxiliary ADC module 104.

The input terminal S ₁ of the amplifier module 101 is connected to the input signal terminal 105, the output terminal S ₂ is connected to the first terminal S ₃ of the third switch 102 and the analog input terminal S ₄ of the auxiliary ADC module, and the amplifier module 101 is configured to condition an analog signal to be converted input by the input signal terminal 105, and output the conditioned analog signal to be converted through the output terminal S ₂.

The digital output end S ₅ of the auxiliary ADC module 104 is connected to the digital input end S ₆ of the main ADC module, and the auxiliary ADC module is configured to convert the conditioned analog signal to be converted and output a converted second digital code through the digital output end S ₅.

The analog input terminal S ₇ of the main ADC module 103 is connected to the second terminal S ₈ of the third switch, and the main ADC module is configured to establish, according to the conditioned analog signal to be converted received through the analog input terminal S ₇ and the second digital code received through the digital input terminal S ₆, an input voltage of the main ADC module to an input voltage meeting a target accuracy requirement, so as to sample the analog signal under the input voltage;

In one embodiment of the present disclosure, the main ADC module is typically a charge-sharing successive approximation ADC, which has high precision, and the number of bits of the main amplifier module is typically 14-20 bits, but is not limited to 14-20 bits. The auxiliary ADC module can be a successive approximation type ADC, a Flash type ADC or a pipelined ADC, and the like, and has a small number of bits, namely relatively low precision, but the analog input range of the auxiliary ADC module is the same as the input range of the main ADC module.

In an embodiment of the present disclosure, the third switch may be a transmission gate switch, a metal-oxide-Semiconductor Field-Effect Transistor (MOSFET) switch, or the like.

In the circuit shown in fig. 6, the main amplifier is used for conditioning the analog signals to be converted, and the conditioned analog signals to be converted are matched with the input ranges of the main ADC module and the auxiliary ADC module, so that the main ADC module and the auxiliary ADC module can be driven sufficiently, that is, the main amplifier module is used as a driver of the auxiliary ADC module in the circuit, so that the area overhead is further saved.

In this embodiment, in the sampling stage of the main ADC module, when the third switch is turned off, the main amplifier module drives the auxiliary ADC to convert the signal on the analog signal input end thereof, so as to obtain a second digital code, where the second digital code includes information of the analog signal to be converted, and the number of bits of the second digital code is the same as that of the auxiliary ADC, and sends the second digital code to the main ADC module. In the above process, the auxiliary ADC module has low accuracy and high speed, so it takes a short time to perform coarse conversion on the input analog signal to be converted, so as to obtain a conversion result.

After the main ADC module receives the second digital code, the circuit inside the main ADC module acts according to the second digital code to generate sampling precharge voltage. It should be noted that, the difference between the sampled precharge voltage and the voltage at the output end of the main amplifier module is within V _fs/2^m; wherein V _fs is the analog signal input range of the main ADC module, and m is the number of bits of the second digital code. I.e. the preset error threshold may be set to V _fs/2^m or set to less than V _fs/2^m.

When the third switch is switched from the open state to the closed state, the main amplifier module starts charging the sampling capacitor in the main ADC module, and the input voltage of the main ADC module has been previously established as the sampling precharge voltage, so that the input voltage of the main ADC module can be established to be the same as the voltage of the output terminal of the main amplifier module on the basis of the sampling precharge voltage. And finally, ending the sampling phase of the main ADC module.

In the above process, before the main amplifier module is directly connected with the main ADC module, since the input voltage of the main ADC module, that is, the sampled precharge voltage, is already very close to the voltage at the output end of the main ADC module, on one hand, when the input voltage of the main ADC module is built to a sufficient accuracy, a larger voltage step will not be generated at the output end of the main ADC module, so as to avoid the disturbance of the internal circuit of the high-accuracy amplifier in the capacitive charging process, and on the other hand, even if the bandwidth of the main ADC module is smaller, it will not take a longer time to build the final input voltage of the main ADC module to a sufficient accuracy.

In an embodiment of the present disclosure, the internal circuit of the main ADC module 103 and the working principle of the internal circuit may refer to the main ADC module 200 shown in fig. 2 in the above embodiment, which is not described herein.

An analog signal processing circuit for a high-precision ADC provided according to an embodiment of the disclosure, the circuit including: a main amplifier module, a main ADC module, an auxiliary ADC module, and a third switch. The circuit structure forms two parallel signal links, can control the third switch to be disconnected and rapidly convert analog signals through the link of the main amplifier module and the auxiliary ADC module so as to obtain digital signals, and transmits the digital signals to the main ADC module, so that rapid precharge inside the main ADC module is realized to generate sampling precharge voltage, then the conduction of the third switch is controlled, and the input voltage of the main ADC module is accurately established on the basis of precharge. Therefore, through the circuit, when the input voltage of the main ADC module is changed in a large swing, the main amplifier module is protected from being interfered by quick charge, and compared with an amplifier serving as a precharge buffer in a traditional circuit, the circuit provided by the embodiment of the disclosure has the advantages of larger slew rate and bandwidth, low number of auxiliary ADC bits, low power consumption and area cost, and thus the power consumption and area cost of the circuit are saved.

In addition, compared with the related art, the analog signal processing circuit provided by the embodiment of the present disclosure may further include the following advantages:

(1) In the related art, a precharge buffer is adopted to generate large current in the process of rapidly charging the ADC, other analog signal lines are easy to interfere on layout wiring, the layout design difficulty of connecting lines between the precharge buffer and the ADC is increased, and the precharge information of the analog signals is transmitted from an auxiliary ADC module to a main ADC module through a digital domain, so that the complexity of the key analog signal wiring in the layout is not increased.

(2) The analog signal processing circuit provided by the embodiment of the disclosure reduces the number of switches in an analog signal link, thereby improving the influence of switch leakage current on ADC sampling precision under high temperature conditions.

Fig. 7 shows a flowchart of an analog signal processing method for a high-precision ADC according to an embodiment of the disclosure, which is applied to the circuit shown in any one of fig. 1 to 5 described above, and includes the following steps S301 to S303:

in step S301, when a main ADC module in the circuit is in a sampling stage, acquiring an analog signal to be converted;

In step S302, the analog signal to be converted is conditioned by a main amplifier module and an auxiliary amplifier module in the circuit, the analog signal to be converted conditioned by the auxiliary amplifier module is converted by an auxiliary ADC module in the circuit, a conversion result is obtained, and the conversion result is sent to the main ADC module;

In step S303, according to the analog signal to be converted conditioned by the main amplifier module and the conversion result, the input voltage of the main ADC module is established to an input voltage meeting the target precision requirement, so as to sample the analog signal under the input voltage.

In an embodiment of the present disclosure, reference may be made to the detailed description of the foregoing embodiments for the description of the circuit structure, which is not repeated herein.

In an embodiment of the present disclosure, the conversion result may be understood as a first digital code.

In an embodiment of the present disclosure, the establishing the input voltage of the main ADC module to an input voltage meeting the target precision requirement according to the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to sample the analog signal under the input voltage includes:

Switching the first switch to a closed state;

In this embodiment, in the sampling stage of the main ADC module, when the first switch between the main ADC module and the amplifier module is turned off, the auxiliary amplifier module drives the auxiliary ADC to convert the signal on the analog signal input end thereof, so as to obtain a conversion result, where the conversion result includes information of the analog signal to be converted, and the number of bits of the conversion result is the same as that of the auxiliary ADC, and sends the conversion result to the main ADC module. In the above process, the auxiliary ADC module has low accuracy and high speed, so it takes a short time to perform coarse conversion on the input analog signal to be converted, so as to obtain a conversion result.

And after the main ADC module receives the conversion result, a circuit inside the main ADC module acts according to the conversion result and shorts the lower polar plates of all sampling capacitors in the main ADC module to generate sampling precharge voltage. It should be noted that, the difference between the sampled precharge voltage and the voltage at the output end of the main amplifier module is within V _fs/2^m; wherein V _fs is the analog signal input range of the main ADC module, and m is the number of bits of the second digital code. I.e. the preset error threshold may be set to V _fs/2^m or less than V _fs/2^m.

When the first switch between the main ADC block and the amplifier block is switched from an open state to a closed state, the main amplifier block starts charging the sampling capacitor in the main ADC block, whereas the input voltage of the main ADC block has been previously established as the sampling precharge voltage, so that the input voltage of the main ADC block can be established to be the same as the voltage of the output terminal of the main amplifier block on the basis of the sampling precharge voltage. And finally, ending the sampling phase of the main ADC module.

In the above process, before the main amplifier module is directly connected with the main ADC module, since the input voltage of the main ADC module, that is, the sampled precharge voltage, is already very close to the voltage at the output end of the main ADC module, on one hand, when the input voltage of the main ADC module is built to a sufficient accuracy, a larger voltage step will not be generated at the output end of the main amplifier module, so as to avoid the disturbance of the internal circuit of the high-accuracy amplifier in the capacitive charging process, and on the other hand, even if the bandwidth of the main amplifier module is smaller, it will not take a longer time to build the final input voltage of the main ADC module to an input voltage meeting the requirement of sufficient accuracy.

According to the analog signal processing method for the high-precision ADC, provided by the embodiment of the disclosure, the analog signal is rapidly converted through the link of the amplifier module and the auxiliary ADC module by switching off the control switch so as to obtain a digital signal, the digital signal is transmitted to the main ADC module, rapid precharge inside the main ADC module is realized to generate sampling precharge voltage, the conduction of the control switch is controlled, and the input voltage of the main ADC module is accurately established on the basis of precharge. Therefore, when the input voltage of the main ADC module is changed in a large swing, the main amplifier module is protected from being interfered by quick charge, the bandwidth requirement on the amplifier is lower because the sampling precharge voltage is very close to the voltage of the output end of the main amplifier, and the power consumption and the area cost of the auxiliary ADC are small because the number of bits of the auxiliary ADC is low, the load provided for the auxiliary amplifier is also small, and the auxiliary amplifier can realize high-speed design under the condition of small working current, so that the power consumption and the area cost of a circuit are saved.

Fig. 8 shows a flowchart of another analog signal processing method for a high-precision ADC provided by an embodiment of the disclosure, which is applied to the circuit shown in fig. 6 as described above, the method including the following steps S401 to S403:

in step S401, when a main ADC module in the circuit is in a sampling stage, an analog signal to be converted is obtained;

in step S402, the analog signal to be converted is conditioned by a main amplifier module in the circuit, the conditioned analog signal to be converted is converted by an auxiliary ADC module in the circuit, a conversion result is obtained, and the conversion result is sent to the main ADC module;

in step S403, according to the conditioned analog signal to be converted and the conversion result, the input voltage of the main ADC module is established to an input voltage meeting the target precision requirement, so as to sample the analog signal under the input voltage.

In an embodiment of the present disclosure, the conversion result may be understood as a second digital code.

In an embodiment of the present disclosure, the establishing the input voltage of the main ADC module to an input voltage meeting the target precision requirement according to the conditioned analog signal to be converted and the conversion result, so as to sample the analog signal under the input voltage, includes:

When a third switch between the main ADC module and the main amplifier module is in an off state, according to the conversion result, the logic states of a plurality of sampling capacitors at high positions in the main ADC module are adjusted to be consistent with the conversion result, and the lower polar plates of all the sampling capacitors in the main ADC module are short-circuited to generate sampling precharge voltage; the difference value between the sampling precharge voltage and the voltage of the output end of the main amplifier module is smaller than or equal to a preset error threshold value, and the number of the sampling capacitors is the same as the number of bits of the conversion result;

switching the third switch to a closed state;

and charging a sampling capacitor in the main ADC module according to the conditioned analog signal to be converted, so that the input voltage of the main ADC module is established to be the same as the voltage of the output end of the main amplifier module from the sampling precharge voltage.

In this embodiment, in the sampling stage of the main ADC module, when the third switch between the main ADC module and the amplifier module is turned off, the main amplifier module drives the auxiliary ADC to convert the signal on the analog signal input end thereof, so as to obtain a conversion result, where the conversion result includes information of the analog signal to be converted, and the number of bits of the conversion result is the same as that of the auxiliary ADC, and sends the conversion result to the main ADC module. In the above process, the auxiliary ADC module has low accuracy and high speed, so it takes a short time to perform coarse conversion on the input analog signal to be converted, so as to obtain a conversion result.

And after the main ADC module receives the conversion result, a circuit inside the main ADC module acts according to the conversion result and shorts the lower polar plates of all sampling capacitors in the main ADC module to generate sampling precharge voltage. It should be noted that, the difference between the sampled precharge voltage and the voltage at the output end of the main amplifier module is within V _fs/2^m; wherein V _fs is the analog signal input range of the main ADC module, and m is the number of bits of the second digital code. I.e. the preset error threshold may be set to V _fs/2^m or set to less than V _fs/2^m.

When the third switch between the main ADC block and the amplifier block is switched from the open state to the closed state, the main amplifier block starts charging the sampling capacitor in the main ADC block, whereas the input voltage of the main ADC block has been previously established as the sampling precharge voltage, so that the input voltage of the main ADC block can be established to be the same as the voltage of the output terminal of the main amplifier block on the basis of the sampling precharge voltage. And finally, ending the sampling phase of the main ADC module.

In the above process, before the main amplifier module is directly connected with the main ADC module, since the input voltage of the main ADC module, that is, the sampled precharge voltage, is already very close to the voltage at the output end of the main ADC module, on one hand, when the input voltage of the main ADC module is built to a sufficient accuracy, a larger voltage step will not be generated at the output end of the main amplifier module, so as to avoid the disturbance of the internal circuit of the high-accuracy amplifier in the capacitive charging process, and on the other hand, even if the bandwidth of the main amplifier module is smaller, it will not take a longer time to build the final input voltage of the main ADC module to a voltage meeting the requirement of sufficient accuracy.

According to the analog signal processing method for the high-precision ADC, provided by the embodiment of the disclosure, the analog signal is rapidly converted through the link of the main amplifier module and the auxiliary ADC module by switching off the control switch so as to obtain a digital signal, the digital signal is transmitted to the main ADC module, rapid precharge inside the main ADC module is realized to generate sampling precharge voltage, the conduction of the control switch is controlled, and the input voltage of the main ADC module is accurately established on the basis of precharge. Therefore, when the input voltage of the main ADC module is changed in a large swing, the main amplifier module is protected from being interfered by quick charging, the bandwidth requirement on the amplifier is low because the sampling precharge voltage is very close to the voltage of the output end of the main amplifier, the number of bits of the auxiliary ADC is low, and the power consumption and the area cost of the auxiliary ADC module are small, so that the power consumption and the area cost of a circuit are saved.

Embodiments of the present disclosure provide a chip including an analog signal processing circuit for a high-precision ADC shown in any of fig. 1 to 6 in the above embodiments.

The disclosed embodiments provide an electronic device including a chip including an analog signal processing circuit for a high-precision ADC as described in the above embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by those skilled in the art that the scope of the invention referred to in this disclosure is not limited to the specific combination of features described above, but encompasses other embodiments in which any combination of features described above or their equivalents is contemplated without departing from the inventive concepts described. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).

Claims

1. An analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a main ADC module, an auxiliary amplifier module, and an auxiliary ADC module, and a first switch;

2. The circuit of claim 1, wherein when the main ADC module is in a sampling phase and the first switch is in an off state, the main ADC module is configured to act according to information of the analog signal to be converted contained in the first digital code, so as to generate a sampling precharge voltage; the difference between the sampling precharge voltage and the voltage of the output end of the main amplifier module is smaller than or equal to a preset error threshold value.

3. The circuit of claim 2, wherein when the first switch is switched from an open state to a closed state, the main ADC module is configured to charge according to a second conditioned analog signal to be converted based on the sampled precharge voltage, so that an input voltage of the main ADC module is the same as a voltage of an output terminal of the main amplifier module.

4. The circuit of claim 1 or 2, wherein the main ADC module comprises: the sampling device comprises a sampling capacitor array, a sampling switch array corresponding to the sampling capacitor array, a second switch, a comparator and a control logic module;

5. The circuit of claim 4, wherein the control logic module is configured to control, when the first switch is in an open state and the second switch is in a closed state, a connection state of sampling switches in the sampling switch array according to the first digital code so that logic states of M sampling capacitors in a high order in the sampling capacitor array are consistent with the first digital code, and then control a first terminal and a second terminal of each sampling switch to be connected so that the sampling capacitor array generates a sampling precharge voltage; wherein, the value of M is the same as the digit of the first digital code, and M is a positive integer.

6. The circuit of claim 5, wherein when the first switch is switched from an open state to a closed state, the sampling capacitor array is configured to charge according to a second conditioned analog signal to be converted based on the sampling precharge voltage, so that voltages of lower plates of the M sampling capacitors are established to be the same as voltages of the output terminals of the main amplifier module.

7. The circuit of claim 4, wherein the array of sampling capacitors is any one of: single-ended capacitive array, differential capacitive array.

8. An analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a third switch, a main ADC module, and an auxiliary ADC module;

9. An analog signal processing method for a high-precision ADC, applied to the circuit according to any one of claims 1 to 7, the method comprising:

10. The method according to claim 9, wherein the establishing the input voltage of the main ADC module to an input voltage meeting a target precision requirement according to the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to sample the analog signal under the input voltage, includes:

Switching the first switch to a closed state;

11. A method of analog signal processing for a high-precision ADC, applied to the circuit of claim 8, the method comprising:

12. A chip comprising an analog signal processing circuit according to any one of claims 1 to 8.

13. An electronic device comprising the chip of claim 12.