CN117895933B - Radio frequency switch circuit, chip and electronic equipment thereof - Google Patents
Radio frequency switch circuit, chip and electronic equipment thereof Download PDFInfo
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- H—ELECTRICITY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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Abstract
The invention provides a radio frequency switch circuit, a chip and electronic equipment thereof, wherein the radio frequency switch circuit is formed by serially connecting n stages of switch transistor units, the n stages of switch transistor units are divided into L switch transistor unit groups along the radio frequency current direction, 1<L is less than or equal to n, each stage of switch transistor unit comprises a switch transistor, a grid bias resistor, a body bias resistor and a path resistor, and the interval between adjacent transverse grids of the switch transistor in each switch transistor unit group is smaller than the interval between adjacent transverse grids of the switch transistor in the later switch transistor unit group. The radio frequency switch circuit design can ensure that different switch transistors have more balanced voltage distribution, and further can improve the power processing capacity of the radio frequency switch circuit.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a radio frequency switch circuit, a chip and an electronic device thereof.
Background
In wireless or mobile communication systems, radio frequency switching circuits are often used for channel selection, and in the case of a common antenna, wireless signal reception and transmission can be achieved. With the rapid development of 5G mobile networks, particularly with the deployment of Multiple-Input Multiple-Output (MIMO) systems, radio frequency devices in communication systems become more complex. The trend of systems with multiple standards integrated into one device has further increased the performance requirements and demands on radio frequency switches. Meanwhile, with the increasing number of frequency bands, functions and modes required for operation of devices such as mobile phones, the space reserved for antennas in mobile systems is continuously reduced, so that the efficiency of the antennas is further deteriorated, and the signal transmission quality of the communication devices is affected. Therefore, in order to meet the sensitivity requirement of the receiver in a complex environment and ensure better 5G communication signal quality, a radio frequency switch circuit with higher power processing capability must be designed.
The power handling capability of a radio frequency switching circuit is closely related to the capacitance at which it is turned off. If the parasitic capacitance of different switch transistors in the radio frequency switch circuit is improperly designed, uneven voltage distribution among the different switch transistors can be caused, and the overall power processing capability of the radio frequency switch circuit can be further deteriorated.
Therefore, it is necessary to optimize the parasitic capacitances of the different switching transistors in the rf switching circuit to ensure that the rf switching circuit has a higher power handling capability.
Disclosure of Invention
The invention aims to provide a radio frequency switch circuit, a chip and electronic equipment thereof, so as to improve the power processing capacity of the radio frequency switch circuit.
To achieve the above and other related objects, the present invention provides a radio frequency switching circuit, which is composed of n stages of switching transistor units connected in series, the n stages of switching transistor units being divided into L switching transistor unit groups along a radio frequency current direction, 1<L being equal to or less than n, each of the switching transistor units including a switching transistor, a gate bias resistor, a body bias resistor, and a path resistor, wherein,
The grid electrode of each switching transistor is respectively connected with the corresponding grid electrode bias resistor, the drain electrode and the source electrode are respectively connected with the corresponding path resistor, and the body electrode is respectively connected with the corresponding body electrode bias resistor; the grid bias resistors in each stage of the switching transistor units are sequentially connected in series, and then the tail ends of the grid bias resistors are connected with grid bias voltage; the body electrode bias resistors in each stage of the switching transistor units are sequentially connected in series, and then the tail ends of the body electrode bias resistors are connected with body electrode bias voltages;
the grid electrode of each switching transistor comprises a plurality of parallel transverse grids, and the distance between the adjacent transverse grids of the switching transistors in each switching transistor unit group is smaller than the distance between the adjacent transverse grids of the switching transistors in the next switching transistor unit group.
Optionally, in the radio frequency switch circuit, a layout structure of each switch transistor is an interdigital structure.
Optionally, in the radio frequency switching circuit, a distance between a lateral gate of the switching transistor in each switching transistor unit group and a metal contact point of an adjacent source or drain is smaller than a distance between a lateral gate of the switching transistor in a subsequent switching transistor unit group and a metal contact point of an adjacent source or drain.
Optionally, in the radio frequency switching circuit, a voltage difference introduced by a difference between a pitch between adjacent lateral gates of the switching transistors in each of the switching transistor unit groups and a pitch between adjacent lateral gates of the switching transistors in a subsequent one of the switching transistor unit groups balances a voltage difference of the switching transistors in the two switching transistor unit groups due to non-ideal factors, wherein the non-ideal factors include parasitic capacitance between gates of the switching transistors and sources, parasitic capacitance between gates of the switching transistors and drains of the switching transistors, parasitic capacitance between bodies and sources of the switching transistors, and parasitic capacitance of sources and drains of the switching transistors to ground.
Optionally, in the radio frequency switching circuit, a source electrode of the switching transistor of each stage is connected to a drain electrode of the switching transistor in the switching transistor unit of the subsequent stage, an output end of the switching transistor unit of each stage is a source electrode of the switching transistor in the switching transistor unit of the stage, and an input end of the switching transistor unit of each stage is a drain electrode of the switching transistor in the switching transistor unit of the stage.
Optionally, in the radio frequency switching circuit, the lengths of the lateral gates of all the switching transistors in the same switching transistor unit group are the same.
Optionally, in the radio frequency switching circuit, all the switching transistors in the same switching transistor unit group have the same size.
Optionally, in the radio frequency switching circuit, the intervals between adjacent lateral gates of all switching transistors in the same switching transistor unit group are the same.
To achieve the above and other related objects, the present invention also provides an integrated circuit chip, including the radio frequency switch circuit described above.
To achieve the above object and other related objects, the present invention also provides an electronic device, including the radio frequency switch circuit described above.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
In the radio frequency switch circuit provided by the invention, n-level switch transistor units are divided into L switch transistor unit groups along the radio frequency current direction, the distance between adjacent transverse gates of switch transistors in each switch transistor unit group is smaller than the distance between adjacent transverse gates of switch transistors in the next switch transistor unit group, so that the parasitic capacitance C ds relationship of the switch transistors in different switch transistor unit groups can be expressed as: c dsG1>CdsG2>CdsG3>…> CdsGL, and further can obtain that the voltage division relationship of the switch transistors in the different switch transistor unit groups under ideal conditions is as follows: v dsG1<VdsG2<VdsG3<…< VdsGL. The voltage division relation formed by the design can just balance the problem of uneven voltage distribution among different switching transistors caused by non-ideal factors, and further the radio frequency switching circuit with high power processing capacity can be obtained.
Drawings
FIG. 1 is a schematic circuit diagram of a radio frequency switching circuit;
FIG. 2 is a schematic circuit diagram of the RF switch circuit of FIG. 1 including parasitic parameters;
FIG. 3 is a layout corresponding to a switching transistor of the radio frequency switching circuit of FIG. 1;
FIG. 4 is a schematic circuit diagram of a RF switch circuit according to an embodiment of the present invention;
Fig. 5 is a layout corresponding to a switching transistor of the radio frequency switching circuit of fig. 4;
FIG. 6 is a graph showing the drain-source voltage of a switching transistor according to an embodiment of the present invention compared with the drain-source voltage of a switching transistor according to the prior art;
In the figures 1-3 of the drawings,
011-Horizontal gate 012-active region, 0121-metal contact, 013-vertical gate;
In FIG. 4 to FIG. 6
11-Horizontal gate, 12-active region, 121-metal contact, 13-vertical gate.
Detailed Description
The radio frequency switch circuit, the chip and the electronic equipment thereof provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the prior art, a method for improving the power processing capability of a radio frequency switching circuit is generally a switching transistor stacking method. In the method, a radio frequency switching circuit is formed by connecting a plurality of switching transistors in series. As shown in fig. 1, the rf switch circuit is formed by connecting switch transistors M 1、M2 … … and M n (n is a positive integer and n > 1) in series, wherein the drain of switch transistor M 1 is connected to the signal input terminal of the rf switch circuit, and the source of switch transistor M n is connected to the signal output terminal of the rf switch circuit. The gate bias voltage V g is connected to the gates of the switching transistors through the gate bias resistors R g, and the body bias voltage V b is connected to the body of the switching transistors through the body bias resistors R b. A path resistor R ds is connected in parallel between the drain and the source of each switching transistor. Fig. 2 shows a prior art rf switching circuit structure including parasitic parameters, where V g and V b are the gate and body bias voltages of the switching transistors, respectively, and V in is the input signal to the rf switching circuit. C gs is the parasitic capacitance between the gate and source of the switching transistor; c gd is the parasitic capacitance between the gate and drain of the switching transistor; c bs is the parasitic capacitance between the body and source of the switching transistor; c bd is the parasitic capacitance between the body and drain of the switching transistor; c n is the parasitic capacitance of the source and drain of the nth switching transistor to ground; i ds is the source drain current of the switching transistor; c ds is the parasitic capacitance between the source and drain of the switching transistor (i.e., the source drain parasitic capacitance). The actual rf switch circuit is not designed with any parasitic capacitance, which is shown in fig. 2 only to make the rf switch circuit easier to understand.
The voltage division of the switching transistor is mainly dependent on the voltage division of its source-drain parasitic capacitance C ds (i.e., the source-drain voltage). For the n series-connected switching transistors shown in fig. 2, the source-drain voltage of the 1 st switching transistor (i.e., switching transistor M 1) can be simply expressed as equation one:
wherein V in is an input signal of the rf switching circuit, Z ds1 is a source-drain capacitance impedance of the 1 st switching transistor, Z dsn is a source-drain capacitance impedance of the n-th switching transistor, C ds1 is a source-drain parasitic capacitance of the 1 st switching transistor, C dsn is a source-drain parasitic capacitance of the n-th switching transistor, ω=2pi f is an operating frequency of the rf switching circuit.
The source drain parasitic capacitance of the switching transistor is related to its size, so that for designs in which the n switching transistors are exactly the same size, the voltage division between the different switching transistors should ideally be uniform. However, in practical situations, when the rf switch circuit is in the off condition and V in is input, due to the parasitic capacitances C gs、Cgd、Cbs、Cbd and C n in fig. 2, leakage currents other than i ds are generated, so that the source-drain currents of the different switch transistors decrease along the current direction, and the voltage division between n switch transistors connected in series decreases along the i ds direction, that is, V ds1>Vds2>…> Vdsn.
Fig. 3 is a layout of a conventional rf switch circuit corresponding to fig. 1. Where D n is the spacing between adjacent lateral gates 011 (finger gates) in the nth switching transistor, D n is the distance from the lateral gate 011 to the metal contact 0121 of the adjacent active region 012 (source or drain) in the nth switching transistor, and W n is the length of the (single) lateral gate 011 in the nth switching transistor. The gate of each switching transistor in the existing radio frequency switching circuit may include two vertical gates 013, and a plurality of horizontal gates 011 are disposed in parallel between the two vertical gates 013. The layout designs of different switching transistors in the existing radio frequency switching circuit are the same, namely:
D1=D2=…=Dn (1)
d1= d2=…=dn (2)
W1=W2=…=Wn (3)
The layout design can cause the phenomenon that the voltage distribution among different switching transistors is uneven (namely V ds1>Vds2>…>Vdsn) during high-power input, namely the problem that the voltage distribution among different switching transistors is uneven due to non-ideal factors (parasitic capacitances C gs、Cgd、Cbs、Cbd and C n).
In order to improve the above problems, the present invention provides a radio frequency switch circuit, and refer to fig. 4. The radio frequency switching circuit in fig. 4 is composed of n-stage switching transistor units connected in series, wherein the n-stage switching transistor units are divided into L switching transistor unit groups along the radio frequency current direction, and 1<L is less than or equal to n. Each of the switch transistor unit groups in this embodiment includes at least one switch transistor unit, that is, each of the switch transistor unit groups may include one switch transistor unit or may include a plurality of switch transistor units.
In this embodiment, the number of switching transistor units included in each of the switching transistor unit groups may be the same or different. For example, in fig. 4, the switching transistor cell group G 1 includes a switching transistor cell U 1, the switching transistor cell group G 2 includes a switching transistor cell U 2, the switching transistor cell group G 3 includes a switching transistor cell U 3 and the switching transistor cell U 4 …, and the switching transistor cell group G L includes a switching transistor cell U （n-1） and a switching transistor cell U n.
The switching transistor cells of each stage may include a switching transistor, a gate bias resistor, a body bias resistor, and a path resistor. The switching transistor in this embodiment is preferably an NMOS transistor, but may be a PMOS transistor.
The grid electrode of each switching transistor is respectively connected with the corresponding grid electrode bias resistor R g, and after the grid electrode bias resistors in each level of switching transistor units are sequentially connected in series, the tail end of each level of switching transistor unit is connected with the grid electrode bias voltage V g. For example, in fig. 4, the gate of the switching transistor M 1 is connected to the gate bias resistor R g1, the gate of the switching transistor M 2 is connected to the gate bias resistor R g2, and so on, the gate of the switching transistor M n is connected to the gate bias resistor R gn, and after the gates of the switching transistors R g1、Rg2…Rgn are serially connected to each other, the terminal is connected to the gate bias voltage V g.
The source of each of the switching transistors is connected to the drain of a switching transistor in a switching transistor unit of a subsequent stage, and the path resistance R ds is provided between the drain and the source of each of the switching transistors. For example, the drain of the switching transistor M 1 in fig. 4 is used as an input terminal, the source of the switching transistor M 1 is connected to the drain of the switching transistor M 2, and the path resistor R ds1 is disposed between the drain and the source of the switching transistor M 1; the source of the switching transistor M 2 is connected to the drain of the switching transistor M 3, and the path resistor R ds2 is disposed between the drain and the source of the switching transistor M 2, and so on, the source of the switching transistor M n-1 is connected to the drain of the switching transistor M n, and the path resistor R dsn-1 is disposed between the drain and the source of the switching transistor M n-1; the source of the switching transistor M n serves as an output terminal, and the path resistor R dsn is provided between the drain and the source of the switching transistor M n. In this embodiment, the output terminal of the switching transistor unit of each stage is the source of the switching transistor in the switching transistor unit of that stage, and the input terminal of the switching transistor unit of each stage is the drain of the switching transistor in the switching transistor unit of that stage.
The body pole of each switching transistor is respectively connected with the corresponding body pole bias resistor R b, and after the body pole bias resistors R b in each level of switching transistor units are sequentially connected in series, the tail end of each level of switching transistor unit is connected with the body pole bias voltage V b. For example, in fig. 4, the body of the switching transistor M 1 is connected to the body bias resistor R b1, the body of the switching transistor M 2 is connected to the body bias resistor R b2, and so on, the body of the switching transistor M n is connected to the body bias resistor R bn, and the ends of the switching transistor M b1、Rb2…Rbn are connected to the gate bias voltage V b after being serially connected to each other.
In this embodiment, the layout structure of the switching transistors is preferably an interdigital structure, and the gate of each switching transistor may include a plurality of parallel horizontal gates and may further include at least one vertical gate. For example, in fig. 5, the gate of each switching transistor may include two vertical gates 13, and a plurality of horizontal gates 11 are disposed in parallel between the two vertical gates 13, and an area between two adjacent horizontal gates 11 is an active area 12, and two longitudinally adjacent active areas 12 are a source area and a drain area, respectively.
In the present embodiment, the pitch between the adjacent lateral gates 11 of the switching transistors in each of the switching transistor cell groups is smaller than the pitch between the adjacent lateral gates 11 of the switching transistors in the following one of the switching transistor cell groups. The adjacent lateral gates 11 refer to longitudinally adjacent lateral gates 11 in the same switching transistor, and the same switching transistor has a plurality of lateral gates 11, that is, there are spaces between the plurality of adjacent lateral gates 11, and the spaces between all the adjacent lateral gates 11 in the same switching transistor in this embodiment are preferably the same, and further, the spaces between the adjacent lateral gates 11 of all the switching transistors in the same switching transistor unit group are preferably the same. The spacing between adjacent lateral gates 11 of the switching transistors in the switching transistor unit group G 1 in this embodiment is D G1 (i.e., the spacing between all adjacent lateral gates 11 in the switching transistor unit group G 1 is D G1), the spacing between adjacent lateral gates 11 of the switching transistors in the switching transistor unit group G 2 is D G2, and so on, the spacing between adjacent lateral gates 11 of the switching transistors in the switching transistor unit group G L is D GL, and this embodiment is preferably D G1<DG2<…<DGL. For example, table 1 is an example parameter of a switching transistor of the present invention.
Table 1:
The switching transistor cell group G 1 in table 1 includes the switching transistor M 1, and the D G1 value of the switching transistor cell group G 1 is 0.07 μm; the switching transistor cell group G 2 includes a switching transistor M 2, and the D G2 value of the switching transistor cell group G 2 is 0.075 μm; the switching transistor unit group G 3 includes a switching transistor M 3 and a switching transistor M 4, and the D G3 value of the switching transistor unit group G 3 is 0.085 μm, that is, the intervals between adjacent lateral gates of the switching transistor M 3 and the switching transistor M 4 are all 0.085 μm; the switching transistor cell group G 4 includes a switching transistor M 5 and a switching transistor M 6, and the D G4 value of the switching transistor cell group G 4 is 0.1 μm; the switching transistor cell group G 5 includes a switching transistor M 7 and a switching transistor M 8, and the D G5 value of the switching transistor cell group G 5 is 0.11 μm; the switching transistor cell group G 6 includes a switching transistor M 9 and a switching transistor M 10, and the D G6 value of the switching transistor cell group G 6 is 0.12 μm; the switching transistor cell group G 7 includes a switching transistor M 11 and a switching transistor M 12, and the D G7 value of the switching transistor cell group G 7 is 0.13 μm; the switching transistor cell group G 8 includes a switching transistor M 13 and a switching transistor M 14, and the D G8 value of the switching transistor cell group G 8 is 0.14 μm; the switching transistor cell group G 9 includes a switching transistor M 15 and a switching transistor M 16, and the D G9 value of the switching transistor cell group G 9 is 0.15 μm. Fig. 6 is a graph comparing the source-drain voltages of the switching transistors corresponding to the example parameters of the switching transistors in table 1 with the source-drain voltages of the switching transistors in the prior art, and it can be found that the source-drain voltages of the switching transistors in the prior art (the interval between the adjacent lateral gates of each switching transistor is designed to be 0.11 μm) are gradually reduced, whereas the source-drain voltages of the switching transistors in the present invention are relatively stable, i.e., the radio frequency switching circuit of the present invention can solve the problem of non-uniform voltage distribution between different switching transistors caused by non-ideal factors, and can improve the power processing capability.
In the present embodiment, the length of the single lateral gate 11 of the switching transistor in the switching transistor cell group G 1 is W G1, the length of the single lateral gate 11 of the switching transistor in the switching transistor cell group G 2 is W G2, and so on, the length of the single lateral gate 11 of the switching transistor in the switching transistor cell group G L is W GL. The lengths of the individual lateral gates 11 of all the switching transistors in the same switching transistor cell group are preferably the same, the total length of the lateral gates 11 of each switching transistor in the same switching transistor cell group is preferably the same (lateral gate total length W Total (S) = length of individual lateral gates 11 times the number of lateral gates 11 of individual transistors), and the total lengths of the lateral gates 11 of the switching transistors (individual) in different switching transistor cell groups are also preferably the same.
Because of D G1<DG2<…<DGL of the present embodiment, the distance D from the switching transistor lateral gate 11 of the different switching transistor cell group to the metal contact 121 of the adjacent source or drain satisfies the following relationship: d G1<dG2<…<dGL. Wherein the distance from the lateral gate 11 of the switching transistor in the switching transistor unit group G 1 to the metal contact 121 of the adjacent source or drain is d G1, the distance from the lateral gate 11 of the switching transistor in the switching transistor unit group G 2 to the metal contact 121 of the adjacent source or drain is d G2, and so on, the distance from the lateral gate 11 of the switching transistor in the switching transistor unit group G L to the metal contact 121 of the adjacent source or drain is d GL. In the present embodiment, the distances from all the lateral gates 11 to the metal contact 121 of the adjacent source or drain in the same switching transistor cell group are preferably the same, and the sizes of all the switching transistors in the same switching transistor cell group are preferably the same.
In this embodiment, the size of D determines the size of the parasitic capacitance of the switching transistor, and the smaller D is, the larger the parasitic capacitance of the switching transistor is, and the larger the parasitic capacitance of the switching transistor cell group is. For a D design of L switch transistor cell groups, the parasitic capacitance C ds relationship between the switch transistors in the L switch transistor cell groups can be expressed as: c dsG1>CdsG2>…>CdsGL, wherein C dsG1 is the parasitic capacitance of the individual switching transistors in the switching transistor cell group G 1, C dsG2 is the parasitic capacitance of the individual switching transistors in the switching transistor cell group G 2, and C dsGL is the parasitic capacitance of the individual switching transistors in the switching transistor cell group G L. As can be derived from the formula one, the voltage division relationship between the switching transistors in the L switching transistor cell groups is ideally: v dsG1<VdsG2<VdsG3<…<VdsGL, where V dsG1 is the source-drain voltage of a single switching transistor in the switching transistor cell group G 1, V dsG2 is the source-drain voltage of a single switching transistor in the switching transistor cell group G 2, and V dsGL is the source-drain voltage of a single switching transistor in the switching transistor cell group G L. Therefore, the voltage division relation formed by the design can just balance the problem of uneven voltage distribution among different switching transistors caused by non-ideal factors, namely, in the practical situation, the voltages among the different switching transistors are basically equal, the distribution is uniform, and then the radio frequency switching circuit with high power processing capability can be obtained.
In this embodiment, after determining the switching transistor units in each switching transistor unit group, the source-drain parasitic capacitance of the switching transistors in each switching transistor unit group is adjusted to balance the problem of non-uniform voltage distribution among different switching transistors caused by non-ideal factors, and the circuit after adjusting the source-drain parasitic capacitance is the radio frequency switching circuit in this embodiment. Since the size of the switching transistor affects the source-drain parasitic capacitance of the switching transistor, the source-drain parasitic capacitance of the switching transistor can be adjusted by adjusting the spacing between adjacent lateral gates of the switching transistor. In the rf switch circuit after the source-drain parasitic capacitance is adjusted (i.e., the rf switch circuit of this embodiment), the pitch between the adjacent lateral gates 11 of the switching transistors in each switching transistor unit group is smaller than the pitch between the adjacent lateral gates 11 of the switching transistors in the following switching transistor unit group.
The voltage difference introduced by the difference in the spacing between adjacent lateral gates 11 of the switching transistors in each of the switching transistor cell groups and the spacing between adjacent lateral gates 11 of the switching transistors in the next one of the switching transistor cell groups will balance the voltage difference of the switching transistors in the two switching transistor cell groups due to non-idealities. The voltage difference of the switch transistors in the two adjacent switch transistor unit groups due to non-ideal factors can be obtained through a simulation method. For example, the voltage difference introduced by the difference in the spacing between adjacent lateral gates 11 of the switching transistors in the switching transistor cell group G 1 and the switching transistor cell group G 2 (i.e., the difference in the source-drain voltage of the switching transistor M 1 and the source-drain voltage of the switching transistor M 2 in the ideal case) can be balanced by 0.1V by adjusting the spacing between adjacent lateral gates 11 of the switching transistor in the switching transistor cell group G 1 and the switching transistor cell group G 2 when the voltage of the switching transistor M 1 in the emulated switching transistor cell group G 1 is 0.1V higher than the voltage of the switching transistor M 2 in the switching transistor cell group G 2 (i.e., the voltage difference formed by the non-ideal factors), thereby making the voltage division of the switching transistor M 1 in the switching transistor cell group G 1 and the switching transistor M 2 in the switching transistor cell group G 2 the same. The present embodiment preferably adjusts the pitch between the adjacent lateral gates 11 of the switching transistors in the adjacent two switching transistor cell groups simultaneously to balance (compensate for) the voltage difference of the switching transistors in the two switching transistor cell groups due to non-ideal factors. In this embodiment, the area of the rf switch circuit is preferably the same as that of the rf switch circuit in the prior art, that is, when the interval between the adjacent lateral gates 11 of the switch transistors in the switch transistor unit group is adjusted, the size of the switch transistors in part of the switch transistor unit group is reduced, and the size of the switch transistors in part of the switch transistor unit group is increased, so as to ensure that the total area of the rf switch circuit is unchanged. In other embodiments, when adjusting the spacing between adjacent lateral gates of the switching transistors in the switching transistor cell group, the size of the switching transistors in the switching transistor cell group may be fully scaled up or down (relative to the size of the switching transistors in the prior art), as long as voltage balancing of different switching transistors is ensured, i.e. the total area of the rf switching circuit may also be varied.
In summary, the rf switch circuit provided by the present invention divides n-stage switch transistor units into L switch transistor unit groups along the rf current direction, each of the switch transistor units includes a switch transistor and a resistor (a gate bias resistor, a body bias resistor and a path resistor), the gate, the body, the source and the drain of the switch transistor are all connected together through the resistor, and the layout of each switch transistor is an interdigital structure. Different parasitic capacitances are designed for different switch transistor unit groups, so that the radio frequency switch is guaranteed to have more balanced voltage distribution under the high-voltage condition, the power processing capacity of the radio frequency switch circuit is improved, and the radio frequency switch circuit design with high power processing capacity is realized. The radio frequency switch circuit provided by the invention has the beneficial effects of ingenious structural design, lower production cost, excellent working performance and the like.
The embodiment of the invention also provides an integrated circuit chip. The integrated circuit chip comprises the radio frequency switch circuit provided by the embodiment, and is used in a radio frequency front-end module in a wireless communication system, and the radio frequency switch circuit has the function of accurately switching and controlling the transmission path of radio frequency signals and gating corresponding radio frequency paths. The specific structure of the rf switching circuit in the integrated circuit chip is not described in detail herein.
In addition, the radio frequency switch circuit provided by the invention can also be used in electronic equipment as an important component of a communication assembly. The electronic device herein refers to a computer device that can be used in a mobile environment and supports multiple communication systems such as GSM, EDGE, TD _scdma, tdd_lte, fdd_lte, 5G, and the like, including mobile phones, notebook computers, tablet computers, and vehicle-mounted computers. In addition, the technical scheme provided by the invention is also suitable for other occasions of communication assembly application, such as a communication base station and the like.
In addition, it will be understood that while the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It is also to be understood that this invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as having the definition of a logical "or" rather than a logical exclusive or "unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.
Claims (8)
1. A radio frequency switch circuit is characterized by comprising n stages of switch transistor units which are connected in series, wherein the n stages of switch transistor units are divided into L switch transistor unit groups along the radio frequency current direction, 1<L is less than or equal to n, each stage of switch transistor unit comprises a switch transistor, a grid bias resistor, a body bias resistor and a path resistor,
The grid electrode of each switching transistor is respectively connected with the corresponding grid electrode bias resistor, the drain electrode and the source electrode are respectively connected with the corresponding path resistor, and the body electrode is respectively connected with the corresponding body electrode bias resistor; the grid bias resistors in each stage of the switching transistor units are sequentially connected in series, and then the tail ends of the grid bias resistors are connected with grid bias voltage; the body electrode bias resistors in each stage of the switching transistor units are sequentially connected in series, and then the tail ends of the body electrode bias resistors are connected with body electrode bias voltages;
The grid electrode of each switching transistor comprises a plurality of parallel transverse grids, the distance between the adjacent transverse grids of the switching transistors in each switching transistor unit group is smaller than the distance between the adjacent transverse grids of the switching transistors in the next switching transistor unit group, and the distances between the adjacent transverse grids of all switching transistors in the same switching transistor unit group are the same; the distance between the lateral gate of the switching transistor in each switching transistor unit group and the metal contact point of the adjacent source electrode or drain electrode is smaller than the distance between the lateral gate of the switching transistor in the next switching transistor unit group and the metal contact point of the adjacent source electrode or drain electrode.
2. The radio frequency switching circuit according to claim 1, wherein the layout structure of each of the switching transistors is an inter-digitated structure.
3. The radio frequency switching circuit of claim 1 wherein a voltage difference introduced by a difference in pitch between adjacent lateral gates of said switching transistors in each of said switching transistor cell groups and adjacent lateral gates of said switching transistors in a subsequent one of said switching transistor cell groups balances a voltage difference created by switching transistors in each of said switching transistor cell groups and subsequent one of said switching transistor cell groups due to non-idealities including parasitic capacitance between gate and source of switching transistor, parasitic capacitance between gate and drain of switching transistor, parasitic capacitance between body and source of switching transistor, and parasitic capacitance of source and drain to ground of switching transistor.
4. The radio frequency switching circuit of claim 1, wherein a source of each stage of the switching transistor is connected to a drain of a switching transistor in a next stage of the switching transistor unit, an output of each stage of the switching transistor unit is a source of a switching transistor in the stage of the switching transistor unit, and an input of each stage of the switching transistor unit is a drain of a switching transistor in the stage of the switching transistor unit.
5. The radio frequency switching circuit of claim 1, wherein the lengths of the individual lateral gates of all switching transistors in a same switching transistor cell group are the same.
6. The radio frequency switching circuit according to claim 1, wherein all switching transistors in a same switching transistor cell group are the same size.
7. An integrated circuit chip comprising the radio frequency switching circuit of any one of claims 1-6.
8. An electronic device comprising a radio frequency switching circuit as claimed in any one of claims 1 to 6.
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| US9525063B2 (en) * | 2013-10-30 | 2016-12-20 | Infineon Technologies Austria Ag | Switching circuit |
| US12040238B2 (en) * | 2013-11-12 | 2024-07-16 | Skyworks Solutions, Inc. | Radio-frequency switching devices having improved voltage handling capability |
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| KR20220001812A (en) * | 2020-06-30 | 2022-01-06 | 삼성전기주식회사 | Radio frequency switch |
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| CN115692443A (en) * | 2022-10-18 | 2023-02-03 | 南京大学 | Voltage type global shutter photosensitive detector based on composite dielectric gate capacitor and method |
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| CN112909029A (en) * | 2021-02-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Radio frequency switch device |
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