CN117895814A - Topological circuit of single-phase three-wire system inverter and control method thereof - Google Patents
Topological circuit of single-phase three-wire system inverter and control method thereof Download PDFInfo
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Abstract
The application provides a single-phase three-wire system inverter topology circuit and a control method thereof, wherein the single-phase three-wire system inverter topology circuit comprises: the first end of the first bus capacitor is connected with the positive electrode of the power supply, and the first end of the second bus capacitor is connected with the negative electrode of the power supply; the first bridge arm, the second bridge arm and the balance bridge arm are connected in parallel with a first node and a second node, wherein the first node is connected with the positive electrode of the power supply, and the second node is connected with the negative electrode of the power supply; the balance bridge arm comprises a first balance transistor and a second balance transistor which are connected in series, wherein the drain electrode of the first balance transistor is connected with the positive electrode of the power supply, and the source electrode of the second balance transistor is connected with the negative electrode of the power supply; one end of the balance inductor is connected with the midpoint of the first bus capacitor and the second bus capacitor, and the other end of the balance inductor is connected with the connecting point of the first balance transistor and the second balance transistor. The topology circuit can rapidly respond to the unbalanced load condition and maintain the neutral point potential balance of the capacitor.
Description
Technical Field
The application relates to the field of power electronic converters, in particular to a single-phase three-wire system inverter topology circuit and a control method thereof.
Background
The electric energy AC/DC micro-grid and the DC/AC inverter technology can be applied to the field of new energy grid-connected power generation. The single-phase three-wire system inverter is a device for converting direct current into alternating current, and when a load changes or an input voltage fluctuates, the single-phase three-wire system inverter can automatically adjust an output voltage or frequency and reduce harmonic components of the output voltage or current through a filter circuit.
The single-phase three-wire system inverter comprises a two-level structure, wherein the single-phase three-wire system inverter controls high level and low level to alternately appear through a switching tube, and based on the single-phase three-wire system inverter, direct current is converted into alternating current, so that alternating current output voltage is formed. The harmonic wave of the output voltage of the two-level structure is larger, and corresponding filtering measures are needed to be adopted in the application scene of high voltage or high power.
Because the voltage harmonic content generated by the two-level structure is large, the unbalanced condition of the grid phase voltage occurs, and the response speed is slow when the load is processed to be unbalanced, the two-level structure can not provide stable grid voltage, and the power supply quality is difficult to maintain.
Disclosure of Invention
The application provides a topological circuit of a single-phase three-wire system inverter and a control method thereof, which can rapidly respond to the unbalanced load condition and maintain the potential balance of the midpoint of a capacitor.
In a first aspect, the present application provides a single-phase three-wire inverter topology comprising: the power supply, the first bus capacitor, the second bus capacitor, the first bridge arm, the second bridge arm, the balance bridge arm and the balance inductor. The first bus capacitor is connected with the second bus capacitor in series, the first end of the first bus capacitor is connected with the positive electrode of the power supply, and the first end of the second bus capacitor is connected with the negative electrode of the power supply; the first bridge arm, the second bridge arm and the balance bridge arm are connected in parallel with a first node and a second node, wherein the first node is connected with the positive electrode of the power supply, and the second node is connected with the negative electrode of the power supply; the balance bridge arm comprises a first balance transistor and a second balance transistor which are connected in series, wherein the drain electrode of the first balance transistor is connected with the positive electrode of the power supply, and the source electrode of the second balance transistor is connected with the negative electrode of the power supply; one end of the balance inductor is connected with the midpoint of the first bus capacitor and the second bus capacitor, and the other end of the balance inductor is connected with the connecting point of the first balance transistor and the second balance transistor.
Optionally, the first bridge arm includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The drain electrode of the first transistor is connected with the positive electrode of the power supply, the source electrode of the first transistor is connected with the drain electrode of the fourth transistor, the source electrode of the fourth transistor is connected with the negative electrode of the power supply, the drain electrode of the second transistor is connected with the source electrode of the first transistor at a third node, the source electrode of the second transistor is connected with the source electrode of the third transistor, and the drain electrode of the third transistor is connected with the second end of the first bus capacitor.
Optionally, the second bridge arm includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The drain electrode of the fifth transistor is connected with the positive electrode of the power supply, the source electrode of the fifth transistor is connected with the drain electrode of the eighth transistor, the source electrode of the eighth transistor is connected with the negative electrode of the power supply, the drain electrode of the sixth transistor is connected with the source electrode of the fifth transistor at the fourth node, the source electrode of the sixth transistor is connected with the source electrode of the seventh transistor, and the drain electrode of the seventh transistor is connected with the second end of the second bus capacitor.
Optionally, the single-phase three-wire system inverter topology circuit of the present application further includes a first filter and a second filter, wherein an input end of the first filter is connected with a third node, an output end of the second filter is connected with a fourth node, and a load and/or a power grid is/are arranged between the output end of the first filter and the input end of the second filter.
In a second aspect, the present application further provides a control method of a single-phase three-wire system inverter, where the control method is applied to the single-phase three-wire system inverter topology circuit according to the above embodiment, and the control method of the single-phase three-wire system inverter includes:
generating an output voltage, wherein the output voltage is a phase voltage with opposite phases generated based on a power supply, a first bridge arm and a second bridge arm; acquiring a first voltage of a first bus capacitor and a second voltage of a second bus capacitor, and calculating a voltage difference between the first voltage and the second voltage; if the voltage difference is smaller than or equal to a preset voltage difference threshold value, judging that the midpoint potential of the first bus capacitor and the second bus capacitor is balanced; and if the voltage difference is greater than the preset voltage difference threshold, discharging the first bus capacitor and/or the second bus capacitor by utilizing the balance bridge arm so as to maintain the balance of the midpoint potential of the capacitors of the first bus capacitor and the second bus capacitor.
Optionally, discharging the first bus capacitor and/or the second bus capacitor by using the balance bridge arm includes: calculating a first balance charge amount based on the voltage difference, the capacitance value of the first bus capacitor and the capacitance value of the second bus capacitor, wherein the first balance charge amount is used for representing the charge amount to be released when the midpoint potential of the capacitors of the first bus capacitor and the second bus capacitor is balanced; based on the first balanced charge quantity and the inductance value of the balanced inductor, adjusting the duty ratio of the balanced bridge arm; and discharging the first bus capacitor and/or the second bus capacitor based on a reactive power loop formed by the regulated balance bridge arm and the balance inductor.
Optionally, the control method of the single-phase three-wire system inverter provided by the application further includes: comparing the first voltage with the second voltage; if the first voltage is larger than the second voltage, the duty ratio of the first balance transistor is adjusted, and the first bus capacitor is discharged; and if the first voltage is smaller than the second voltage, the duty ratio of the second balance transistor is adjusted, and the second bus capacitor is discharged.
Optionally, the output voltage is adjusted by adjusting the duty cycle of the driving signal of the first bridge arm and the duty cycle of the driving signal of the second bridge arm.
Optionally, the control method of the single-phase three-wire system inverter provided by the application further includes: charging the first bus capacitor and/or the second bus capacitor by using the balance bridge arm comprises the following steps: calculating a second balancing charge amount based on the voltage difference, the capacitance value of the first bus capacitor and the capacitance value of the second bus capacitor, wherein the second balancing charge amount is used for representing the charge amount to be injected when the midpoint potential of the capacitors of the first bus capacitor and the second bus capacitor are balanced; based on the second balanced charge quantity and the inductance value of the balance inductor, adjusting the duty ratio of the balance bridge arm; and charging the first bus capacitor and/or the second bus capacitor based on a reactive power loop formed by the regulated balance bridge arm and the balance inductor.
Optionally, the operation modes of the single-phase three-wire system inverter topology circuit include a grid-connected mode and an off-grid mode, and in the grid-connected mode, the single-phase three-wire system inverter topology circuit is integrated into a power grid through an output relay; in off-grid mode, the topology circuit of the single-phase three-wire system inverter is directly connected to a load.
According to the technical scheme, the application provides a single-phase three-wire system inverter topology circuit and a control method thereof, wherein the single-phase three-wire system inverter topology circuit comprises: the first bus capacitor is connected with the second bus capacitor in series, the first end of the first bus capacitor is connected with the positive electrode of the power supply, and the first end of the second bus capacitor is connected with the negative electrode of the power supply; the first bridge arm, the second bridge arm and the balance bridge arm are connected in parallel with a first node and a second node, wherein the first node is connected with the positive electrode of the power supply, and the second node is connected with the negative electrode of the power supply; the balance bridge arm comprises a first balance transistor and a second balance transistor which are connected in series, wherein the drain electrode of the first balance transistor is connected with the positive electrode of the power supply, and the source electrode of the second balance transistor is connected with the negative electrode of the power supply; one end of the balance inductor is connected with the midpoint of the first bus capacitor and the second bus capacitor, and the other end of the balance inductor is connected with the connecting point of the first balance transistor and the second balance transistor. The topology circuit can rapidly respond to the unbalanced load condition and maintain the neutral point potential balance of the capacitor.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of a topology circuit of a single-phase three-wire inverter according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating steps of a control method of a single-phase three-wire inverter according to an embodiment of the present application;
FIG. 3 is an exemplary diagram of a control system for a single-phase three-wire inverter according to an embodiment of the present application;
fig. 4 is an off-grid simulated waveform example diagram of a single-phase three-wire inverter according to an embodiment of the present application;
fig. 5 is an off-grid experimental waveform example diagram of a single-phase three-wire inverter according to an embodiment of the present application;
fig. 6 is a waveform example diagram of a grid-connected experiment of a single-phase three-wire inverter according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the examples below do not represent all embodiments consistent with the present application. Merely as examples of systems and methods consistent with some aspects of the present application as detailed in the claims.
It should be noted that the brief description of the terms in the present application is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present application. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
The terms "first," second, "" third and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for limiting a particular order or sequence, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
The single-phase three-wire system power grid is provided with two live wires and a zero wire, if the live wire 1 is L 1 The live wire 2 is L 2 Zero line is o, then L 1 The voltage value between the voltage and the o point is +120V, L 2 The voltage value between the voltage and the o point is 120V. When the power of the electric appliance is smaller, the electric appliance is connected with L 1 Between o-point or L 2 And o-point, using phase voltages for power supply. When the power of the electric appliance is larger, the electric appliance is connected with L 1 And L is equal to 2 The power is supplied between the points using a line voltage of 240V.
A single-phase three-wire grid can be produced by the secondary winding of the transformer, but this production has drawbacks that can lead to an imbalance in the phase voltage of the grid when the load of the single-phase three-wire grid is unbalanced. As the load increases, the grid voltage also decreases, affecting the quality and reliability of the power supply. Therefore, a single-phase three-wire inverter is required to convert direct current into alternating current and maintain the stability of the circuit. When load change or input voltage fluctuation occurs, the single-phase three-wire system inverter can automatically adjust output voltage or frequency, and harmonic components of the output voltage or current are reduced through the filter circuit, so that power supply stability of a power grid is realized.
The single-phase three-wire system inverter includes a two-level structure. In the two-level structure, a single three-wire inverter controls the high level and the low level to alternately appear through a switching tube, and converts direct current into alternating current so as to form alternating current output voltage. The harmonic wave of the output voltage of the two-level structure is larger, and the power supply quality can not be ensured in the application scene of high voltage or high power.
Because the voltage harmonic content generated by the two-level structure of the single-phase three-wire system inverter is large, the voltage of the power grid phase is unbalanced, and the response speed is low when the load is unbalanced. Therefore, the two-level structure cannot provide a stable grid voltage, and it is difficult to maintain the power supply quality.
In order to quickly respond to the situation of unbalanced load and improve the stability of the circuit, some embodiments of the present application provide a topology circuit of a single-phase three-wire system inverter, fig. 1 is a schematic diagram of the topology circuit of the single-phase three-wire system inverter according to the embodiment of the present application, and the topology circuit of the single-phase three-wire system inverter of the embodiment is described in detail below according to fig. 1.
It should be understood that, in some embodiments of the present application, a single-phase three-wire inverter is provided that uses a T-type structure to generate three levels, including: the high level, the medium level and the low level realize three different level outputs by utilizing the single-phase conductivity of the transistor so as to meet different load demands.
Some embodiments of the present application provide a single-phase three-wire inverter topology circuit, comprising: power supply U dc First bus capacitor C 1 Second bus capacitor C 2 First bridge arm L 1 Second bridge arm L 2 Balance bridge arm and balance inductance. Wherein, the first bus capacitor C 1 And a second bus capacitor C 2 Series connection of first bus capacitor C 1 Is connected with the power supply U dc The positive electrode is connected with a second bus capacitor C 2 Is connected with the power supply U dc The negative electrode is connected; first bridge arm L 1 Second bridge arm L 2 The balance bridge arm is connected in parallel with the first node P and the second node N, wherein the first node P is connected with the power supply U dc The positive electrode is connected with the second node N and the power supply U dc The negative electrode is connected; the balance bridge arm comprises a first balance transistor S connected in series c1 And a second balance transistor S c2 Wherein the first balance transistor S c1 Drain of (d) and power supply U dc Positive electrode is connected to a second balance transistor S c2 Source of (d) and power supply U dc The negative electrode is connected; one end of the balance inductor is connected with the first bus capacitor C 1 And a second bus capacitor C 2 Is connected with the midpoint of the capacitor of the balance inductor, and the other end of the balance inductor is connected with the first balance transistor S c1 And a second balance transistor S c2 Is connected to the connection point of (c).
In some embodiments, the first bus capacitor C 1 Second bus capacitor C 2 With power supply U dc Series connection of first bus capacitor C 1 And a second bus capacitor C 2 Secondary ripple can be taken over and the influence of transient voltages on the circuit elements is reduced. In addition, a first bus capacitor C 1 And a second bus capacitor C 2 The power supply voltage can be smoothed, and the overcharge condition of the power supply voltage can be prevented.
In some embodiments, the first bridge arm L is controlled by a first controller 1 The second bridge arm L is controlled by a second controller 2 And controlling the balance bridge arm by using a third controller. First bridge arm L 1 Second bridge arm L 2 And the balance bridge arm is controlled independently, and direct current is converted into alternating current, so that the conversion and transmission of electric energy are realized. Wherein the first bridge arm L 1 And a second bridge arm L 2 The balance bridge arm is used for generating phase voltages with opposite phases, and when loads in the topological circuit are balanced, the balance bridge arm does not act; when the load in the topological circuit is unbalanced, the balance bridge arm acts to ensure the balance of the neutral point potential of the capacitor.
In some embodiments, the balancing bridge arm includes a first balancing transistor S in series c1 And a second balance transistor S c2 Wherein the first balance transistor S c1 Drain of (d) and power supply U dc Positive electrode is connected to a second balance transistor S c2 Source of (d) and power supply U dc The negative electrode is connected. First balance transistor S c1 And a second balance transistor S c2 As a voltage-controlled semiconductor device, a first balance transistor S is exemplified c1 And a second balance transistor S c2 Is a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) element. The MOSFET element can efficiently convert direct current into alternating current, so that the conversion efficiency of the inverter is improved.
For example, a voltage is applied between the gate and source of the transistor, which creates an electric field that causes electrons to flow between the source and drain of the transistor, forming a current. By varying the gate voltage, the magnitude of the drain current and the switching state can be controlled. Specifically, the gate voltage of the transistor is changed by the controller.
In some embodiments, the balancing inductance acts to smooth the current through filtering, thereby eliminating high frequency noise. One end of the balance inductor is connected with the first bus capacitor C 1 And a second bus capacitor C 2 Is connected with the midpoint of the capacitor of the balance inductor, and the other end of the balance inductor is connected with the first balance transistor S c1 And a second balance transistor S c2 Is connected to the connection point of (c). When the load in the topological circuit is unbalanced, the first balancing transistor S is based on the balancing inductance c1 And a second balance transistor S c2 Form a reactive power loop by supplying a reactive power to the first bus capacitor C 1 Or a second bus capacitor C 2 Reactive power is injected to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
In some embodiments, first leg L 1 Comprising the following steps: first transistor S a1 Second transistor S a2 Third transistor S a3 And a fourth transistor S a4 . Wherein the first transistor S a1 Drain of (d) and power supply U dc The positive electrode is connected to the first transistor S a1 Source of (d) and fourth transistor S a4 Drain electrode connection of fourth transistor S a4 Source of (d) and power supply U dc The negative electrode is connected to the second transistor S a2 Drain electrode of (d) and first transistor S a1 A source electrode of the second transistor S is connected to the third node a2 Source of (d) and third transistor S a3 Source connection of third transistor S a3 Drain electrode of (C) and first bus capacitor C 1 Is connected to the second end of the first connector.
Exemplary, first transistor S a1 Second transistor S a2 Third transistor S a3 And a fourth transistor S a4 Are MOSFET devices. Wherein the first transistor S a1 And a second transistor S a2 Is inverted in the driving signal of the third transistor S a3 And a fourth transistor S a4 Is inverted with respect to the drive signal of (a). Adjusting the first transistor S with the first controller a1 And a fourth transistor S a4 The duty ratio of the driving signal of the first bridge arm L is further adjusted 1 Is set, the output voltage of which is set.
In some embodiments, second leg L 2 Comprising the following steps: fifth transistor S b1 Sixth transistor S b2 Seventh transistor S b3 And an eighth transistor S b4 . Wherein the fifth transistor S b1 Drain of (d) and power supply U dc Positive electrode is connected to a fifth transistor S b1 Source electrode of (v) and eighth transistor S b4 Drain electrode connection of eighth transistor S b4 Source of (d) and power supply U dc Negative electrode is connected to a sixth transistor S b2 Drain of (d) and fifth transistor S b1 A source electrode of the sixth transistor S is connected to the fourth node b2 Source of (c) and seventh transistor S b3 Source connection of seventh transistor S b3 Drain electrode of (C) and second bus capacitor C 2 Is connected to the second end of the first connector.
Exemplary, fifth transistor S b1 Sixth transistor S b2 Seventh transistor S b3 And an eighth transistor S b4 Are MOSFET devices. Wherein the fifth transistor S b1 And a sixth transistor S b2 Is inverted in the driving signal of (a) a seventh transistor S b3 And an eighth transistor S b4 Is inverted with respect to the drive signal of (a). Adjusting the fifth transistor S with the second controller b1 And an eighth transistor S b4 The duty ratio of the driving signal of the second bridge arm L is adjusted 2 Is set, the output voltage of which is set.
In some embodiments, first leg L 1 And a second bridge arm L 2 Symmetrically utilize the first bridge arm L 1 And a second bridge arm L 2 A phase voltage with opposite phase is generated as an output voltage.
In some embodiments, the single-phase three-wire inverter topology further includes a first filter L f1 And a second filter L f2 Wherein the first filter L f1 Is connected to the third node, a second filter L f2 The output end of (1) is connected with a fourth node, a first filter L f1 And a second filter L f2 Between the inputs of (a) is a load and/or a grid.
Illustratively, a first filter L f1 And a second filter L f2 Is a passive filter, is a filter circuit formed by combination of inductance, capacitance and resistance, and is used for filtering high-frequency components and smoothing the first bridge arm L 1 And a second bridge arm L 2 The output voltage, and then the output current in the circuit is more stable.
In some embodiments, the output of the single-phase three-wire inverter is connected to the grid or load through an rimless filter. Under the grid-connected mode, the single-phase three-wire system inverter is connected into a power grid through an output relay, and current is injected into the power grid; in off-grid mode, the single-phase three-wire inverter is directly connected to the load.
In the embodiment of the present application, when load imbalance or abrupt load change occurs, the neutral potential imbalance of the capacitor occurs, i.e. the first bus capacitor C 1 Voltage and second bus capacitor C 2 The voltage difference of the voltage is too large. At this time, the output voltage is unstable, the voltages at the two ends of the power device in the topology circuit are unbalanced, and the hidden trouble of system fault exists. First bus capacitor C by using balance bridge arm 1 Or a second bus capacitor C 2 Charging or discharging to maintain the first bus capacitor C 1 And a second bus capacitor C 2 The neutral point potential of the capacitor is balanced, so that the quality of output voltage and current is improved, and the stability of the circuit is further improved.
In some embodiments, a first bus capacitor C 1 Is greater than the second bus capacitor C 2 Based on the balanced inductance and the first balanced transistor S c1 The reactive power loop is formed for the first bus capacitor C 1 Discharging to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
In some embodiments, a second bus capacitor C 2 Is greater than the first bus capacitor C 1 Based on the balance inductance and the second balance transistor S c2 The reactive power loop is formed for the second bus capacitor C 2 Discharging to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
In some embodiments, a first bus capacitor C 1 Is greater than the second bus capacitor C 2 Based on the balance inductance and the second balance transistor S c2 The reactive power loop is formed for the second bus capacitor C 2 Charging is performed to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
In some embodiments, a second bus capacitor C 2 The voltage is greater than the first bus capacitor C 1 Voltage, based on balance inductance and first balance transistor S c1 The reactive power loop is formed for the first bus capacitor C 1 Charging is performed to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
It should be appreciated that the balancing bridge arm is maintaining the first bus capacitance C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the first bus capacitor C can be independently used 1 Or a second bus capacitor C 2 Charging or discharging may be performed simultaneously with the first bus capacitor C 1 And a second bus capacitor C 2 Charging or discharging the first balance transistor S according to different situations c1 And a second balance transistor S c2 And (3) making adaptive changes to the connection mode of the device.
Based on the topology circuit of the single-phase three-wire system inverter described in the above embodiment, some embodiments of the present application further provide a control method of the single-phase three-wire system inverter. The method is applied to the single-phase three-wire inverter topology circuit as described in the above embodiments.
Fig. 2 is a schematic diagram illustrating steps of a control method of a single-phase three-wire inverter according to an embodiment of the present application; fig. 3 is a diagram illustrating an example of a control system of a single-phase three-wire inverter according to an embodiment of the present application. The method of this embodiment will be described in detail with reference to fig. 2 and 3.
Step S210, generating an output voltage.
In some embodiments, a DC power supply U is utilized dc First bridge arm L 1 And a second bridge arm L 2 Generating phase oppositionThe phase voltage is used as the output voltage. By adjusting the first arm L 1 Duty ratio of driving signal of (2) and second arm L 2 The drive signal duty cycle of (2) adjusts the output voltage.
In some embodiments, first leg L 1 And a second bridge arm L 2 Symmetrically, the first bridge arm L is controlled by the first controller 1 The second bridge arm L is controlled by a second controller 2 The third controller is utilized to control the balance bridge arm so as to form a closed-loop control system, and then the single-phase three-wire inverter is enabled to drive the direct current power supply U dc Is converted into an alternating current power supply, and maintains the neutral point potential balance of the capacitor. The first controller comprises a first voltage loop controller and a first current loop controller; the second controller includes a second voltage loop controller and a second current loop controller.
In some embodiments, the operating modes of the single-phase three-wire inverter topology circuit include a grid-tie mode in which the single-phase three-wire inverter is incorporated into the power grid through the output relay and an off-grid mode; in off-grid mode, the single-phase three-wire inverter is directly connected to the load.
In an off-grid mode, for example, an output sampling voltage and an output sampling current of the single-phase three-wire inverter are obtained, and a first output reference voltage is generated by a first controller. The first output reference voltage is differenced from the output sampling voltage, and the difference is transmitted to a first voltage loop controller, which calculates a first output reference current. And the first output reference current and the output sampling current are subjected to difference, the difference is transmitted to a first current loop controller, the first current loop controller calculates a modulation voltage, the modulation voltage is modulated and delayed, and finally a first modulation signal is output. The first controller controls the first bridge arm L through a first modulation signal 1 The duty ratio of the driving signal of the first bridge arm L is further adjusted 1 Is a voltage of (2);
a second output reference voltage is generated by a second controller. The second output reference voltage and the output sampling voltage are differenced, and the difference is transmitted to a second voltage loop controller, and the second voltage loop controller calculates a second voltageAnd outputting a reference current. And the second output reference current and the output sampling current are subjected to difference, the difference is transmitted to a second current loop controller, the second current loop controller calculates a modulation voltage, the modulation voltage is modulated and delayed, and finally a second modulation signal is output. The second controller controls the second bridge arm L through a second modulation signal 2 The duty ratio of the driving signal of the second bridge arm L is adjusted 2 Is set in the above-described voltage range.
In an example, in a grid-connected mode, an output sampling current of the single-phase three-wire system inverter is obtained, a first output reference current is generated through a first controller, the first output reference current and the output sampling current are differenced, the difference value is transmitted to a first current loop controller, the first current loop controller generates a modulation voltage through calculation, modulates and delays the modulation voltage, and finally a first modulation signal is output. The first controller controls the first bridge arm L through a first modulation signal 1 The duty ratio of the driving signal of the first bridge arm L is further adjusted 1 Is a voltage of (2);
and generating a second output reference current through a second controller, differencing the second output reference current with an output sampling current, transmitting the difference to a second current loop controller, calculating a modulation voltage by the second current loop controller, modulating and delaying the modulation voltage, and finally outputting a second modulation signal. The second controller controls the second bridge arm L through a second modulation signal 2 The duty ratio of the driving signal of the second bridge arm L is adjusted 2 Is set in the above-described voltage range.
In the embodiment of the present application, the first bridge arm L is controlled by the first controller 1 The second bridge arm L is controlled by a second controller 2 And a third controller is used for controlling the balance bridge arm to realize decoupling control of the zero line voltage and the live line voltage.
Step S220, obtaining a first bus capacitor C 1 First voltage and second bus capacitor C of (a) 2 And calculates a voltage difference between the first voltage and the second voltage.
For example, due to the conditions of overload of a topological circuit of a single-phase three-wire system inverter, asymmetric parameters of a power device and the likeThe condition will lead to the fluctuation of the neutral point potential of the capacitor, resulting in the first bus capacitor C 1 First voltage and second bus capacitor C of (C) 2 Is not equal. Calculating the voltage difference between the first voltage and the second voltage, and if the voltage difference is too large, indicating the first bus capacitor C 1 And a second bus capacitor C 2 The neutral point potential of the capacitor is unbalanced, so that the output voltage is unstable, the voltage of a power device in a topological circuit is unbalanced, and the hidden trouble of system faults exists.
Step S230, comparing the voltage difference with a preset voltage difference threshold, and determining the first bus capacitor C if the voltage difference is less than or equal to the preset voltage difference threshold 1 And a second bus capacitor C 2 Is balanced with the neutral point potential of the capacitor; if the voltage difference is greater than the preset voltage difference threshold, utilizing the balance bridge arm to pair the first bus capacitor C 1 Or a second bus capacitor C 2 Discharging to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
For example, the voltage difference is smaller than a preset voltage difference threshold, and the first bus capacitor C is determined 1 And a second bus capacitor C 2 At this time, the first bridge arm L is controlled by the first controller 1 The second bridge arm L is controlled by a second controller 2 So that the first bridge arm L 1 And a second bridge arm L 2 Phase voltages of opposite phases are generated, while the balancing bridge arm does not act.
For example, the voltage difference is greater than a preset voltage difference threshold, and the first bus capacitor C is determined 1 And a second bus capacitor C 2 At the moment, the first bridge arm L is controlled by the first controller 1 The second bridge arm L is controlled by a second controller 2 So that the first bridge arm L 1 And a second bridge arm L 2 Generating phase voltages with opposite phases, and controlling the balance bridge arm by using the third controller to enable the balance bridge arm to correspond to the first bus capacitor C 1 Or a second bus capacitor C 2 Discharging to maintain the first bus capacitor C 1 And a second bus capacitor C 2 Is balanced by the neutral potential of the capacitor.
In some embodiments, the first voltage is compared to the second voltage; if the first voltage is greater than the second voltage, the first balance transistor S is adjusted c1 For the first bus capacitor C 1 Discharging; if the first voltage is smaller than the second voltage, the second balance transistor S is regulated c2 For the second bus capacitor C 2 And performing discharge.
Exemplary, first bus capacitor C 1 Is greater than the second bus capacitor C 2 A third controller is used for sending a modulation signal to the balance bridge arm to adjust the first balance transistor S c1 To realize the duty ratio of the first bus capacitor C 1 Is provided.
Exemplary, first bus capacitor C 1 Is smaller than the second bus capacitor C 2 A third controller is used for sending a modulation signal to the balance bridge arm to adjust a second balance transistor S c2 To realize the second bus capacitor C 2 Is provided.
In some embodiments, based on the first bus capacitance C 1 First voltage and second bus capacitor C of (C) 2 A voltage difference of the second voltage of (C) a first bus capacitor 1 And a second bus capacitor C 2 Calculating a first balanced charge quantity for characterizing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral point potential of the capacitor is balanced, the electric charge quantity to be released is needed; based on the first balanced charge quantity and the inductance value of the balanced inductor, adjusting the duty ratio of the balanced bridge arm; based on the reactive power loop formed by the regulated balance bridge arm and the balance inductor, the first bus capacitor C is connected with the second bus capacitor C 1 Or a second bus capacitor C 2 And (5) discharging.
The third controller is exemplified by 1 Calculating the capacitance value representing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the first bus capacitor C 1 A first amount of balanced charge is required to be released. The third controller combines the first balanced charges according to kirchhoff's voltage lawThe inductance value of the quantity and balance inductance is calculated, and the modulation signal is sent to a first balance transistor S in a balance bridge arm c1 For adjusting the first balance transistor S c1 Is a duty cycle of (c). Regulated first balance transistor S c1 Reactive power loop formed by balancing inductance and corresponding to first bus capacitor C 1 And performing discharge.
The third controller is exemplified by 2 Calculating the capacitance value representing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the second bus capacitor C 2 A first amount of balanced charge is required to be released. The third controller calculates a modulation signal according to kirchhoff' S voltage law by combining the first balanced charge quantity and the inductance value of the balanced inductor, and sends the modulation signal to a second balanced transistor S in the balanced bridge arm c2 For adjusting the second balance transistor S c2 Is a duty cycle of (c). Regulated second balancing transistor S c2 Reactive power loop formed by balancing inductance and corresponding second bus capacitor C 2 And performing discharge.
In other embodiments, the first bus capacitor C is coupled by a balancing bridge arm 1 Or a second bus capacitor C 2 Charging is performed. Based on the voltage difference, the first bus capacitor C 1 And a second bus capacitor C 2 Calculating a second balanced charge quantity, the second balanced charge quantity being used for characterizing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral point potential of the capacitor is balanced, the charge quantity to be injected is needed; based on the second balanced charge quantity and the inductance value of the balance inductor, adjusting the duty ratio of the balance bridge arm; based on the reactive power loop formed by the regulated balance bridge arm and the balance inductor, the first bus capacitor C is connected with the second bus capacitor C 1 Or a second bus capacitor C 2 And (5) charging.
The third controller is exemplified by 1 Calculating the capacitance value representing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the first bus capacitor C 1 Second balance requiring injectionThe amount of charge. The third controller calculates a modulation signal according to kirchhoff' S voltage law by combining the second balanced charge amount and the inductance value of the balance inductor, and sends the modulation signal to the first balance transistor S in the balance bridge arm c1 For adjusting the first balance transistor S c1 Is a duty cycle of (c). Regulated first balance transistor S c1 Reactive power loop formed by balancing inductance and corresponding to first bus capacitor C 1 Charging is performed.
The third controller is exemplified by 2 Calculating the capacitance value representing the first bus capacitor C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the second bus capacitor C 2 The second amount of balanced charge to be injected is required. The third controller calculates a modulation signal according to kirchhoff' S voltage law by combining the second balancing charge amount and the inductance value of the balancing inductance, and sends the modulation signal to a second balancing transistor S in the balancing bridge arm c2 For adjusting the second balance transistor S c2 Is a duty cycle of (c). Regulated second balancing transistor S c2 Reactive power loop formed by balancing inductance and corresponding second bus capacitor C 2 Charging is performed.
It should be appreciated that the balancing bridge arm is maintaining the first bus capacitance C 1 And a second bus capacitor C 2 When the neutral potential of the capacitor is balanced, the first bus capacitor C can be independently used 1 Or a second bus capacitor C 2 Charging or discharging may be performed simultaneously with the first bus capacitor C 1 And a second bus capacitor C 2 Charging or discharging the first balance transistor S according to different situations c1 And a second balance transistor S c2 And (3) making adaptive changes to the connection mode of the device.
Fig. 4 is an off-grid simulation waveform example diagram of a single-phase three-wire inverter according to an embodiment of the present application, in which the single-phase three-wire inverter according to the embodiment is simulated in an off-grid mode, and one phase of the single-phase three-wire inverter is connected to a 2000W resistive load, and the other phase is idle. As can be seen from fig. 4, the first bus capacitor C in the single-phase three-wire inverter 1 Is higher than the first voltage of (1)And a second bus capacitor C 2 The second voltages of (2) are approximately equal, indicating that the midpoint potential of the capacitor is balanced under the control of the balance bridge arm.
Fig. 5 is a waveform example graph of an off-grid experiment of the single-phase three-wire inverter according to the embodiment of the present application, where the single-phase three-wire inverter according to the embodiment is tested in the off-grid mode, and one phase of the single-phase three-wire inverter is connected to a 2000W resistive load, and the other phase is idle. As can be seen from fig. 5, when the output voltage is 500V, the voltage of the midpoint potential of the capacitor is 249.5V, which is approximately half of the bus voltage, and this illustrates that the midpoint potential of the capacitor is balanced under the control of the balance arm.
Fig. 6 is a waveform example diagram of a grid-connected experiment of the single-phase three-wire system inverter according to the embodiment of the present application, where the single-phase three-wire system inverter outputs a current to the single-phase three-wire system power grid, and the amplitude of the current is 18.84A, which illustrates that the single-phase three-wire system inverter according to the embodiment can maintain the neutral point potential balance of the capacitor in the grid-connected mode.
According to the technical scheme, the application provides a single-phase three-wire system inverter topology circuit and a control method thereof, wherein the single-phase three-wire system inverter topology circuit comprises: first bus capacitor C 1 And a second bus capacitor C 2 First bus capacitor C 1 Is connected with the power supply U dc The positive electrode is connected with a second bus capacitor C 2 Is connected with the power supply U dc The negative electrode is connected; first bridge arm L 1 Second bridge arm L 2 The balance bridge arm is connected in parallel with the first node P and the second node N, wherein the first node and the power supply U dc The positive electrode is connected with the second node and the power supply U dc The negative electrode is connected; the balance bridge arm comprises a first balance transistor S connected in series c1 And a second balance transistor S c2 Wherein the first balance transistor S c1 Drain of (d) and power supply U dc Positive electrode is connected to a second balance transistor S c2 Source of (d) and power supply U dc The negative electrode is connected; one end of the balance inductor is connected with the first bus capacitor C 1 And a second bus capacitor C 2 Is connected with the midpoint of the capacitor of the balance inductor, and the other end of the balance inductor is connected with the first balance transistor S c1 And a second balance transistor S c2 Is connected to the point of connection of (2)And (5) connection. The topology circuit can rapidly respond to the unbalanced load condition and maintain the neutral point potential balance of the capacitor.
The foregoing detailed description of the embodiments is merely illustrative of the general principles of the present application and should not be taken in any way as limiting the scope of the invention. Any other embodiments developed in accordance with the present application without inventive effort are within the scope of the present application for those skilled in the art.
Claims (10)
1. A single-phase three-wire inverter topology, comprising: a power supply, a first bus capacitor, a second bus capacitor, a first bridge arm, a second bridge arm, a balance bridge arm and a balance inductance, wherein,
the first bus capacitor is connected with the second bus capacitor in series, the first end of the first bus capacitor is connected with the positive electrode of the power supply, and the first end of the second bus capacitor is connected with the negative electrode of the power supply;
the first bridge arm, the second bridge arm and the balance bridge arm are connected in parallel with a first node and a second node, wherein the first node is connected with the positive electrode of the power supply, and the second node is connected with the negative electrode of the power supply;
the balance bridge arm comprises a first balance transistor and a second balance transistor which are connected in series, wherein the drain electrode of the first balance transistor is connected with the positive electrode of the power supply, and the source electrode of the second balance transistor is connected with the negative electrode of the power supply;
one end of the balance inductor is connected with the midpoint of the first bus capacitor and the second bus capacitor, and the other end of the balance inductor is connected with the connecting point of the first balance transistor and the second balance transistor.
2. The single-phase three-wire inverter topology of claim 1, wherein said first leg comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein,
the drain electrode of the first transistor is connected with the positive electrode of the power supply, the source electrode of the first transistor is connected with the drain electrode of the fourth transistor, the source electrode of the fourth transistor is connected with the negative electrode of the power supply, the drain electrode of the second transistor is connected with the source electrode of the first transistor at a third node, the source electrode of the second transistor is connected with the source electrode of the third transistor, and the drain electrode of the third transistor is connected with the second end of the first bus capacitor.
3. The single-phase three-wire inverter topology of claim 1, wherein said second leg comprises: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein,
the drain electrode of the fifth transistor is connected with the positive electrode of the power supply, the source electrode of the fifth transistor is connected with the drain electrode of the eighth transistor, the source electrode of the eighth transistor is connected with the negative electrode of the power supply, the drain electrode of the sixth transistor is connected with the source electrode of the fifth transistor at a fourth node, the source electrode of the sixth transistor is connected with the source electrode of the seventh transistor, and the drain electrode of the seventh transistor is connected with the second end of the second bus capacitor.
4. The single-phase three-wire inverter topology according to claim 1, further comprising a first filter and a second filter, wherein an input of the first filter is connected to the third node, an output of the second filter is connected to the fourth node, and a load and/or a power grid is between the output of the first filter and the input of the second filter.
5. A control method of a single-phase three-wire inverter, applied to the single-phase three-wire inverter topology circuit of any one of claims 1 to 4, the control method comprising:
generating an output voltage, wherein the output voltage is a phase voltage with opposite phases generated based on a power supply, a first bridge arm and a second bridge arm;
acquiring a first voltage of a first bus capacitor and a second voltage of a second bus capacitor, and calculating a voltage difference between the first voltage and the second voltage;
if the voltage difference is smaller than or equal to a preset voltage difference threshold value, judging that the midpoint potential of the first bus capacitor and the second bus capacitor is balanced;
and if the voltage difference is larger than the preset voltage difference threshold, discharging the first bus capacitor and/or the second bus capacitor by utilizing a balance bridge arm so as to maintain the balance of the midpoint potential of the first bus capacitor and the second bus capacitor.
6. The control method according to claim 5, wherein discharging the first bus bar capacitance and/or the second bus bar capacitance with a balance bridge arm includes:
calculating a first balanced charge quantity based on the voltage difference, the capacitance value of the first bus capacitor and the capacitance value of the second bus capacitor, wherein the first balanced charge quantity is used for representing the charge quantity to be released when the midpoint potential of the capacitors of the first bus capacitor and the second bus capacitor is balanced;
adjusting the duty ratio of the balance bridge arm based on the first balance charge amount and the inductance value of the balance inductance;
and discharging the first bus capacitor and/or the second bus capacitor based on a reactive power loop formed by the regulated balance bridge arm and the balance inductor.
7. The control method according to claim 6, characterized by further comprising:
comparing the first voltage with the second voltage;
if the first voltage is larger than the second voltage, the duty ratio of a first balance transistor is adjusted, and the first bus capacitor is discharged;
and if the first voltage is smaller than the second voltage, adjusting the duty ratio of a second balance transistor, and discharging the second bus capacitor.
8. The control method according to claim 5, characterized in that the generating an output voltage further comprises:
and adjusting the output voltage by adjusting the driving signal duty ratio of the first bridge arm and the driving signal duty ratio of the second bridge arm.
9. The control method of claim 5, further comprising charging the first bus capacitor and/or the second bus capacitor with a balancing bridge arm, comprising:
calculating a second balanced charge amount based on the voltage difference, the capacitance value of the first bus capacitor and the capacitance value of the second bus capacitor, wherein the second balanced charge amount is used for representing the charge amount to be injected when the midpoint potential of the capacitors of the first bus capacitor and the second bus capacitor is balanced;
adjusting the duty ratio of the balance bridge arm based on the second balance charge amount and the inductance value of the balance inductance;
and charging the first bus capacitor and/or the second bus capacitor based on a reactive power loop formed by the regulated balance bridge arm and the balance inductor.
10. The control method of claim 5, wherein the operating modes of the single-phase three-wire inverter topology circuit include a grid-tie mode and an off-grid mode, the method further comprising:
in the grid-connected mode, the single-phase three-wire system inverter topology circuit is integrated into a power grid through an output relay;
in the off-grid mode, the single-phase three-wire system inverter topology circuit is directly connected to a load.
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| US20150207433A1 (en) * | 2014-01-22 | 2015-07-23 | Lite-On Electronics (Guangzhou) Limited | Single-phase three-wire power control system and power control method therefor |
| CN113765428A (en) * | 2021-08-31 | 2021-12-07 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| CN114257107A (en) * | 2020-09-22 | 2022-03-29 | 株洲变流技术国家工程研究中心有限公司 | NPC type three-level inverter circuit |
| CN116780922A (en) * | 2023-06-29 | 2023-09-19 | 西安理工大学 | F-type three-level grid-connected inverter topological structure and modulation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20150207433A1 (en) * | 2014-01-22 | 2015-07-23 | Lite-On Electronics (Guangzhou) Limited | Single-phase three-wire power control system and power control method therefor |
| CN114257107A (en) * | 2020-09-22 | 2022-03-29 | 株洲变流技术国家工程研究中心有限公司 | NPC type three-level inverter circuit |
| CN113765428A (en) * | 2021-08-31 | 2021-12-07 | 河北科技大学 | Active neutral point clamped three-level converter and regulation and control method thereof |
| CN116780922A (en) * | 2023-06-29 | 2023-09-19 | 西安理工大学 | F-type three-level grid-connected inverter topological structure and modulation method thereof |
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