CN117895775A

CN117895775A - Quick-charging chip and soft start method thereof

Info

Publication number: CN117895775A
Application number: CN202410288861.8A
Authority: CN
Inventors: 朱冬勇; 罗周益; 周江云; 卿健
Original assignee: Chengdu Yichong Wireless Power Technology Co ltd
Current assignee: Chengdu Yichong Wireless Power Technology Co ltd
Priority date: 2024-03-14
Filing date: 2024-03-14
Publication date: 2024-04-16

Abstract

The application belongs to the field of charging, and provides a quick-charging chip and a soft-starting method thereof, wherein in a first stage, a first target field effect transistor in a switched capacitor circuit of the quick-charging chip is controlled to be continuously conducted so as to precharge all cross-over capacitors in the switched capacitor circuit to a first voltage; in the second stage, the first type field effect transistor and the second type field effect transistor are switched on according to a preset period so as to precharge each bridging capacitor to a corresponding target voltage and finish soft start, wherein the first type field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the second type field effect transistor is one or more power field effect transistors after the first type field effect transistor is removed for the switched capacitor circuit. After all the bridging capacitors are precharged to the first voltage, the first phase is ended and the second phase is entered. In this application scheme, through prefilling in stages, under the requirement of accomplishing soft start fast, guarantee prefilling process is more steady, promotes the security.

Description

Quick-charging chip and soft start method thereof

Technical Field

The application relates to the field of charging, in particular to a quick charging chip and a soft starting method thereof.

Background

With the continuous upgrading of performances and functions of handheld electronic devices, mobile phones and the like, the requirements of mobile devices on battery capacity are increasing. Meanwhile, the demand for rapid charging of large-capacity batteries is also increasing. The charging system is a standard configuration such as a charging system of a mobile phone, which can rapidly charge a battery of several thousand milliamperes in several tens of minutes, in addition to a general charging path.

A commonly used fast-charge chip includes a switched capacitor circuit (Switched Capacitor Converter, abbreviated as SCC), which includes a plurality of Power field effect transistors (Power MOS transistors) and a plurality of Flying capacitors (also called Flying capacitors or Flying capacitors). The SCC is formed by a plurality of power field effect transistors and a plurality of bridging capacitors in a parallel connection and/or series connection mode so as to realize input/output conversion of different voltages and currents.

The fast charge chip needs to precharge the crossover capacitor in the SCC during operation, a process also known as soft start. How to ensure that the quick-charging chip can safely, quickly and stably complete soft start becomes a problem of concern of the person skilled in the art.

Disclosure of Invention

The present application is directed to a fast-charging chip and a soft-start method thereof, so as to at least partially improve the above-mentioned problems.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

in a first aspect, an embodiment of the present application provides a method for soft start of a fast charging chip, where the method includes:

in the first stage, a first target field effect transistor in a switched capacitor circuit of a fast charging chip is controlled to be continuously conducted so as to precharge all bridging capacitors in the switched capacitor circuit to a first voltage;

the first target field effect transistor is one or more power field effect transistors in the switched capacitor circuit;

in the second stage, switching the first field effect transistor and the second field effect transistor to be conducted according to a preset period so as to precharge each bridging capacitor to a corresponding target voltage, and completing soft start;

the first type field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the second type field effect transistor is one or more power field effect transistors of the switched capacitor circuit excluding the first type field effect transistor.

In a second aspect, an embodiment of the present application provides a fast charging chip, where the fast charging chip includes: the control unit is connected with the switch capacitance circuit;

The control unit is used for controlling a first target field effect transistor in a switched capacitor circuit of the fast charging chip to be continuously conducted in a first stage so as to precharge all cross-over capacitors in the switched capacitor circuit to a first voltage;

the control unit is used for switching the first field effect transistor and the second field effect transistor to be conducted according to a preset period in the second stage so as to precharge each bridging capacitor to a corresponding target voltage and finish soft start;

Compared with the prior art, the fast charging chip and the soft starting method thereof provided by the embodiment of the application control the first target field effect transistor in the switched capacitor circuit of the fast charging chip to be continuously conducted in the first stage so as to precharge all the bridging capacitors in the switched capacitor circuit to the first voltage; the first target field effect transistor is one or more power field effect transistors in the switched capacitor circuit; in the second stage, switching the first type field effect transistor and the second type field effect transistor to be conducted according to a preset period so as to precharge each bridging capacitor to a corresponding target voltage, and completing soft start; the first type of field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the second type of field effect transistor is one or more power field effect transistors of the switched capacitor circuit excluding the first type of field effect transistor. After all the bridging capacitors are precharged to the first voltage, the first phase is ended and the second phase is entered. In this application scheme, through prefilling in stages, under the requirement of accomplishing soft start fast, guarantee prefilling process is more steady, promotes the security.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a switched capacitor circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a driving signal of a second stage according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a control unit according to an embodiment of the present disclosure;

FIG. 4 is a second schematic structural diagram of the control unit according to the embodiment of the present disclosure;

FIG. 5 is a second schematic diagram of the driving signals of the second stage according to the embodiment of the present application;

FIG. 6 is a schematic diagram illustrating peak current comparison provided in an embodiment of the present application;

fig. 7 is a flow chart of a soft start method of a fast charging chip according to an embodiment of the present application.

In the figure: 110-a logic control unit; 120-a driving unit; a 121-conversion circuit; 122-a driving circuit; 123-clamping circuits; a 124-delay circuit; 125-selection circuit.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

The switching capacitor circuit in the fast charge chip can realize the conversion of the input and output N-1 of different voltages and currents, for example, in a forward N-1 mode, the conversion ratio of the input voltage to the output voltage is 4-1, 3-1, 2-1 and 1-1, and the conversion ratio of the input current to the output current is 1-4 and 1-3 and 1-2 and 1-1; in the reverse 1-N mode, the conversion ratio of the input voltage to the output voltage is 1-4, 1-3, 1-2, and 1-1, and the conversion ratio of the input current to the output current is 4-1, 3-1, 2-1, and 1-1. The switching capacitor circuit has high conversion efficiency, and N-1 can be other conversion ratios, such as 8-1, 6-1, and the like.

In the forward N-1 working mode, if N-1 is 4-1, the input voltage is 20V, the output voltage VOUT=5V, and the output voltage can be kept within 3.8V-4.2V by selecting proper input voltage, so that the battery charger is very suitable for charging single lithium batteries. Meanwhile, the input current can be 3A, the output current is 12A, the charging power of about 50W can be easily realized, and the charging efficiency of consumer mobile equipment such as mobile phones and the like is remarkably improved. Even two fast charging chips can be used to realize hundreds of watts of charging power.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a switched capacitor circuit according to an embodiment of the present application. As shown in fig. 1, the switched capacitor circuit includes a first power fet Q1, a second power fet Q2, a third power fet Q3, a fourth power fet Q4, a fifth power fet Q5, a sixth power fet Q6, a seventh power fet Q7, an eighth power fet Q8, a first crossover capacitor CF1, a second crossover capacitor CF2, and a third crossover capacitor CF3.

The first end of the first power fet Q1 is connected to an input end (PMID, also referred to as VIN) of the switched capacitor circuit, the second end of the first power fet Q1 is connected to a first end of the second power fet Q2, and the third end of the first power fet Q1 is connected to a control unit (not shown in fig. 1).

A connection terminal (CP 1 TOP) is led out between the first power fet Q1 and the second power fet Q2 and connected to the upper plate of the first crossover capacitor CF 1. The second end of the second power fet Q2 is connected to the first end of the third power fet Q3, and the third end of the second power fet Q2 is connected to a control unit (not shown in fig. 1).

A connection terminal (CP 2 TOP) is led out between the second power fet Q2 and the third power fet Q3 and connected to the upper plate of the second crossover capacitor CF 2. The second end of the third power fet Q3 is connected to the first end of the fourth power fet Q4. The third terminal of the third power fet Q3 is for connection to a control unit (not shown in fig. 1).

A connection terminal (CP 3 TOP) is led out between the third power fet Q3 and the fourth power fet Q4 and connected to the upper plate of the third crossover capacitor CF 3. The second end of the fourth power field effect transistor Q4 is connected to the first end of the fifth power field effect transistor Q5 and the first end of the seventh power field effect transistor Q7, respectively. A connection terminal is led out from the second end of the fourth power field effect transistor Q4 and is used as an output end (VOUT) of the switched capacitor circuit. The third terminal of the fourth power fet Q4 is for connection to a control unit (not shown in fig. 1).

The second terminal of the fifth power fet Q5 is connected to the first terminal of the sixth power fet Q6, and the third terminal of the fifth power fet Q5 is connected to a control unit (not shown in fig. 1). The second terminal of the sixth power fet Q6 is grounded, and the third terminal of the sixth power fet Q6 is connected to a control unit (not shown in fig. 1). A connection terminal (CP 1_bot) is led out between the fifth power fet Q5 and the sixth power fet Q6 and is connected to the lower plate of the first crossover capacitor CF1 and the lower plate of the third crossover capacitor CF 3.

The second end of the seventh power fet Q7 is connected to the first end of the eighth power fet Q8, the second end of the eighth power fet Q8 is grounded, and the third end of the seventh power fet Q7 and the third end of the eighth power fet Q8 are both connected to a control unit (not shown in fig. 1). A connection terminal (CP 2_bot) is led out between the seventh power fet Q7 and the eighth power fet Q8 and is connected to the lower plate of the second crossover capacitor CF 2.

In an alternative embodiment, the switched capacitor circuit further includes an output capacitor COUT, an upper plate of the output capacitor COUT is connected to the output terminal (VOUT), and a lower plate of the output capacitor COUT is grounded.

In the switched capacitor circuit shown in fig. 1, the number of power field effect transistors is up to 8, the number of cross-over capacitors is also 3, and the voltages at two ends of different cross-over capacitors need to be pre-charged at different voltage values, which provides new challenges for the fast-charging chip to safely, quickly and stably complete soft start.

In order to overcome the above problems, an embodiment of the present application provides a fast charging chip, including: the control unit is connected with the switched capacitor circuit.

It should be noted that, the switched capacitor circuit in the fast-charging chip in the embodiment of the present application may be, but not limited to, the switched capacitor circuit shown in fig. 1. The control unit is respectively connected with the third end of each power field effect transistor of the switch capacitor circuit.

The control unit may include a logic control unit 110 and M driving units 120, as shown in fig. 3 below. The logic control unit 110 is connected to the input ends of the M driving units 120, the output end of the ith driving unit 120 is connected to the third end of the ith power fet, M is the number of power fets, taking fig. 1 as an example, and m=8. The driving unit 120 may output a driving signal under the control of the logic control unit 110 to control the on state of the corresponding power fet, such as a full on state, a current-limiting on state, and a cut-off state.

The control unit is used for controlling the first target field effect transistor in the switched capacitor circuit of the fast charging chip to be continuously conducted in the first stage so as to precharge all the bridging capacitors in the switched capacitor circuit to the first voltage.

The first target field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the first stage can be the first stage after the fast charging chip is powered on. The first voltage may be, but is not limited to, the voltage VOUT at the output of the switched-capacitor circuit when operating in the forward mode, and the first voltage may be, but is not limited to, the voltage VIN at the input of the switched-capacitor circuit when operating in the reverse mode.

Taking the switched capacitor circuit shown in fig. 1 as an example in the forward N-1 (4-1) mode, the first target fet includes a second power fet Q2, a third power fet Q3, a fourth power fet Q4, a sixth power fet Q6, and an eighth power fet Q8, and all the crossover capacitors include a first crossover capacitor CF1, a second crossover capacitor CF2, and a third crossover capacitor CF3.

The first power fet Q1, the fifth power fet Q5, and the seventh power fet Q7 are not first target fets, and are in a cut-off state in the first stage.

For the on state of the first target fet in the first stage, an alternative implementation is provided in the embodiments of the present application, please refer to the following.

The control unit is used for controlling one or more first target field effect transistors to be fully conducted, controlling the remaining first target field effect transistors to be conducted in a current-limiting mode, and pre-charging all bridging capacitors in the switched capacitor circuit to a first voltage.

Continuing to take the example of the switched capacitor circuit shown in fig. 1 operating in the forward N-1 (4-1) mode, the second power fet Q2, the third power fet Q3, and the fourth power fet Q4 are in a fully-on state in the first stage, and the sixth power fet Q6 and the eighth power fet Q8 are in a current-limiting on state in the first stage.

After all the bridging capacitors are precharged to the first voltage, the first phase is ended and the second phase is entered. In this application scheme, through prefilling in stages, under the requirement of accomplishing soft start fast, guarantee prefilling process is more steady, promotes the security.

The control unit is used for switching the first field effect transistor and the second field effect transistor to be conducted according to a preset period in the second stage so as to precharge each bridging capacitor to a corresponding target voltage and finish soft start.

The first type of field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the second type of field effect transistor is one or more power field effect transistors of the switched capacitor circuit excluding the first type of field effect transistor.

Continuing to take the switched capacitor circuit shown in fig. 1 as an example in the forward N-1 (4-1) mode, the first type of field effect transistor includes a first power field effect transistor Q1, a third power field effect transistor Q3, a fifth power field effect transistor Q5 and an eighth power field effect transistor Q8, and the second type of field effect transistor includes a second power field effect transistor Q2, a fourth power field effect transistor Q4, a sixth power field effect transistor Q6 and a seventh power field effect transistor Q7. The target voltage corresponding to the first crossover capacitor CF1 is 3 times of the voltage VOUT at the output end, the target voltage corresponding to the second crossover capacitor CF2 is 2 times of the voltage VOUT at the output end, and the target voltage corresponding to the third crossover capacitor CF3 is 1 time of the voltage VOUT at the output end.

Regarding how to switch the first type field effect transistor and the second type field effect transistor on according to a preset period in the second stage, an alternative implementation manner is further provided in the embodiment of the present application, please refer to fig. 2, fig. 2 is a schematic diagram of a driving signal in the second stage provided in the embodiment of the present application. Wherein, T1 is preceded by a first stage and T1 to T2 are second stages.

The control unit is used for controlling the second type field effect transistor to be switched into a cut-off state after entering the ith period, and then controlling the first type field effect transistor to be switched into a conduction state for a first duration.

Wherein i is greater than or equal to 1.

After the i-th period is entered, the control unit sends corresponding driving signals, such as low-level signals, to the second type field effect transistors (the second power field effect transistor Q2, the fourth power field effect transistor Q4, the sixth power field effect transistor Q6 and the seventh power field effect transistor Q7) so as to switch the second type field effect transistors into the cut-off state. After the second type fet is switched to the cut-off state, the control unit sends corresponding driving signals, such as high-level signals, to the first type fet (the first power fet Q1, the third power fet Q3, the fifth power fet Q5, and the eighth power fet Q8) to switch the first type fet to the on state for a first duration.

After the first type field effect transistor is switched into a conducting state and lasts for a first time period, the control unit is used for controlling the first type field effect transistor to be switched into a cutting-off state and then controlling the second type field effect transistor to be switched into the conducting state and lasts for a second time period.

Optionally, after the first period of time, the control unit sends corresponding driving signals, such as low-level signals, to the first type field effect transistor (the first power field effect transistor Q1, the third power field effect transistor Q3, the fifth power field effect transistor Q5, and the eighth power field effect transistor Q8) so as to switch the first type field effect transistor to the cut-off state. After the first type field effect transistor is switched to the cut-off state, a corresponding driving signal, for example, a high-level signal, is sent to the second type field effect transistor (the second power field effect transistor Q2, the fourth power field effect transistor Q4, the sixth power field effect transistor Q6 and the seventh power field effect transistor Q7) so that the second type field effect transistor is switched to the on state for a second duration.

After the second period of time is over, the next (i+1) period is entered, and the first field effect transistor and the second field effect transistor are repeatedly switched on until the second stage is over.

It should be noted that, in the second stage, the first type field effect transistor and the second type field effect transistor operate in different phases and cannot be conducted at the same time point. Optionally, one period is divided into a phase a (corresponding to a first time period) and a phase B (corresponding to a second time period), where the first type of field effect transistor operates in the phase a and the second type of field effect transistor operates in the phase B.

In an alternative embodiment, the first field effect transistor includes a first field effect transistor and a second field effect transistor, the second field effect transistor includes a third field effect transistor and a fourth field effect transistor, wherein the first field effect transistor is a field effect transistor in a fully conductive state when the second phase is conductive, the second field effect transistor is a field effect transistor in a current-limiting conductive state when the second phase is conductive, the third field effect transistor is a field effect transistor in a fully conductive state when the second phase is conductive, and the fourth field effect transistor is a field effect transistor in a current-limiting conductive state when the second phase is conductive.

Continuing to take the switched capacitor circuit shown in fig. 1 as an example when operating in the forward N-1 (4-1) mode, the third power fet Q3 and the fifth power fet Q5 in the first type of fets are first type fets, and the first power fet Q1 and the eighth power fet Q8 are second type fets. The second power field effect transistor Q2, the fourth power field effect transistor Q4 and the sixth power field effect transistor Q6 in the second type field effect transistor are third type field effect transistors, and the seventh power field effect transistor Q7 is fourth type field effect transistor.

The drive signal of the fet in the current-limited on state is lower than the drive signal of the fet in the full on state.

On the basis of fig. 2, an alternative implementation manner is further provided in the embodiment of the present application regarding how to drive the power fet, please refer to fig. 3, fig. 3 is a schematic structural diagram of the control unit provided in the embodiment of the present application.

The driving unit 120 includes a conversion circuit 121, a driving circuit 122, and a clamp circuit 123.

The switching circuits 121 are respectively connected to different power domains, VPOS-VNEG and VDD-VSS as shown. The first and second terminals of the conversion circuit 121 are respectively connected to the logic control unit 110, and optionally, to different ports. The first terminal of the conversion circuit 121 is configured to receive the control signal (qx_drv) transmitted by the logic control unit 110, and the second terminal of the conversion circuit 121 is configured to receive the current limit enable signal (ilim_en) transmitted by the logic control unit 110. It should be noted that, only when the corresponding power fet needs to be in the current-limiting conductive state, the logic control unit 110 will send out the current-limiting enable signal.

A third terminal of the conversion circuit 121 is connected to the driving circuit 122. The conversion circuit 121 is configured to transfer a control signal (qx_drv) from the VDD-VSS domain to the VPOS-VNEG domain, and to transfer the converted control signal to the driving circuit 122.

The fourth terminal of the conversion circuit 121 is connected to the clamp circuit 123. The switching circuit 121 is configured to switch the received current limit enable signal (from VDD-VSS domain to VPOS-VNEG domain), and to transmit the switched signal to the clamp circuit 123.

The clamping circuit 123 is connected to the driving circuit 122, and the clamping circuit 123 and the driving circuit 122 are configured to clamp when receiving the current-limiting enable signal, so that the driving circuit 122 clamps the driving signal (qx_gate) output according to the received control signal to the second voltage, and the corresponding power fet Qx is in a current-limiting conductive state when being conductive. When the clamp circuit 123 does not receive the current limiting enable signal, the clamp circuit 123 does not clamp the driving circuit 122, the driving circuit 122 outputs a driving signal (qx_gate) with a higher third voltage according to the received control signal, and the corresponding power fet Qx is in a fully conductive state when being conductive. Wherein the third voltage is higher than the second voltage as shown in fig. 2.

Fig. 3 shows only the connection relationship between the logic control unit 110 and the x-th driving unit 120, and similarly, the connection relationship between the logic control unit 110 and the M driving units 120 can be known.

In the timing shown in fig. 2, the first field-effect transistor (including the first power field-effect transistor Q1, the third power field-effect transistor Q3, the fifth power field-effect transistor Q5, and the eighth power field-effect transistor Q8) operating in the same phase may be synchronously connected to the driving signal, and the second field-effect transistor (including the second power field-effect transistor Q2, the fourth power field-effect transistor Q4, the sixth power field-effect transistor Q6, and the seventh power field-effect transistor Q7) operating in the other phase may be synchronously connected to the driving signal, and may be synchronously switched to the on state.

Continuing to take the switched capacitor circuit shown in fig. 1 as an example in the forward N-1 (4-1) mode, after the second stage (time T1) is entered, the first power fet Q1, the third power fet Q3, the fifth power fet Q5 and the eighth power fet Q8 are switched to the conducting state, the lower plate of the third across capacitor CF3 is connected to the output terminal (VOUT) through the fifth power fet Q5, the upper plate of the third across capacitor CF3 is connected to the upper plate of the second across capacitor CF2 through the third power fet Q3, and the lower plate of the second across capacitor CF2 is connected to the ground through the eighth power fet Q8 that is current-limited and conducting.

Since the eighth power fet Q8 is in the current-limited on state, the voltage cf2_top in the figure jumps to 2 times the voltage VOUT at the output terminal, and the voltage cp2_bot also jumps up to around the voltage VOUT at the output terminal. Due to the size of the eighth power fet Q8 and the influence of parasitic capacitance (Cgd capacitance), the CP2_bot voltage suddenly jumps will bring the gate voltage of the eighth power fet Q8 in the current-limiting state, also called gate voltage, which will cause the current-limiting capability of the eighth power fet Q8 to be weakened or even vanished. At this time, a spike current (also referred to as spike current) that enters from the output terminal and passes through the fifth power fet Q5, the third power fet Q3, and the eighth power fet Q8 to the bottom occurs.

In order to avoid or mitigate the occurrence of the spike current, an alternative implementation manner is further provided in the embodiment of the present application, please refer to fig. 4, fig. 4 is a schematic diagram of a second structure of the control unit provided in the embodiment of the present application. The variation of fig. 4 with respect to fig. 3 is that the driving unit 120 further comprises a delay circuit 124 and a selection circuit 125.

As shown in fig. 4, the third terminal of the conversion circuit 121 is connected to the first terminal of the delay circuit 124 and the first terminal (a) of the selection circuit 125, the second terminal of the delay circuit 124 is connected to the second terminal (b) of the selection circuit 125, and the third terminal (z) of the selection circuit 125 is connected to the driving circuit 122, wherein the delay circuit 124 may be a rising delay generating circuit (rising delay gen.).

When the corresponding power fet Qx is turned on synchronously, the selection circuit 125 selects the a path, i.e. the first end and the third end of the selection circuit 125 are turned on; when the corresponding power fet Qx is turned on in a delayed manner, for example, the eighth power fet Q8 in the figure, the selection circuit 125 selects the b path, i.e., the second terminal and the third terminal of the selection circuit 125 are turned on.

In an alternative embodiment, the fourth terminal of the switching circuit 121 is further connected to a selection circuit 125 (not shown in the figure), and the high-level selection circuit 125 selects the b path when the fourth terminal of the switching circuit 121, and the low-level selection circuit 125 selects the a path when the fourth terminal of the switching circuit 121.

When the selection circuit 125 selects the a path, the structure is equivalent to that shown in fig. 3, and will not be described here. When the b-path is selected by the selection circuit 125, the upper edge of the control signal introduces a delay time, i.e. a predetermined delay time period (also called Td, the value may be several tens ns). That is, the conversion circuit 121 transmits the converted control signal to the delay circuit 124, and when the control signal is on the upper edge, the delay circuit 124 transmits the received control signal to the driving circuit 122 through the b-path after the preset delay period Td. So that the partial field effect transistors (current-limiting on) operating in the same phase are switched to the on state after a delay period Td preset later.

It should be noted that, when receiving the current limiting enable signal, the clamp circuit 123 corresponding to the current-limiting conductive power fet Qx clamps the drive circuit 122, so that the drive circuit 122 clamps the drive signal (qx_gate) output according to the received control signal to the second voltage, and the corresponding power fet Qx is in the current-limiting conductive state when being conductive.

Referring to fig. 5, fig. 5 is a second schematic diagram of a driving signal of a second stage according to an embodiment of the present application.

The control unit is used for controlling the second field effect transistor to be switched into a cut-off state after entering the ith period, then controlling the second target field effect transistor to be switched into a conducting state, and controlling the third target field effect transistor to be switched into the conducting state after a preset delay time length, and continuing the first time length (the conducting time length of the second target field effect transistor).

The third target field effect transistor is any one second field effect transistor in the first field effect transistors. Optionally, the third target fet is a second fet grounded in the first fet. The second target field effect transistor is all the first field effect transistors except the third target field effect transistor.

Alternatively, the third target fet may be a preconfigured power fet requiring delayed activation.

Continuing with the example of the switched capacitor circuit shown in fig. 1 operating in the forward N-1 (4-1) mode, the third target fet is the eighth power fet Q8, and the second target fet is the first power fet Q1, the third power fet Q3, and the fifth power fet Q5. When the CP2_bot jumps to the voltage VOUT value near the output terminal, since the eighth power fet Q8 is switched to the on state after the preset delay period Td, the eighth power fet Q8 starts to be current-limited and turned on after the preset delay period Td, and the eighth power fet Q8 is turned on without being raised by the CP2_bot, so that the peak current is not generated.

After the first duration, the control unit is used for controlling the first type field effect transistor to switch to the cut-off state, and then controlling the second type field effect transistor to switch to the on state for the second duration.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating peak current comparison provided in an embodiment of the present application. Where 1xVOUT represents the voltage of the third flying capacitor CF3 equal to VOUT,2xVOUT represents the voltage of the second flying capacitor CF2 equal to VOUT×2, and 3xVOUT represents the voltage of the first flying capacitor CF1 equal to VOUT×3. In the figure, ipeak1 represents the peak current in the non-delay state corresponding to fig. 3, ipeak2 represents the peak current in the delay state corresponding to fig. 4, and the peak current can be significantly reduced by setting the delay to optimize the soft start.

After soft start is completed, that is, after each bridge capacitor is pre-charged to the corresponding target voltage, the bridge capacitor enters a third stage, and the first type field effect transistor (the first power field effect transistor Q1, the third power field effect transistor Q3, the fifth power field effect transistor Q5 and the eighth power field effect transistor Q8) and the second type field effect transistor (the second power field effect transistor Q2, the fourth power field effect transistor Q4, the sixth power field effect transistor Q6 and the seventh power field effect transistor Q7) are controlled to respectively work in different phases, the first type field effect transistor works in the phase a, the second type field effect transistor works in the phase B, and are all in a full-on state, so that charge conversion is started.

The method for soft start of the fast-charging chip provided in the embodiment of the present application may be applied to, but is not limited to, the fast-charging chip described above, and referring to fig. 7, the method for soft start of the fast-charging chip includes: s310 and S320 are specifically described below.

S310, in the first stage, the first target field effect transistor in the switched capacitor circuit of the fast charge chip is controlled to be continuously conducted so as to precharge all the cross-over capacitors in the switched capacitor circuit to the first voltage.

The first target field effect transistor is one or more power field effect transistors in the switched capacitor circuit.

And S320, switching the first field effect transistor and the second field effect transistor to be conducted according to a preset period in the second stage so as to precharge each bridging capacitor to a corresponding target voltage, and completing soft start.

In an alternative embodiment, S330 may also be executed after the soft start of the fast-charging chip is successful, as described in detail below.

S330, in the third stage, the first field effect transistor and the second field effect transistor are controlled to work in different phases respectively, and charging conversion is started.

The first field effect transistor works in the phase A, the second field effect transistor works in the phase B and is in a complete conduction state, and then charging conversion is started.

Referring to S310, referring to the following, S310, in the first stage, the step of controlling the first target fet in the switched capacitor circuit of the fast charge chip to be continuously turned on to precharge all the cross-over capacitors in the switched capacitor circuit to the first voltage includes: s311 is specifically described below.

And S311, controlling one or more first target field effect transistors to be fully conducted, and controlling the remaining first target field effect transistors to be current-limited and conducted so as to precharge all the cross-over capacitors in the switched capacitor circuit to the first voltage.

Referring to S320, referring to the following, S320, in the second stage, the first type field effect transistor and the second type field effect transistor are switched on according to a preset period to precharge each bridge capacitor to a corresponding target voltage, so as to complete the step of soft start, which is provided by the embodiment of fig. 7: s321 and S322 are specifically described below.

S321, after the ith period is entered, the second type field effect transistor is controlled to be switched into a cut-off state, and then the first type field effect transistor is controlled to be switched into a conduction state for a first duration.

S322, after the first time duration, the first field effect transistor is controlled to switch to the cut-off state, and then the second field effect transistor is controlled to switch to the on state for the second time duration.

Optionally, the first field effect transistor includes a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is a field effect transistor in a complete conducting state when the second phase is conducted, and the second field effect transistor is a field effect transistor in a current limiting conducting state when the second phase is conducted.

Referring to S320, referring to the following, S320, in the second stage, the first type field effect transistor and the second type field effect transistor are switched on according to a preset period to precharge each bridge capacitor to a corresponding target voltage, so as to complete the step of soft start, which is provided by the embodiment of fig. 7: s323 and S324 are specifically described below.

S323, after the ith period is entered, the second field effect transistor is controlled to be switched into a cut-off state, then the second target field effect transistor is controlled to be switched into a conducting state, and after a preset delay time period, the third target field effect transistor is controlled to be switched into the conducting state for a first time period.

The third target field effect transistor is any one second field effect transistor in the first field effect transistor, and the second target field effect transistor is all the first field effect transistor except the third target field effect transistor.

S324, after the first duration, the first field effect transistor is controlled to switch to the cut-off state, and then the second field effect transistor is controlled to switch to the on state for the second duration.

In summary, in the first stage, the first target field effect transistor in the switched capacitor circuit of the fast charging chip is controlled to be continuously turned on to precharge all the bridge capacitors in the switched capacitor circuit to the first voltage; the first target field effect transistor is one or more power field effect transistors in the switched capacitor circuit; in the second stage, switching the first type field effect transistor and the second type field effect transistor to be conducted according to a preset period so as to precharge each bridging capacitor to a corresponding target voltage, and completing soft start; the first type of field effect transistor is one or more power field effect transistors in the switched capacitor circuit, and the second type of field effect transistor is one or more power field effect transistors of the switched capacitor circuit excluding the first type of field effect transistor. After all the bridging capacitors are precharged to the first voltage, the first phase is ended and the second phase is entered. In this application scheme, through prefilling in stages, under the requirement of accomplishing soft start fast, guarantee prefilling process is more steady, promotes the security.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. The method for soft start of the quick-charging chip is characterized by comprising the following steps:

2. The soft start method of a fast charge chip of claim 1, wherein in the first stage, the step of controlling the first target fet in the switched capacitor circuit of the fast charge chip to be continuously turned on to precharge all the crossover capacitors in the switched capacitor circuit to the first voltage comprises:

and controlling one or more first target field effect transistors to be fully conducted, and controlling the rest of the first target field effect transistors to be conducted in a current-limiting way so as to precharge all the bridging capacitors in the switched capacitor circuit to a first voltage.

3. The method for soft start of a fast charge chip according to claim 1, wherein in the second stage, switching the first field effect transistor and the second field effect transistor on according to a preset period to precharge each of the bridge capacitors to a corresponding target voltage, and completing the soft start step, comprising:

After entering the ith period, controlling the second type field effect transistor to be switched into a cut-off state, and then controlling the first type field effect transistor to be switched into a conduction state for a first duration;

after the first time duration, the first type field effect transistor is controlled to switch to a cut-off state, and then the second type field effect transistor is controlled to switch to a conduction state for a second time duration.

4. The method of claim 1, wherein the first fet is a fully on state fet when the second stage is on, and the second fet is a current limiting on state fet when the second stage is on.

5. The soft start method of claim 4, wherein in the second stage, switching the first field effect transistor and the second field effect transistor on according to a preset period to precharge each of the bridge capacitors to a corresponding target voltage, and completing the soft start comprises:

after the ith period is entered, the second field effect transistor is controlled to be switched into a cut-off state, then the second target field effect transistor is controlled to be switched into a conducting state, and after a preset delay time length, the third target field effect transistor is controlled to be switched into the conducting state for a first time length;

The third target field effect transistor is any one of the second field effect transistors in the first field effect transistor, and the second target field effect transistor is all the first field effect transistors except the third target field effect transistor;

6. The utility model provides a quick charge chip which characterized in that, quick charge chip includes: the control unit is connected with the switch capacitance circuit;

7. The fast charge chip of claim 6, wherein the control unit is configured to control one or more of the first target field effect transistors to be fully turned on and to control the remaining first target field effect transistors to be current limited on so as to precharge all of the flying capacitors in the switched capacitor circuit to a first voltage.

8. The fast charge chip of claim 6, wherein the control unit is configured to control the second type field effect transistor to switch to a cut-off state after entering an i-th period, and then control the first type field effect transistor to switch to a conductive state for a first duration;

after the first duration, the control unit is configured to control the first type field effect transistor to switch to a cut-off state, and then control the second type field effect transistor to switch to a conducting state for a second duration.

9. The fast charge chip of claim 6, wherein the first type of field effect transistor comprises a first type of field effect transistor and a second type of field effect transistor, wherein the first type of field effect transistor is a field effect transistor in a fully conductive state when the second stage is conductive, and the second type of field effect transistor is a field effect transistor in a current limiting conductive state when the second stage is conductive.

10. The fast charge chip of claim 9, wherein the control unit is configured to control the second field effect transistor to switch to a cut-off state after entering an i-th period, then control the second target field effect transistor to switch to a conductive state, and control the third target field effect transistor to switch to a conductive state for a first period after a preset delay period;