CN117894817A

CN117894817A - Native NMOS device and method of making the same

Info

Publication number: CN117894817A
Application number: CN202211220650.8A
Authority: CN
Inventors: 林盈秀; 翁武得; 胡永中
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2024-04-16

Abstract

The invention provides a native NMOS element and a manufacturing method thereof. The native NMOS element includes: the semiconductor device comprises a P-type epitaxial layer, a first insulating region, a second insulating region, a first P-type well region, a second P-type well region, a grid, an N-type source electrode and an N-type drain electrode. The P-type epitaxial layer has a first P-type impurity doping concentration. The first P-type well region completely covers and is connected to the lower surface of the N-type source electrode. The second P-type well region completely covers and is connected to the lower surface of the N-type drain electrode. The first P-type well region and the second P-type well region are provided with second P-type impurity doping concentrations, the second P-type impurity doping concentrations are higher than the first P-type impurity doping concentrations, and the second P-type impurity doping concentrations are enough to prevent leakage current from flowing between the N-type drain current and the P-type substrate when the native NMOS element is operated.

Description

Native NMOS device and method of making the same

Technical Field

The present invention relates to a native NMOS device and a method for fabricating the same, and more particularly, to a native NMOS device capable of preventing leakage current and a method for fabricating the same.

Background

FIG. 1 is a schematic cross-sectional view of a prior art native NMOS device. The native NMOS device 10 includes a P-type epitaxial layer 111, insulating regions 121 and 122, a gate 13, an N-type source 14, an N-type drain 15, and a P-type contact 112. The P-type epitaxial layer 111 is formed on the P-type substrate 11. The N-type source 14 and the N-type drain 15 are formed under the outside of both sides of the gate 13. The gate 13 includes a dielectric layer, a conductive layer and a spacer layer, which are well known to those skilled in the art and will not be described herein.

U.S. patent application US20140197497A1 discloses a native PMOS device and a method for fabricating the same, wherein the native PMOS device has a low threshold voltage and a high driving current. European patent application EP0902466A1 discloses a method for manufacturing a native PMOS device, which integrates the manufacturing method of the native PMOS device with the process steps of the nonvolatile memory.

The above conventional native PMOS devices and the native NMOS devices shown in fig. 1 have the problem of too high leakage current. That is, when the native MOS device is turned on or off, there are problems of leakage current and penetration leakage (punch through leakage), so that the application range is limited, and there is a problem of high manufacturing cost, and the development of the size reduction is also limited.

In view of the above, the present invention provides a native NMOS device capable of preventing leakage current and a method for manufacturing the same, which can increase the application range and reduce the cost, and has smaller dimensions than the prior art at the same leakage current and through-leakage current specifications.

Disclosure of Invention

In one aspect, the present invention provides a native NMOS device comprising: a P-type epitaxial layer formed on a P-type substrate, the P-type epitaxial layer having a first P-type impurity doping concentration (impurity dopant concentration); a first insulating region and a second insulating region formed on the P-type epitaxial layer for defining an operation region between the first insulating region and the second insulating region; a first P-type well region and a second P-type well region formed in the P-type epitaxial layer by the same ion implantation process step; a grid electrode formed on the P-type epitaxial layer in the operation region; and an N-type source electrode and an N-type drain electrode which are formed in the P-type epitaxial layer in the operation region by the same ion implantation process step and are respectively positioned on the first P-type well region and the second P-type well region below the outer parts of the two sides of the grid electrode; wherein the first P-type well region completely covers and is connected to the lower surface of the N-type source electrode; wherein the second P-type well region completely covers and is connected to the lower surface of the N-type drain electrode; the first P-type well region and the second P-type well region are provided with a second P-type impurity doping concentration, the second P-type impurity doping concentration is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is enough to prevent leakage current from flowing between the N-type drain current and the P-type substrate when the native NMOS element operates.

In another aspect, the present invention provides a native NMOS device manufacturing method, comprising: forming a P-type epitaxial layer on a P-type substrate, wherein the P-type epitaxial layer has a first P-type impurity doping concentration; forming a first insulating region and a second insulating region on the P-type epitaxial layer to define an operating region between the first insulating region and the second insulating region; forming a first P-type well region and a second P-type well region in the P-type epitaxial layer by using the same ion implantation process step; forming a gate on the P-type epitaxial layer in the operation region; forming an N-type source electrode and an N-type drain electrode in the P-type epitaxial layer in the operation region respectively by the same ion implantation process step, wherein the N-type source electrode and the N-type drain electrode are respectively positioned on the first P-type well region and the second P-type well region below the outer parts of the two sides of the grid electrode; wherein the first P-type well region completely covers and is connected to the lower surface of the N-type source electrode; wherein the second P-type well region completely covers and is connected to the lower surface of the N-type drain electrode; the first P-type well region and the second P-type well region are provided with a second P-type impurity doping concentration, the second P-type impurity doping concentration is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is enough to prevent leakage current from flowing between the N-type drain current and the P-type substrate when the native NMOS element operates.

In one embodiment, the native NMOS device further comprises: a first P-type pocket region and a second P-type pocket region formed outside the first P-type well region and the second P-type well region respectively under the gate in the P-type epitaxial layer by the same ion implantation process step; the first and second P-type pocket regions have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the third P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-type drain and the N-type source when the native NMOS device is turned off.

In one embodiment, the native NMOS device further comprises: a first N-type lightly doped drain (lightly doped drain, LDD) region and a second N-type lightly doped drain region formed respectively outside the source and the drain under the gate in the P-type epitaxial layer by the same ion implantation process step; the first N-type lightly doped drain region and the second N-type lightly doped drain region are respectively connected with the source electrode and the outer side of the drain electrode under the grid electrode in the P-type epitaxial layer.

In one embodiment, the native NMOS device further comprises: a first N-type lightly doped drain (lightly doped drain, LDD) region and a second N-type lightly doped drain region formed respectively outside the source and the drain under the gate in the P-type epitaxial layer by the same ion implantation process step; the first N-type lightly doped drain region and the second N-type lightly doped drain region are connected to the outer sides of the source electrode and the drain electrode under the grid electrode in the P-type epitaxial layer.

In one embodiment, the P-type epitaxial layer has no N-type region other than the N-type source and the N-type drain in the active region.

In one embodiment, the P-type epitaxial layer has no N-type region other than the N-type source, the N-type drain, the first N-type lightly doped drain region and the second N-type lightly doped drain region in the active region.

In one embodiment, the native NMOS device further comprises: an N-type buried layer formed and connected below the P-type epitaxial layer and completely covering the P-type epitaxial layer in the operation region; and a first N-type isolation region and a second N-type isolation region formed outside the first isolation region and the second isolation region on the N-type buried layer in the P-type epitaxial layer by the same ion implantation process step; wherein neither the first N-type isolation region nor the second N-type isolation region is in the active region.

In one embodiment, when the native NMOS device includes the first N-type lightly doped drain region and the second N-type lightly doped drain region, in the active region, the P-type epitaxial layer has no N-type region except the N-type source, the N-type drain, the first N-type lightly doped drain region, the second N-type lightly doped drain region and the N-type buried layer; when the native NMOS device does not include the first N-type lightly doped drain region and the second N-type lightly doped drain region, the P-type epitaxial layer has no N-type region except the N-type source electrode, the N-type drain electrode and the N-type buried layer in the active region.

In one embodiment, the P-type epitaxial layer has a volume resistivity of 45Ohm-cm.

Compared with the prior art, the native NMOS device and the manufacturing method thereof provided by the invention can prevent leakage current in the on or off operation of the native NMOS device.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.

Drawings

FIG. 1 is a schematic cross-sectional view of a prior art native NMOS device.

Fig. 2 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention.

FIGS. 10A-10K are schematic cross-sectional views illustrating a method of fabricating a native NMOS device according to an embodiment of the present invention.

Description of the symbols in the drawings

10, 20, 30, 40, 50, 60, 70, 80, 90: native NMOS device

11, 21, 31, 41, 51, 61, 71, 81, 91: p-type substrate

21a,31a,41a,51a,61a,71a,81a,91a: upper surface of

21b,31b,41b,51b,61b,71b,81b,91b: lower surface of

22, 32, 42, 52, 62, 72, 82, 92: operating area

13, 23, 33, 43, 53, 63, 73, 83, 93: grid electrode

14, 24, 34, 44, 54, 64, 74, 84, 94: n-type source electrode

15, 25, 35, 45, 55, 65, 75, 85, 95: n-type drain electrode

111, 211, 311, 411, 511, 611, 711, 811, 911: p-type epitaxial layer

112, 212, 312, 412, 512, 612, 712, 812, 912: p-type contact electrode

121, 221, 321, 421, 521, 621, 721, 821, 921: a first insulating region

122, 222, 322, 422, 522, 622, 722, 822, 922: second insulating region

261, 361, 461, 561, 661, 761, 861, 961: first P-type well region

262, 362, 462, 562, 662, 762, 862, 962: second P-type well region

371, 571, 771, 971: first P-type pocket region

372, 572, 772, 972: second P-type pocket region

481, 581, 881, 981: first N-type lightly doped drain region

482, 582, 882, 982: second N-type lightly doped drain region

613, 713, 813, 913: n-type buried layer

Detailed Description

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. The drawings in the present invention are schematic and are mainly intended to represent the process steps and the upper and lower order relationship between the layers, and the shapes, thicknesses and widths are not drawn to scale.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a native NMOS device according to an embodiment of the present invention. As shown in fig. 2, the native NMOS device 20 includes: the P-type epitaxial layer 211, the first insulating region 221, the second insulating region 222, the gate 23, the N-type source 24, the N-type drain 25, the first P-type well 261, the second P-type well 262, and the P-type contact 212.

The P-type epitaxial layer 211 is formed on the P-type substrate 21 and has a P-type conductivity. The P-type epitaxial layer 211 has a first P-type impurity doping concentration. The P-type epitaxial layer 211 has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 2, the same applies hereinafter). The P-type substrate 21 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 211 is formed on the P-type substrate 21, for example, in an epitaxial process. Part of the P-type epitaxial layer 211 is used to provide a conduction current channel for the native NMOS device 20 in a conduction operation.

With continued reference to fig. 2, a first insulating region 221 and a second insulating region 222 are formed on the P-type epitaxial layer 211. The first insulating region 221 and the second insulating region 222 are used to define the operation region 22 between the first insulating region 221 and the second insulating region 222. The first insulating region 221 and the second insulating region 222 are, for example, but not limited to, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 2.

With continued reference to fig. 2, a first P-well 261 and a second P-well 262 are formed in the P-epi layer 211 by the same ion implantation process, and have a P-type conductivity. The gate electrode 23 is formed on the P-type epitaxial layer 221 in the operation region 22. The gate 23 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 21a and connected to the upper surface 21a, which is well known to those skilled in the art, and is not described herein. The N-type source 24 and the N-type drain 25 are formed in the P-type epitaxial layer 211 in the operation region 22 by the same ion implantation process, and the N-type source 24 and the N-type drain 25 are respectively located on the first P-type well region 261 and the second P-type well region 262 below the outer portions of the two sides of the gate 23. The N-type source 24 and the N-type drain 25 are located under the upper surface 21a and connected to the upper surface 21a, and have N-type conductivity. The P-type contact electrode 212 is formed in the P-type epitaxial layer 211, is located below the upper surface 21a and connected to the upper surface 21a, and has a P-type conductivity for serving as an electrical contact between the first P-type well 261, the P-type epitaxial layer 211 and the second P-type well 262.

With continued reference to fig. 2, the first P-well 261 completely covers and is connected to the lower surface of the N-type source 24. The second P-type well region 262 completely covers and is connected to the lower surface of the N-type drain electrode 25. The first P-well 261 and the second P-well 262 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-type drain 25 and the P-type substrate 21 when the native NMOS device 20 is operated.

In one embodiment, the P-type epitaxial layer 211 has a volume resistivity of 45Ohm-cm.

In one embodiment, the P-type epitaxial layer 211 has no N-type region other than the N-type source 24 and the N-type drain 25 in the active region 22.

It should be noted that the upper surface 21a does not refer to a completely flat plane, but refers to one surface of the P-type epitaxial layer 211. In the present embodiment, for example, a portion of the upper surface 21a where the first insulating region 221 contacts the upper surface 21a has a depressed portion. The portion of the upper surface 21a of the second rim region 222 that contacts the upper surface 21a also has a depressed portion.

Note that the gate electrode 23 includes a conductive layer having conductivity, a dielectric layer connected to the upper surface 21a, and a spacer layer having an electrical insulation property, wherein the conductive layer is used as an electrical contact of the gate electrode 23, formed on the dielectric layer and connected to the dielectric layer. Spacers are formed on both sides of the conductive layer to serve as an electrically insulating layer on both sides of the gate electrode 23. This is well known to those skilled in the art and will not be described here in detail.

It should be noted that the aforementioned "N-type" and "P-type" refer to that in the native NMOS device, impurities of different conductivity types are doped in the semiconductor composition region (such as, but not limited to, the aforementioned P-type epitaxial layer 211, the N-type source 24, the N-type drain 25, the first P-type well 261, the second P-type well 262, the P-type contact electrode 212, etc.), so that the semiconductor composition region is N-type or P-type, wherein the N-type and the P-type are electrically opposite to each other.

It should be noted that the native NMOS device refers to a device having a threshold voltage close to zero during normal operation, and provides various applications in circuit design, such as no voltage drop when used as a source follower, no head space (headroom) being sacrificed, and a buffer without dc voltage offset. This is well known to those skilled in the art and will not be described in detail herein.

Fig. 3 shows a schematic cross-sectional view of a native NMOS device 30 according to another embodiment of the present invention. As shown in fig. 3, the native NMOS device 30 includes: the P-type epitaxial layer 311, the first insulating region 321, the second insulating region 322, the gate 33, the N-type source 34, the N-type drain 35, the first P-type well 361, the second P-type well 362, the P-type contact 312, the first P-type pocket 371, and the second P-type pocket 372.

The P-type epitaxial layer 311 is formed on the P-type substrate 31 and has a P-type conductivity. The P-type epitaxial layer 311 has a first P-type impurity doping concentration. The P-type epitaxial layer 311 has an upper surface 31a and a lower surface 31b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 3, the same applies hereinafter). The P-type substrate 31 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 311 is formed on the P-type substrate 31, for example, by an epitaxial process. Part of the P-type epitaxial layer 311 is used to provide a conduction current path for the native NMOS device 30 during a turn-on operation.

With continued reference to fig. 3, a first insulating region 321 and a second insulating region 322 are formed on the P-type epitaxial layer 311. The first insulating region 321 and the second insulating region 322 are used to define the operation region 32 between the first insulating region 321 and the second insulating region 322. The first insulating region 321 and the second insulating region 322 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 3.

With continued reference to fig. 3, the first P-well 361 and the second P-well 362 are formed in the P-epi layer 311 by the same ion implantation process, and have a P-type conductivity. The gate 33 is formed on the P-type epitaxial layer 321 in the operation region 32. The gate 33 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 31a and connected to the upper surface 31a, which is well known to those skilled in the art and will not be described herein. The N-type source 34 and the N-type drain 35 are formed in the P-type epitaxial layer 311 in the operation region 32 by the same ion implantation process, and the N-type source 34 and the N-type drain 35 are respectively located on the first P-type well region 361 and the second P-type well region 362 below the two sides of the gate 33. The N-type source 34 and the N-type drain 35 are located under the upper surface 31a and connected to the upper surface 31a, and have N-type conductivity. The P-type contact electrode 312 is formed in the P-type epitaxial layer 311, is located below the upper surface 31a and connected to the upper surface 31a, and has a P-type conductivity for serving as an electrical contact between the first P-type well region 361, the P-type epitaxial layer 311 and the second P-type well region 362.

With continued reference to fig. 3, the first P-well 361 completely covers and is connected to the lower surface of the N-source 34. The second P-type well region 362 completely covers and is connected to the lower surface of the N-type drain 35. The first P-well region 361 and the second P-well region 362 each have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and which is sufficient to prevent leakage current from flowing between the N-drain 35 and the P-substrate 31 when the native NMOS device 30 is operated.

The first P-type pocket 371 and the second P-type pocket 372 are formed outside the first P-type well 361 and the second P-type well 362 respectively under the gate 33 in the P-type epitaxial layer 311 by the same ion implantation process. The first P-type pocket 371 and the second P-type pocket 372 have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and is sufficient to prevent leakage current from flowing between the N-type drain 36 and the N-type source 34 when the native NMOS device 30 is turned off.

In one embodiment, P-type epitaxial layer 311 has a volume resistivity of 45Ohm-cm.

In one embodiment, the P-type epitaxial layer 311 has no N-type region other than the N-type source 34 and the N-type drain 35 in the active region 32.

Fig. 4 shows a schematic cross-sectional view of a native NMOS device 40 according to another embodiment of the present invention. As shown in fig. 4, the native NMOS device 40 includes: the P-type epitaxial layer 411, the first insulating region 421, the second insulating region 422, the gate electrode 43, the N-type source electrode 44, the N-type drain electrode 45, the first P-type well region 461, the second P-type well region 462, the P-type contact electrode 412, the first N-type lightly doped drain (lightly doped drain, LDD) region 481, and the second N-type lightly doped drain region 482.

The P-type epitaxial layer 411 is formed on the P-type substrate 41 and has a P-type conductivity. The P-type epitaxial layer 411 has a first P-type impurity doping concentration. The P-type epitaxial layer 411 has an upper surface 41a and a lower surface 41b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 4, the same applies hereinafter). The P-type substrate 41 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 411 is formed on the P-type substrate 41, for example, by an epitaxial process. Part of the P-type epitaxial layer 411 is used to provide a conduction current path for the native NMOS device 40 during a turn-on operation.

With continued reference to fig. 4, a first insulating region 421 and a second insulating region 422 are formed on the P-type epitaxial layer 411. The first insulating region 421 and the second insulating region 422 are used to define the operation region 42 between the first insulating region 421 and the second insulating region 422. The first insulating region 421 and the second insulating region 422 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 4.

With continued reference to fig. 4, a first P-well 461 and a second P-well 462 are formed in the P-epi 411 by the same ion implantation process, and have a P-conductivity type. The gate electrode 43 is formed on the P-type epitaxial layer 421 in the operation region 42. The gate 43 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 41a and connected to the upper surface 41a, which is well known to those skilled in the art, and is not described herein. The N-type source 44 and the N-type drain 45 are formed in the P-type epitaxial layer 411 in the operation region 42 by the same ion implantation process, and the N-type source 44 and the N-type drain 45 are respectively located on the first P-type well 461 and the second P-type well 462 outside and below the two sides of the gate 43. The N-type source 44 and the N-type drain 45 are located under the upper surface 41a and connected to the upper surface 41a, and have N-type conductivity. The P-type contact 412 is formed in the P-type epitaxial layer 411, is located below the upper surface 41a and connected to the upper surface 41a, and has a P-type conductivity to serve as an electrical contact between the first P-type well 461, the P-type epitaxial layer 411 and the second P-type well 462.

With continued reference to fig. 4, the first P-well 461 completely covers and is connected to the lower surface of the N-source 44. The second P-type well 462 completely covers and is connected to the lower surface of the N-type drain 45. The first P-well 461 and the second P-well 462 each have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and which is sufficient to prevent leakage current from flowing between the N-drain 45 and the P-substrate 41 when the native NMOS device 40 is operated.

The first N-type lightly doped drain region 481 and the second N-type lightly doped drain region 482 are formed outside the source 44 and the drain 45 respectively under the gate 43 in the P-type epitaxial layer 411 by the same ion implantation process step. The first and second N-type lightly doped drain regions 481 and 482 are connected to the outsides of the source 44 and the drain 45, respectively, of the P-type epitaxial layer 411, which are directly under the gate 43. The first and second N-type lightly doped drain regions 481 and 482 serve to attenuate the drain 45 electric field to improve hot electron injection (hot carrier injection, HCI) effect.

In one embodiment, the P-type epitaxial layer 411 has a volume resistivity of 45Ohm-cm.

In one embodiment, in the active region 42, the P-type epitaxial layer 411 has no N-type region except for the N-type source 44, the N-type drain 45, the first N-type lightly doped drain region 481, and the second N-type lightly doped drain region 482.

Fig. 5 shows a schematic cross-sectional view of a native NMOS device 50, according to another embodiment of the present invention. As shown in fig. 5, the native NMOS device 50 includes: the P-type epitaxial layer 511, the first insulating region 521, the second insulating region 522, the gate 53, the N-type source 54, the N-type drain 55, the first P-type well region 561, the second P-type well region 562, the P-type contact 512, the first P-type pocket region 571, the second P-type pocket region 572, the first N-type lightly doped drain (lightly doped drain, LDD) region 581, and the second N-type lightly doped drain region 582.

The P-type epitaxial layer 511 is formed on the P-type substrate 51 and has a P-type conductivity. The P-type epitaxial layer 511 has a first P-type impurity doping concentration. The P-type epitaxial layer 511 has an upper surface 51a and a lower surface 51b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 5, the same applies hereinafter). The P-type substrate 51 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 511 is formed on the P-type substrate 51, for example, in an epitaxial process. Part of the P-type epitaxial layer 511 is used to provide a conduction current path for the native NMOS device 50 during a turn-on operation.

With continued reference to fig. 5, a first insulating region 521 and a second insulating region 522 are formed on the P-type epitaxial layer 511. The first insulating region 521 and the second insulating region 522 are used to define the operation region 52 between the first insulating region 521 and the second insulating region 522. The first insulating region 521 and the second insulating region 522 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 5.

With continued reference to fig. 5, a first P-well 561 and a second P-well 562 are formed in the P-epi 511 by the same ion implantation process, and have a P-conductivity type. Gate 53 is formed on P-type epitaxial layer 521 in operative region 52. The gate 53 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 51a and connected to the upper surface 51a, which is well known to those skilled in the art, and is not described herein. The N-type source 54 and the N-type drain 55 are formed in the P-type epitaxial layer 511 in the operation region 52 by the same ion implantation process, and the N-type source 54 and the N-type drain 55 are respectively located on the first P-type well region 561 and the second P-type well region 562 outside and below the two sides of the gate 53. The N-type source 54 and the N-type drain 55 are located under the upper surface 51a and connected to the upper surface 51a, and have N-type conductivity. The P-type contact electrode 512 is formed in the P-type epitaxial layer 511, is located below the upper surface 51a and connected to the upper surface 51a, and has a P-type conductivity for serving as an electrical contact between the first P-type well region 561, the P-type epitaxial layer 511 and the second P-type well region 562.

With continued reference to fig. 5, the first P-well 561 completely covers and is connected to the lower surface of the N-source 54. The second P-type well region 562 completely covers and is connected to the lower surface of the N-type drain electrode 55. The first P-well 561 and the second P-well 562 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-drain 55 and the P-substrate 51 when the native NMOS device 50 is operated.

The first P-type pocket region 571 and the second P-type pocket region 572 are formed outside the first P-type well region 561 and the second P-type well region 562, respectively, under the gate 53 in the P-type epitaxial layer 511 by the same ion implantation process. The first P-type pocket 571 and the second P-type pocket 572 have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and which is sufficient to prevent leakage current from flowing between the N-type drain 56 and the N-type source 54 when the native NMOS device 50 is turned off.

The first N-type lightly doped drain region 581 and the second N-type lightly doped drain region 582 are formed at the outer sides of the source 54 and the drain 55 directly under the gate 53 in the P-type epitaxial layer 511 by the same ion implantation process step, respectively. The first and second N-type lightly doped drain regions 581 and 582 are respectively connected to the outer sides of the source 54 and the drain 55 under the gate 53 in the P-type epitaxial layer 511. The first and second N-type lightly doped drain regions 581 and 582 serve to attenuate the electric field of the drain 55 to improve the hot electron injection (hot carrier injection, HCI) effect.

In one embodiment, the P-type epitaxial layer 511 has a volume resistivity of 45Ohm-cm.

In one embodiment, in the active region 52, the P-type epitaxial layer 511 has no N-type region other than the N-type source 54, the N-type drain 55, the first N-type lightly doped drain region 581, and the second N-type lightly doped drain region 582.

Fig. 6 shows a schematic cross-sectional view of a native NMOS device 60 according to another embodiment of the present invention. As shown in fig. 6, the native NMOS device 60 includes: the P-type epitaxial layer 611, the N-type buried layer 613, the first insulating region 621, the second insulating region 622, the gate 63, the N-type source 64, the N-type drain 65, the first P-type well 661, the second P-type well 662, the P-type contact 612, the first N-type isolation region 691, and the second N-type isolation region 692.

The P-type epitaxial layer 611 is formed on the P-type substrate 61 and has a P-type conductivity. The P-type epitaxial layer 611 has a first P-type impurity doping concentration. The P-type epitaxial layer 611 has opposite upper and lower surfaces 61a and 61b in a vertical direction (as indicated by the solid arrow in fig. 6, the following description). The P-type substrate 61 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 611 is formed on the P-type substrate 61, for example, in an epitaxial step. The portion of the P-type epitaxial layer 611 is used to provide a conduction current path for the native NMOS device 60 during a turn-on operation.

An N-type buried layer 613 is formed and connected below the P-type epitaxial layer 611 and completely covers the P-type epitaxial layer 611 in the operation region 62.

With continued reference to fig. 6, a first insulating region 621 and a second insulating region 622 are formed on the P-type epitaxial layer 611. The first insulating region 621 and the second insulating region 622 are used to define the operation region 62 between the first insulating region 621 and the second insulating region 622. The first insulating region 621 and the second insulating region 622 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 6.

With continued reference to fig. 6, the first P-well 661 and the second P-well 662 are formed in the P-epi layer 611 by the same ion implantation process, and have a P-conductivity type. The gate electrode 63 is formed on the P-type epitaxial layer 621 in the operation region 62. The gate 63 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 61a and connected to the upper surface 61a, which is well known to those skilled in the art and will not be described herein. The N-type source 64 and the N-type drain 65 are formed in the P-type epitaxial layer 611 in the operation region 62 by the same ion implantation process, and the N-type source 64 and the N-type drain 65 are respectively located on the first P-type well 661 and the second P-type well 662 outside and below the two sides of the gate 63. The N-type source 64 and the N-type drain 65 are located under the upper surface 61a and connected to the upper surface 61a, and have N-type conductivity. The P-type contact electrode 612 is formed in the P-type epitaxial layer 611, is located below the upper surface 61a and connected to the upper surface 61a, and has a P-type conductivity for serving as an electrical contact between the first P-type well 661, the P-type epitaxial layer 611 and the second P-type well 662.

With continued reference to fig. 6, the first P-well 661 completely covers and is connected to the lower surface of the N-type source 64. The second P-type well region 662 completely covers and is connected to the lower surface of the N-type drain electrode 65. The first P-well 661 and the second P-well 662 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-drain 65 and the P-substrate 61 when the native NMOS device 60 is operated.

The first N-type isolation region 691 and the second N-type isolation region 692 are formed outside the first insulating region 621 and the second insulating region 622 on the N-type buried layer 613 in the P-type epitaxial layer 611 by the same ion implantation process step. Neither the first N-type isolation region 691 nor the second N-type isolation region 692 is in the active region 62. The N-buried layer 613, the first N-type isolation region 691, and the second N-type isolation region 692 form isolation regions in the P-type epitaxial layer 611 that completely encapsulate the handle region 62 for electrically isolating the native NMOS device 60 from other semiconductor devices formed in the P-type epitaxial layer 611.

In one embodiment, the P-type epitaxial layer 611 has a volume resistivity of 45Ohm-cm.

In one embodiment, the P-type epitaxial layer 611 has no N-type region in the active region 62 other than the N-type source 64 and the N-type drain 65.

Fig. 7 shows a schematic cross-sectional view of a native NMOS device 70 according to another embodiment of the present invention. As shown in fig. 7, the native NMOS device 70 includes: the P-type epitaxial layer 711, the N-type buried layer 713, the first insulating region 721, the second insulating region 722, the gate 73, the N-type source 74, the N-type drain 75, the first P-type well 761, the second P-type well 762, the P-type contact 712, the first N-type isolation 791, the second N-type isolation 792, the first P-type pocket 771, and the second P-type pocket 772.

The P-type epitaxial layer 711 is formed on the P-type substrate 71 and has a P-type conductivity. The P-type epitaxial layer 711 has a first P-type impurity doping concentration. The P-type epitaxial layer 711 has an upper surface 71a and a lower surface 71b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 7, the same applies hereinafter). The P-type substrate 71 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 711 is formed on the P-type substrate 71, for example, by an epitaxial process. A portion of the P-type epitaxial layer 711 is used to provide a conduction current path for the native NMOS device 70 during a turn-on operation.

An N-type buried layer 713 is formed and connected under the P-type epitaxial layer 711 and completely covers the P-type epitaxial layer 711 in the operation region 72.

With continued reference to fig. 7, a first insulating region 721 and a second insulating region 722 are formed on the P-type epitaxial layer 711. The first insulating region 721 and the second insulating region 722 are used to define the operation region 72 between the first insulating region 721 and the second insulating region 722. The first insulating region 721 and the second insulating region 722 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 7.

With continued reference to fig. 7, a first P-well 761 and a second P-well 762 are formed in the P-epi layer 711 by the same ion implantation process, and have a P-type conductivity. The gate 73 is formed on the P-type epitaxial layer 721 in the operation region 72. The gate 73 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 71a and connected to the upper surface 71a, which is well known to those skilled in the art, and is not described herein. The N-type source 74 and the N-type drain 75 are formed in the P-type epitaxial layer 711 in the operation region 72 by the same ion implantation process, and the N-type source 74 and the N-type drain 75 are respectively located on the first P-type well 761 and the second P-type well 762 outside and below the two sides of the gate 73. The N-type source 74 and the N-type drain 75 are located below the upper surface 71a and connected to the upper surface 71a, and have N-type conductivity. The P-type contact electrode 712 is formed in the P-type epitaxial layer 711, is located below the upper surface 71a and connected to the upper surface 71a, and has a P-type conductivity for serving as an electrical contact between the first P-type well 761, the P-type epitaxial layer 711 and the second P-type well 762.

With continued reference to fig. 7, the first P-well 761 completely covers and is connected to the lower surface of the N-source 74. The second P-type well region 762 completely covers and is connected to the lower surface of the N-type drain electrode 75. The first P-well 761 and the second P-well 762 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-type drain 75 and the P-type substrate 71 when the native NMOS device 70 is operated.

The first N-type isolation region 791 and the second N-type isolation region 792 are formed outside the first insulating region 721 and the second insulating region 722 on the N-type buried layer 713 in the P-type epitaxial layer 711 by the same ion implantation process step. Neither the first N-type isolation region 791 nor the second N-type isolation region 792 is in the active region 72. The N-buried layer 713, the first N-type isolation region 791 and the second N-type isolation region 792 form an isolation region in the P-type epitaxial layer 711 that completely encapsulates the handle region 72 for electrically isolating the native NMOS device 70 from other semiconductor devices formed in the P-type epitaxial layer 711.

The first P-type pocket 771 and the second P-type pocket 772 are formed outside the first P-type well 761 and the second P-type well 762 respectively under the gate 73 in the P-type epitaxial layer 711 by the same ion implantation process. The first P-type pocket 771 and the second P-type pocket 772 have a third P-type impurity doping concentration that is higher than the first P-type impurity doping concentration, and the third P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-type drain 76 and the N-type source 74 when the native NMOS device 70 is turned off.

In one embodiment, P-type epitaxial layer 711 has a volume resistivity of 45Ohm-cm.

In one embodiment, P-type epitaxial layer 711 has no N-type region in active region 72 other than N-type source 74 and N-type drain 75.

Fig. 8 shows a schematic cross-sectional view of a native NMOS device 80, according to another embodiment of the present invention. As shown in fig. 8, the native NMOS device 80 includes: the P-type epitaxial layer 811, the N-type buried layer 813, the first insulating region 821, the second insulating region 822, the gate 83, the N-type source 84, the N-type drain 85, the first P-type well region 861, the second P-type well region 862, the P-type contact 812, the first N-type lightly doped drain (lightly doped drain, LDD) region 881, the second N-type lightly doped drain region 882, the first N-type isolation region 891, and the second N-type isolation region 892.

A P-type epitaxial layer 811 is formed on the P-type substrate 81 and has a P-type conductivity. The P-type epitaxial layer 811 has a first P-type impurity doping concentration. The P-type epitaxial layer 811 has an upper surface 81a and a lower surface 81b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 8, the same applies hereinafter). The P-type substrate 81 is, for example and without limitation, a P-type or N-type semiconductor P-type substrate. The P-type epitaxial layer 811 is formed on the P-type substrate 81, for example, by an epitaxial process. A portion of the P-type epitaxial layer 811 is used to provide a conduction current path for the native NMOS device 80 during a turn-on operation.

An N-type buried layer 813 is formed and connected below the P-type epitaxial layer 811 and completely covers the P-type epitaxial layer 811 in the operation region 82.

With continued reference to fig. 8, a first insulating region 821 and a second insulating region 822 are formed on the P-type epitaxial layer 811. The first insulating region 821 and the second insulating region 822 are used to define the operation region 82 between the first insulating region 821 and the second insulating region 822. The first isolation region 821 and the second isolation region 822 are, for example and without limitation, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 8.

With continued reference to fig. 8, a first P-well 861 and a second P-well 862 are formed in the P-epi layer 811 by the same ion implantation process, and have P-conductivity. A gate 83 is formed on the P-type epitaxial layer 821 in the operation region 82. The gate 83 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 81a and connected to the upper surface 81a, which is well known to those skilled in the art, and is not described herein. The N-type source 84 and the N-type drain 85 are formed in the P-type epitaxial layer 811 in the operation region 82 by the same ion implantation process, and the N-type source 84 and the N-type drain 85 are respectively located on the first P-type well 861 and the second P-type well 862 outside and below the two sides of the gate 83. The N-type source 84 and the N-type drain 85 are located under the upper surface 81a and connected to the upper surface 81a, and have N-type conductivity. The P-type contact electrode 812 is formed in the P-type epitaxial layer 811, is located below the upper surface 81a and is connected to the upper surface 81a, and has a P-type conductivity for serving as an electrical contact between the first P-type well 861, the P-type epitaxial layer 811 and the second P-type well 862.

With continued reference to fig. 8, the first P-well 861 completely covers and is connected to the bottom surface of the N-source 84. The second P-type well region 862 completely covers and is connected to the lower surface of the N-type drain electrode 85. The first P-well 861 and the second P-well 862 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-drain 85 and the P-substrate 81 when the native NMOS device 80 is operated.

The first N-type isolation region 891 and the second N-type isolation region 892 are formed outside the first isolation region 821 and the second isolation region 822 on the N-type buried layer 813 in the P-type epitaxial layer 811 by the same ion implantation process step. Neither the first N-type isolation region 891 nor the second N-type isolation region 892 is in the active region 82. The N-buried layer 813, the first N-type isolation region 891 and the second N-type isolation region 892 form isolation regions in the P-type epitaxial layer 811 that completely encapsulate the handle region 82, so as to electrically isolate the native NMOS device 80 from other semiconductor devices formed in the P-type epitaxial layer 811.

The first N-type lightly doped drain region 881 and the second N-type lightly doped drain region 882 are formed at the outer sides of the source 84 and the drain 85 respectively under the gate 83 in the P-type epitaxial layer 811 by the same ion implantation process. The first and second N-type lightly doped drain regions 881 and 882 are connected to the outer sides of the source 84 and the drain 85, respectively, of the P-type epitaxial layer 811 directly under the gate 83. The first and second N-type lightly doped drain regions 881 and 882 serve to attenuate the drain 85 electric field to improve hot electron injection (hot carrier injection, HCI) effects.

In one embodiment, the P-type epitaxial layer 811 has a volume resistivity of 45Ohm-cm.

In one embodiment, in the active region 82, the P-type epitaxial layer 811 has no N-type region except for the N-type source 84, the N-type drain 85, the first N-type lightly doped drain region 881, and the second N-type lightly doped drain region 882.

Fig. 9 shows a schematic cross-sectional view of a native NMOS device 90, according to another embodiment of the present invention. As shown in fig. 9, the native NMOS device 90 includes: the P-type epitaxial layer 911, the first insulating region 921, the second insulating region 922, the gate 93, the N-type source 94, the N-type drain 95, the first P-type well region 961, the second P-type well region 962, the P-type contact 912, the first P-type pocket region 971, the second P-type pocket region 972, the first N-type lightly doped drain (lightly doped drain, LDD) region 981, and the second N-type lightly doped drain region 982.

The P-type epitaxial layer 911 is formed on the P-type substrate 91 and has a P-type conductivity. The P-type epitaxial layer 911 has a first P-type impurity doping concentration. The P-type epitaxial layer 911 has opposite upper and lower surfaces 91a and 91b in a vertical direction (as indicated by the solid arrow in fig. 9, the same applies). The P-type substrate 91 is, for example and without limitation, a P-type semiconductor substrate. The P-type epitaxial layer 911 is formed on the P-type substrate 91, for example, by an epitaxial process. A portion of the P-type epitaxial layer 911 is used to provide a conduction current path for the native NMOS device 90 during a turn-on operation.

With continued reference to fig. 9, a first insulating region 921 and a second insulating region 922 are formed on the P-type epitaxial layer 911. The first insulating region 921 and the second insulating region 922 are used to define the operation region 92 between the first insulating region 921 and the second insulating region 922. The first insulating region 921 and the second insulating region 922 are, for example but not limited to, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 9.

With continued reference to fig. 9, a first P-well 961 and a second P-well 962 are formed in the P-epitaxial layer 911 by the same ion implantation process, and have a P-type conductivity. The gate 93 is formed on the P-type epitaxial layer 921 in the operation region 92. The gate 93 includes a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 91a and connected to the upper surface 91a, which is well known to those skilled in the art, and is not described herein. The N-type source 94 and the N-type drain 95 are formed in the P-type epitaxial layer 911 in the operation region 92 by the same ion implantation process, and the N-type source 94 and the N-type drain 95 are respectively located on the first P-type well region 961 and the second P-type well region 962 outside and below both sides of the gate 93. The N-type source 94 and the N-type drain 95 are located under the upper surface 91a and connected to the upper surface 91a, and have N-type conductivity. The P-type contact electrode 912 is formed in the P-type epitaxial layer 911, is located below the upper surface 91a and connected to the upper surface 91a, and has a P-type conductivity for serving as an electrical contact between the first P-type well 961, the P-type epitaxial layer 911 and the second P-type well 962.

With continued reference to fig. 9, the first P-well 961 completely covers and is connected to the lower surface of the N-source 94. The second P-well 962 completely covers and is connected to the bottom surface of the N-drain 95. The first P-well 961 and the second P-well 962 have a second P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-drain 95 and the P-substrate 91 when the native NMOS device 90 is operated.

The first N-type isolation region 991 and the second N-type isolation region 992 are formed outside the first insulating region 921 and the second insulating region 922 on the N-type buried layer 913 in the P-type epitaxial layer 911 in the same ion implantation process step. Neither the first N-type isolation region 991 nor the second N-type isolation region 992 is in the active region 92. The N-buried layer 913, the first N-type isolation region 991, and the second N-type isolation region 992 form isolation regions in the P-type epitaxial layer 911 that completely encapsulate the handle region 92, for electrically isolating the native NMOS device 90 from other semiconductor devices formed in the P-type epitaxial layer 911.

The first P-type pocket 971 and the second P-type pocket 972 are formed outside the first P-type well 961 and the second P-type well 962, respectively, under the gate 93 in the P-type epitaxial layer 911 by the same ion implantation process. The first P-type pocket 971 and the second P-type pocket 972 have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and which is sufficient to prevent leakage current from flowing between the N-type drain 96 and the N-type source 94 when the native NMOS device 90 is turned off.

The first N-type lightly doped drain region 981 and the second N-type lightly doped drain region 982 are formed outside the source 94 and the drain 95, respectively, under the gate 93 in the P-type epitaxial layer 911 by the same ion implantation process step. The first N-type lightly doped drain region 981 and the second N-type lightly doped drain region 982 are respectively connected to the outer sides of the source 94 and the drain 95 under the gate 93 in the P-type epitaxial layer 911. The first and second N-type lightly doped drain regions 981 and 982 are used to attenuate the drain 95 electric field to improve hot electron injection (hot carrier injection, HCI) effects.

In one embodiment, the P-type epitaxial layer 911 has a volume resistivity of 45Ohm-cm.

In one embodiment, in the active region 92, the P-type epitaxial layer 911 has no N-type region except for the N-type source 94, the N-type drain 95, the first N-type lightly doped drain region 981 and the second N-type lightly doped drain region 982.

Referring to fig. 10A-10K, a method for fabricating a native NMOS device 90 is shown according to an embodiment of the present invention. As shown in fig. 10A, a P-type substrate 91 is first provided. Next, as shown in fig. 10B, N-type conductive impurities, such as but not limited to, in the form of accelerated ions, are implanted into the P-type substrate 91, and the N-type buried layer 913 is formed by thermal diffusion during or after the subsequent formation of the P-type epitaxial layer 911 (as shown in fig. 10C).

Next, referring to fig. 10C, a P-type epitaxial layer 911 is formed on the P-type substrate 91. The P-type epitaxial layer 911 is formed on the P-type substrate 91, for example, by an epitaxial process. As described above, the N-type buried layer 913 is formed in a thermally diffused manner during or after the formation of the P-type epitaxial layer 911. The P-type epitaxial layer 911 has a first P-type impurity doping concentration. The P-type epitaxial layer 911 has opposite upper and lower surfaces 91a and 91b in a vertical direction (as indicated by the solid arrow in fig. 10C, the same applies). The P-type substrate 91 is, for example and without limitation, a P-type semiconductor substrate. A portion of the P-type epitaxial layer 911 is used to provide a conduction current path for the native NMOS device 90 during a turn-on operation.

Next, referring to fig. 10D, for example, the first N-type isolation region 991 and the second N-type isolation region 992 are formed outside the first isolation region 921 and the second isolation region 922 (formed later) on the N-type buried layer 913 in the P-type epitaxial layer 911 by the same ion implantation process step. Neither the first N-type isolation region 991 nor the second N-type isolation region 992 is in the active region 92. The N-buried layer 913, the first N-type isolation region 991, and the second N-type isolation region 992 form isolation regions in the P-type epitaxial layer 911 that completely encapsulate the handle region 92, for electrically isolating the native NMOS device 90 from other semiconductor devices formed in the P-type epitaxial layer 911.

Next, referring to fig. 10E, for example, a first P-type well 961 and a second P-type well 962 are formed in the P-type epitaxial layer 911 by the same ion implantation process step, and have P-type conductivity.

Next, referring to fig. 10F, for example, a first insulating region 921 and a second insulating region 922 are formed on the P-type epitaxial layer 911 in the same process step. The first insulating region 921 and the second insulating region 922 are used to define the operation region 92 between the first insulating region 921 and the second insulating region 922. The first insulating region 921 and the second insulating region 922 are, for example but not limited to, shallow trench isolation (shallow trench isolation, STI) structures as shown in fig. 10F.

Next, referring to fig. 10G, a gate 93 is formed on the P-type epitaxial layer 921 in the operation region 92. The gate 93 includes a conductive layer, a spacer layer, and a dielectric layer, wherein the dielectric layer is disposed on the upper surface 91a and connected to the upper surface 91a, and wherein the dielectric layer is disposed on the upper surface 91a and connected to the upper surface 91a, which are well known to those skilled in the art, and are not described herein.

Next, referring to fig. 10H, after the gate 93 is formed, for example, but not limited to, the N-type source 94 and the N-type drain 95 are formed in the P-type epitaxial layer 911 in the operation region 92 by the same ion implantation process, and the N-type source 94 and the N-type drain 95 are respectively located on the first P-type well region 961 and the second P-type well region 962 below the outer portions of the two sides of the gate 93. The N-type source 94 and the N-type drain 95 are located under the upper surface 91a and connected to the upper surface 91a, and have N-type conductivity.

Next, referring to fig. 10I, a P-type contact 912 is formed in the P-type epitaxial layer 911 under the upper surface 91a and connected to the upper surface 91a by an ion implantation process, and has a P-type conductivity for serving as an electrical contact between the first P-type well 961, the P-type epitaxial layer 911 and the second P-type well 962. Wherein the P-type contact 912 adjoins the N-type source 94 in the channel direction.

Next, referring to fig. 10J, a first N-type lightly doped drain region 981 and a second N-type lightly doped drain region 982 are formed by the same ion implantation process step outside the source 94 and the drain 95 directly under the gate 93 in the P-type epitaxial layer 911. The first N-type lightly doped drain region 981 and the second N-type lightly doped drain region 982 are respectively connected to the outer sides of the source 94 and the drain 95 under the gate 93 in the P-type epitaxial layer 911. The first and second N-type lightly doped drain regions 981 and 982 are used to attenuate the drain 95 electric field to improve hot electron injection (hot carrier injection, HCI) effects. In the vertical direction, a first N-type lightly doped drain region 981 and a second N-type lightly doped drain region 982 are formed under the upper surface 91a and connected to the upper surface 11a.

Next, referring to fig. 10K, the first P-type pocket 971 and the second P-type pocket 972 are formed outside the first P-type well 961 and the second P-type well 962 under the gate 93 in the P-type epitaxial layer 911 by the same ion implantation process. The first P-type pocket 971 and the second P-type pocket 972 have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and which is sufficient to prevent leakage current from flowing between the N-type drain 96 and the N-type source 94 when the native NMOS device 90 is turned off.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. Various equivalent changes may be made by those skilled in the art within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, etc., may be added without affecting the main characteristics of the device; as another example, the lithography technique is not limited to a photomask technique, but may also include an electron beam lithography technique. All of which may be analogized in accordance with the teachings of the present invention. Furthermore, the various embodiments described are not limited to single use, but may be used in combination, for example, but not limited to, combining the two embodiments. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations. Furthermore, it is not necessary for any embodiment of the present invention to achieve all of the objects or advantages and, therefore, the scope of the claims should not be limited by any of the claims.

Claims

1. A native NMOS device, comprising:

the P-type epitaxial layer is formed on a P-type substrate and has a first P-type impurity doping concentration;

a first insulating region and a second insulating region formed on the P-type epitaxial layer for defining an operation region between the first insulating region and the second insulating region;

a first P-type well region and a second P-type well region formed in the P-type epitaxial layer by the same ion implantation process step;

a grid electrode formed on the P-type epitaxial layer in the operation region; and

an N-type source electrode and an N-type drain electrode which are formed in the P-type epitaxial layer in the operation region by the same ion implantation process step and are respectively positioned on the first P-type well region and the second P-type well region below the outer parts of the two sides of the grid electrode;

wherein the first P-type well region completely covers and is connected to the lower surface of the N-type source electrode;

wherein the second P-type well region completely covers and is connected to the lower surface of the N-type drain electrode;

the first P-type well region and the second P-type well region are provided with a second P-type impurity doping concentration, the second P-type impurity doping concentration is higher than the first P-type impurity doping concentration, and the second P-type impurity doping concentration is enough to prevent leakage current from flowing between the N-type drain current and the P-type substrate when the native NMOS element operates.

2. The native NMOS device of claim 1, further comprising a first and a second P-type pocket regions formed outside the first and second P-type well regions respectively under the gate in the P-type epitaxial layer by the same ion implantation process step;

the first and second P-type pocket regions have a third P-type impurity doping concentration, which is higher than the first P-type impurity doping concentration, and the third P-type impurity doping concentration is sufficient to prevent leakage current from flowing between the N-type drain and the N-type source when the native NMOS device is turned off.

3. The native NMOS device of claim 1, further comprising a first N-type lightly doped drain region and a second N-type lightly doped drain region formed outside the source and the drain respectively under the gate in the P-type epitaxial layer by a same ion implantation process step;

the first N-type lightly doped drain region and the second N-type lightly doped drain region are respectively connected with the source electrode and the outer side of the drain electrode under the grid electrode in the P-type epitaxial layer.

4. The native NMOS device of claim 2, further comprising a first N-type lightly doped drain region and a second N-type lightly doped drain region formed outside the source and the drain respectively under the gate in the P-type epitaxial layer by the same ion implantation process step;

The first N-type lightly doped drain region and the second N-type lightly doped drain region are connected to the outer sides of the source electrode and the drain electrode under the grid electrode in the P-type epitaxial layer.

5. The native NMOS device of claim 1, wherein in the active region, there is no N-type region in the P-type epitaxial layer other than the N-type source and the N-type drain.

6. The native NMOS device of any one of claims 3-4, wherein in the active region, there is no N-type region in the P-type epitaxial layer other than the N-type source, the N-type drain, the first N-type lightly doped drain region, and the second N-type lightly doped drain region.

7. The native NMOS device of any one of claims 1 to 4, further comprising:

an N-type buried layer formed and connected below the P-type epitaxial layer and completely covering the P-type epitaxial layer in the operation region; and

a first N-type isolation region and a second N-type isolation region formed outside the first isolation region and the second isolation region on the N-type buried layer in the P-type epitaxial layer by the same ion implantation process step;

wherein neither the first N-type isolation region nor the second N-type isolation region is in the active region.

8. The native NMOS device of claim 7, wherein when said native NMOS device comprises said first N-type lightly doped drain region and said second N-type lightly doped drain region, no N-type region is present in said P-type epitaxial layer except for said N-type source, said N-type drain, said first N-type lightly doped drain region, said second N-type lightly doped drain region and said N-type buried layer in said active region;

when the native NMOS device does not include the first N-type lightly doped drain region and the second N-type lightly doped drain region, the P-type epitaxial layer has no N-type region except the N-type source electrode, the N-type drain electrode and the N-type buried layer in the active region.

9. The native NMOS device of claim 1, wherein the P-type epitaxial layer has a volume resistivity of 45Ohm-cm.

10. A method of fabricating a native NMOS device, comprising:

forming a P-type epitaxial layer on a P-type substrate, wherein the P-type epitaxial layer has a first P-type impurity doping concentration;

forming a first insulating region and a second insulating region on the P-type epitaxial layer to define an operating region between the first insulating region and the second insulating region;

forming a first P-type well region and a second P-type well region in the P-type epitaxial layer by using the same ion implantation process step;

Forming a gate on the P-type epitaxial layer in the operation region; and

forming an N-type source electrode and an N-type drain electrode in the P-type epitaxial layer in the operation region respectively by the same ion implantation process step, wherein the N-type source electrode and the N-type drain electrode are respectively positioned on the first P-type well region and the second P-type well region below the outer parts of the two sides of the grid electrode;

11. The method of manufacturing a native NMOS device of claim 10, further comprising:

forming a first P-type pocket region and a second P-type pocket region respectively outside the first P-type well region and the second P-type well region under the grid in the P-type epitaxial layer by the same ion implantation process step;

12. The method of manufacturing a native NMOS device of claim 10, further comprising: forming a first N-type lightly doped drain region and a second N-type lightly doped drain region respectively at the outer sides of the source electrode and the drain electrode under the grid electrode in the P-type epitaxial layer by the same ion implantation process step;

the second N-type lightly doped drain region is connected with the outer sides of the source electrode and the drain electrode under the grid electrode in the P-type epitaxial layer respectively.

13. The method of manufacturing a native NMOS device of claim 11, further comprising: forming a first N-type lightly doped drain region and a second N-type lightly doped drain region respectively at the outer sides of the source electrode and the drain electrode under the grid electrode in the P-type epitaxial layer by the same ion implantation process step;

14. The method of claim 10, wherein the P-type epitaxial layer has no N-type region other than the N-type source and the N-type drain in the active region.

15. The method as claimed in any one of claims 12 to 13, wherein the P-type epitaxial layer has no N-type region in the active region except for the N-type source, the N-type drain, the first N-type lightly doped drain region and the second N-type lightly doped drain region.

16. The method for manufacturing a native NMOS device according to any one of claims 10 to 13, further comprising:

forming an N-type buried layer below the P-type epitaxial layer, and completely covering and connecting the P-type epitaxial layer in the operation region; and

forming a first N-type isolation region and a second N-type isolation region outside the first isolation region and the second isolation region on the N-type buried layer in the P-type epitaxial layer by using the same ion implantation process step;

17. The method of claim 16, wherein when the native NMOS device comprises the first and second N-type lightly doped drain regions, there are no N-type regions in the P-type epitaxial layer except the N-type source, the N-type drain, the first N-type lightly doped drain region, the second N-type lightly doped drain region and the N-type buried layer in the active region;

18. The method of claim 10, wherein the P-type epitaxial layer has a volume resistivity of 45Ohm-cm.