CN117894683A - Super junction VDMOS and manufacturing method thereof - Google Patents
Super junction VDMOS and manufacturing method thereof Download PDFInfo
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- CN117894683A CN117894683A CN202311862235.7A CN202311862235A CN117894683A CN 117894683 A CN117894683 A CN 117894683A CN 202311862235 A CN202311862235 A CN 202311862235A CN 117894683 A CN117894683 A CN 117894683A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 57
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 210000000746 body region Anatomy 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000227 grinding Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000005019 vapor deposition process Methods 0.000 description 4
- 238000000608 laser ablation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 150000004645 aluminates Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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Abstract
The application discloses a super junction VDMOS and a manufacturing method thereof, wherein the method comprises the following steps: forming a first epitaxial layer on a substrate; a first trench formed inside the first epitaxial layer; forming a first conductive column in the first trench; forming a second epitaxial layer above the first epitaxial layer and the first conductive column; forming a second trench extending from the upper surface of the second epitaxial layer to the first trench; forming a second conductive post in the second trench; forming a body region and a source electrode extending from the upper surface of the second conductive column to the inside of the second conductive column, wherein the body region is connected with the second epitaxial layer, and the source electrode is positioned in the body region; and forming a gate structure on the upper surface of the second conductive column, wherein the gate structure comprises a dielectric layer covered on the second conductive column and a gate conductor covered on the dielectric layer, and the gate structure is positioned between the two second conductive columns. The preparation difficulty of the high depth-to-width ratio groove is reduced by a method of etching the epitaxial layer step by step through multiple times of deposition.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a super junction VDMOS and a manufacturing method thereof.
Background
The junction vertical power metal oxide semiconductor field effect transistor (super junction vertical double-diffused metal oxide semiconductor FIELD EFFECT transistor) is a semiconductor switching device applied to the field of medium and high voltage, and has higher voltage resistance and smaller on-resistance than a common VDMOS due to the unique design of alternately arranging P columns and N columns. Has been widely concerned since the advent of the prior art, and has wide application prospect.
However, due to the complexity of the design, the depth-to-width ratio of the trench is too large, and the implementation difficulty and the cost are high in the process, so that a process production flow with low implementation difficulty and low cost is needed.
Disclosure of Invention
The application provides a super junction VDMOS and a manufacturing method thereof, which at least solve the technical problems in the prior art.
According to a first aspect of the present application, there is provided a method of manufacturing a super junction VDMOS, comprising:
Forming a first epitaxial layer on a substrate, wherein the first epitaxial layer is of a first doping type;
forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof;
forming a first conductive column in the first groove, wherein the first conductive column is of a second doping type;
forming a second epitaxial layer positioned above the first epitaxial layer and the first conductive column, wherein the second epitaxial layer is of a first doping type;
Forming second trenches extending from the upper surface of the second epitaxial layer to the first trenches, wherein the second trenches are in one-to-one correspondence with the first trenches and are communicated longitudinally;
forming a second conductive column in the second groove, wherein the second conductive column is of a second doping type, and the first conductive column is connected with the second conductive column;
forming a well region extending from the upper surface of the second conductive column to the inside of the second conductive column, wherein the well region is of a second doping type;
forming a gate structure positioned on the upper surface of the second conductive column, wherein the gate structure comprises a dielectric layer covered on the second epitaxial layer and a gate conductor covered on the dielectric layer, and the gate conductor is positioned between the two second conductive columns;
And forming a source electrode positioned in the well region, wherein the source electrode is of a first doping type.
In an embodiment, the forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof includes:
Forming a first hard mask layer on the first epitaxial layer;
forming a first photoresist layer on the first hard mask layer;
forming a first groove position on the first photoresist layer by adopting a photoetching process;
Etching the first hard mask layer, transferring the first groove position to the first hard mask layer, and removing the first photoresist layer;
the first epitaxial layer is etched along the first trench locations to form a first trench extending from the upper surface of the first epitaxial layer to the interior thereof.
In an embodiment, the forming a first conductive pillar within the first trench includes:
forming the first conductive column in the first groove and on the upper surface of the first hard grinding layer by adopting an epitaxial process;
removing the first conductive column on the upper surface of the first hard grinding layer by adopting a chemical mechanical grinding process;
and removing the first hard grinding layer.
In one embodiment, the forming a second trench extending from the upper surface of the second epitaxial layer to the interior thereof includes:
Forming a second hard mask layer on the second epitaxial layer;
forming a second photoresist layer on the second hard mask layer;
Forming a second groove position on the second photoresist layer by adopting a photoetching process, wherein the second groove position corresponds to each first groove position along the longitudinal direction;
Etching the second hard mask layer, transferring the second groove position to the second hard mask layer, and removing the second photoresist layer;
and etching the second epitaxial layer along the second trench to form a second trench extending from the upper surface of the second epitaxial layer to the inside of the second epitaxial layer.
In an embodiment, the forming a second conductive pillar within the second trench includes:
Forming a second conductive column in the second groove and on the upper surface of the second hard mask layer by adopting an epitaxial process;
Removing the second conductive column on the upper surface of the second hard mask layer by adopting a chemical mechanical polishing process;
and removing the second hard mask layer.
In one embodiment, the forming a well region extending from the upper surface of the second conductive pillar to the inside thereof, the body region being contiguous with the second conductive pillar, includes:
Forming a third photoresist layer on the upper surface of the second epitaxial layer, wherein the third photoresist layer covers the upper surface of the second conductive column at the same time;
Forming a third groove position on the third photoresist layer, wherein the second conductive column is arranged right below the third groove position;
and forming a well region extending from the upper surface of the second conductive column to the inside of the second conductive column through the third groove by adopting an ion implantation process.
In one embodiment, the forming the gate structure on the upper surface of the second conductive pillar includes:
forming the dielectric layer on the second epitaxial layer;
forming a polysilicon layer on the dielectric layer;
Forming a third hard mask layer on the polysilicon layer;
forming a fourth photoresist layer on the third hard mask layer;
Forming a fourth groove position on the fourth photoresist layer by adopting a photoetching process;
Etching the fourth hard mask layer, transferring the fourth groove position to the fourth hard mask layer, and removing the fourth photoresist layer;
Etching the polysilicon layer along the fourth groove position to form a gate conductor positioned on the dielectric layer;
And removing the fourth hard mask layer.
In one embodiment, the forming the source electrode in the well region includes;
Forming a fifth photoresist layer on the upper surface of the gate structure and the upper surface of the second epitaxial layer;
forming a fifth groove position on the fifth photoresist layer by adopting a photoetching process;
and forming a source electrode in the well region through the fifth groove position by adopting an ion implantation process.
According to a second aspect of the present application, there is provided a superjunction VDMOS comprising:
A substrate;
the epitaxial layer is positioned on the upper surface of the substrate, a groove is formed in the epitaxial layer, and the epitaxial layer is of a first doping type;
The conductive column is positioned in the groove and is of a second doping type;
The well region extends downwards from the upper surface of the epitaxial layer to the inside of the well region, the well region is connected with the epitaxial layer, and the source electrode is positioned in the body region;
The grid structure is positioned on the upper surface of the epitaxial layer and comprises a dielectric layer covered on the epitaxial layer and a grid conductor covered on the dielectric layer, and the grid conductor is positioned between the two conductive columns.
In one embodiment, the epitaxial layer is configured to be doped with boron at a doping concentration of 5×10 15cm-3.
According to the super-junction VDMOS and the manufacturing method thereof, the preparation difficulty of the high-aspect-ratio groove is reduced by a method of multi-time deposition epitaxial layer step etching.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 shows a cross-sectional view of a superjunction VDMOS of an embodiment of the present application;
FIGS. 2 a-2 h are cross-sectional views of stages in a method of manufacturing a superjunction VDMOS in an embodiment of the application; wherein,
FIG. 2a illustrates a schematic cross-sectional view after forming a first trench location in an embodiment of the present application;
FIG. 2b illustrates a schematic cross-sectional view after forming a first trench in an embodiment of the application;
Fig. 2c illustrates a schematic cross-sectional view after forming a first conductive pillar in a first trench in an embodiment of the application;
Figure 2d schematically illustrates a cross-sectional view after forming a second epitaxial layer in an embodiment of the present application;
FIG. 2e illustrates a schematic cross-sectional view after forming a second trench location in an embodiment of the present application;
FIG. 2f illustrates a schematic cross-sectional view after forming a second trench in an embodiment of the present application;
FIG. 2g schematically illustrates a cross-sectional view after forming a well region in an embodiment of the present application;
FIG. 2h schematically illustrates a cross-sectional view after forming a gate structure in an embodiment of the present application;
Fig. 2i schematically shows a cross-sectional view after forming a source in an embodiment of the application.
Part number description:
101-a substrate;
102-an epitaxial layer;
1021-a first epitaxial layer;
1022-a second epitaxial layer;
103-grooves;
1031-a first trench;
1032-a second trench;
104-a well region;
105-source;
106-a gate conductor;
107-a dielectric layer;
201-a first hard mask layer;
202-a first photoresist layer;
203-a second hard mask layer;
204-a second photoresist layer;
301-conductive pillars;
3011-a first conductive post;
3012-a second conductive post;
401-a first trench location;
402-second trench location.
Detailed Description
When describing the structure of a device, when a layer, an area, is referred to as being "on" or "over" another layer, another area, it can be directly on the other layer, another area, or other layers or areas can be included between the layer, another area, and the other layer, another area. If the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art.
For example, materials that may be used for the substrate include: si, al2O3, siC, or the like.
The epitaxial layer may use the same or different materials as the substrate as required. If the epitaxial layer material is the same as the substrate material, such an epitaxial layer is referred to as a homoepitaxial layer. Such an epitaxial layer is referred to as a heteroepitaxial layer if the material of the epitaxial layer is different from that of the substrate. In an embodiment of the application, the epitaxial layer is a homoepitaxial layer.
Materials that may be used for the dielectric layer include any material that can form an interface with the epitaxial layer. For example, when the epitaxial layer is Si, the dielectric layer may be formed of SiO 2, or a material having a dielectric constant greater than SiO 2, including, for example, oxides, nitrides, oxynitrides, si-ates, aluminates, titanates, and the like.
The materials of the respective components may be not only materials known to those skilled in the art, but also new materials developed in the future for the components or the functions described above may be used.
Fig. 1 shows a cross-sectional view of a superjunction VDMOS of an embodiment of the present application. In the present application, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. An N-type semiconductor layer may be formed by implanting an N-type dopant, such as P, as, into the semiconductor layer. A P-type semiconductor layer may be formed by doping a P-type dopant, such as B, into the semiconductor layer.
As shown in fig. 1, the super junction VDMOS includes a substrate 101 and an epitaxial layer 102, and the epitaxial layer 102 is located on the upper surface of the substrate 101. The substrate 101 serves as a drain region of the superjunction VDMOS of a first doping type, in one embodiment heavily N-doped. Epitaxial layer 102 is N-doped with respect to substrate 101, i.e., epitaxial layer 101 is lightly doped with respect to substrate 101. Illustratively, the epitaxial layer 102 of the embodiments of the present disclosure is formed by two epitaxial growth processes from below and above, and may include a first epitaxial layer 1021 and a second epitaxial layer 1022 located above the first epitaxial layer 1021, respectively.
The superjunction VDMOS further comprises a trench 103 in the epitaxial layer 102. The trench 103 extends from the upper surface of the epitaxial layer 102 to the inside of the epitaxial layer 102 and terminates in the epitaxial layer 102. The number of trenches 103 provided in the epitaxial layer 102 may be dependent on the actual situation. In one embodiment, there are 4 trenches 103, and each trench 103 has the same structure. For example, corresponding to the two growth processes of the epitaxial layer 102, each trench 103 in the embodiments of the disclosure may be formed by two etching processes, including a first trench 1031 etched in the first epitaxial layer 1021 and a second trench 1032 etched in the second epitaxial layer 1022.
The superjunction VDMOS further includes a conductive pillar 301, the conductive pillar 301 being located within the trench 103. The conductive pillars 301 are second doped, in one embodiment P-doped. Illustratively, the conductive post 301 includes a first conductive post 3011 and a second conductive post 3012 located above the first conductive post 3011. Specifically, the first conductive post 3011 is positioned within the first trench 1031 and the second conductive post 3012 is positioned within the second trench 1032.
The super junction VDMOS further includes a well 104 and a source 105, the source 105 being located within the well 104.
Specifically, the well region 104 extends from the upper surface of the epitaxial layer 102 to the inside thereof, the well region 104 is connected to the conductive pillar 301, and the source 105 is located in the well region 104. Well 104 is of a second doping type, and in one embodiment, the well is doped P-type. The source 105 is of a first doping type, in one embodiment, the source is an N-type doping
The super junction VDMOS further includes a gate structure 106, where the gate structure 106 includes a dielectric layer 1061 covering the top surface of the second epitaxial layer 1021 and a gate conductor 1062 covering the dielectric layer 1061, and the gate structure 106 is located between the two second conductive pillars 3012.
Fig. 2a to 2i are sectional views illustrating stages of a method of manufacturing a super junction VDMOS in an embodiment of the present application. The following describes in detail the method for manufacturing the super junction VDMOS according to the embodiment of the present application with reference to fig. 2a to 2 h.
Fig. 2a is a schematic cross-sectional view of the first epitaxial layer 1021 after the first trench is formed, referring to fig. 2a, in which a first hard mask layer 201 and a first photoresist layer 202 are formed, and a first trench 401 is formed in the first hard mask layer 201 and the first photoresist layer 202. In one embodiment, the material of the substrate 101 may be an N-type monocrystalline silicon substrate.
In this step, a first epitaxial layer 1021 is formed on the substrate 101, the substrate 101 being a drain region of the device having a first doping type. In one embodiment, the substrate 101 is an N-type monocrystalline silicon substrate.
In an embodiment, the first epitaxial layer 1021 may be a homoepitaxial layer or a heteroepitaxial layer. The first epitaxial layer 1021 may be grown using a vapor deposition process. The vapor deposition process may be physical vapor deposition or chemical vapor deposition. Chemical vapor deposition is preferred. Chemical vapor deposition includes low pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, and the like. Physical vapor deposition includes evaporation, sputtering, and the like.
In this step, a first hard mask layer 201 is formed on the first epitaxial layer 1021, and a first photoresist layer 202 is formed on the first hard mask layer 201.
In one embodiment, an oxide layer is oxidized on the upper surface of the first epitaxial layer 1021 by an oxidation process. The oxidation process includes, but is not limited to: at least one of thermal oxidation, chemical vapor deposition, physical vapor deposition, and the like. Preferably a thermal oxidation process. The oxide may be silicon dioxide. The oxide may act as a first hard mask layer 201 (HM). A deposition process is used to form the first photoresist layer 202.
In this step, a first trench 401 is formed in the first hard mask layer 201 and the first photoresist layer 202.
First, the first photoresist layer 202 is patterned using photolithography to form first trench locations 401 on the first photoresist layer 202. Etching the first hard mask layer 201 transfers the first trench locations 401 onto the first hard mask layer 201, removing the first photoresist layer 202.
The etching process may be a wet etching process or a dry etching process. Preferably a dry etching process. The dry etching process includes, but is not limited to, at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation.
Fig. 2b schematically illustrates a cross-sectional view after forming the first trench in an embodiment of the application. Referring to fig. 2b, a first trench 1031 is formed extending from the upper surface of the first epitaxial layer 1021 to the inside thereof.
In this step, the first epitaxial layer 1021 is further etched using the first trench locations 401 on the layer of the first hard mask 201 to form first trenches 1031 extending from the upper surface of the first epitaxial layer 1021 to the inside thereof. Fig. 2c schematically illustrates a cross-sectional view after forming a first conductive pillar in a first trench in an embodiment of the application. Referring to fig. 2c, a first conductive pillar is formed in the first trench.
In this step, an epitaxial process is used to form the first conductive pillars 3011 in the first trenches 1031 and on the upper surface of the first hard mask layer 201. Then, the first hard mask layer 201 and the first conductive post 3011 on the upper surface of the first epitaxial layer 1021 are removed by using a chemical mechanical polishing process, so that the upper surface of the first conductive post 3011 is flush with the first epitaxial layer 1021.
In one embodiment, the first conductive post 3011 is of the second doping type and is doped with boron at a doping concentration of 5×10 15cm-3.
Figure 2d schematically illustrates a cross-sectional view after forming a second epitaxial layer in an embodiment of the present application. Referring to fig. 2d, a second epitaxial layer 1022 is formed on the upper surface of the first epitaxial layer 1021.
In an embodiment, the second epitaxial layer 1022 may be a homoepitaxial layer or a heteroepitaxial layer. A vapor deposition process may be used to grow the second epitaxial layer 1022. The vapor deposition process may be physical vapor deposition or chemical vapor deposition. Chemical vapor deposition is preferred. Chemical vapor deposition includes low pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, and the like. Physical vapor deposition includes evaporation, sputtering, and the like.
Fig. 2e schematically shows a cross-sectional view after forming the second trench locations in an embodiment of the application. Referring to fig. 2e, a second hard mask layer 203 and a second photoresist layer 204 are formed on the second epitaxial layer 1022, and a second trench location 402 is formed in the second hard mask layer 203 and the second photoresist layer 204.
In this step, a second hard mask layer 203 is formed on the second epitaxial layer 1022, and a second photoresist layer 204 is formed on the second hard mask layer 203.
In one embodiment, an oxide layer is oxidized on the top surface of the second epitaxial layer 1022 by an oxidation process. The oxidation process includes, but is not limited to: at least one of thermal oxidation, chemical vapor deposition, physical vapor deposition, and the like. Preferably a thermal oxidation process. The oxide may be silicon dioxide. The oxide may act as a second hard mask layer 203 (HM). A deposition process is used to form a second photoresist layer 204.
In this step, a second trench location 402 is formed in the second hard mask layer 203 and the second photoresist layer 204.
First, the second photoresist layer 204 is patterned using photolithography to form second trench locations 402 on the second photoresist layer 204. Etching the second hard mask layer 203 transfers the second trench locations 402 onto the second hard mask layer 203, removing the second photoresist layer 204.
The etching process may be a wet etching process or a dry etching process. Preferably a dry etching process. The dry etching process includes, but is not limited to, at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation.
Fig. 2f illustrates a schematic cross-sectional view after forming the second trench 1032 in an embodiment of the present application. Referring to fig. 2f, in this step, the second epitaxial layer 1022 is further etched by using the second trench locations 402 on the second hard mask layer 203 to form second trenches 1032 extending from the upper surface of the second epitaxial layer 1022 to the inside thereof, the number of the second trenches 1032 is the same as the number of the first trenches 1031, and each of the first trenches 1031 and the corresponding second trench 1032 are connected thereto in the longitudinal direction.
The etching process may be a wet etching process or a dry etching process. Preferably a dry etching process. The dry etching process includes, but is not limited to, at least one of ion milling etching, plasma etching, reactive ion etching, laser ablation. After the second trenches 1032 are etched, the second photoresist layer 204 is removed.
Fig. 2g schematically illustrates a cross-sectional view after forming a well region in an embodiment of the application. Referring to fig. 2g, a second conductive post 3012 is formed in the second trench 1032, and a well region 104 is formed extending from the upper surface of the second epitaxial layer 1022 into the first second conductive post.
In this step, a third photoresist layer is formed on the upper surface of the second epitaxial layer 1022, then the third photoresist layer is lithographically patterned to form a well pattern on the photoresist layer, and then ion implantation is performed through the well pattern to form the well 104. Well 104 is of a second doping type and in one embodiment well 50 is of a P-type doping.
Fig. 2h schematically illustrates a cross-sectional view after forming a gate structure in an embodiment of the application. Referring to fig. 2h, a dielectric layer 107 is formed over the second epitaxial layer 1022.
Dielectric layer 107 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Vapor Deposition, ALD), or other deposition methods.
The material of dielectric layer 107 includes, but is not limited to, silicon dioxide.
With continued reference to fig. 2h, a plurality of gate conductors 106 are formed on the dielectric layer 107, the gate conductors 106 being located between adjacent conductive pillars 301.
In this step, a polysilicon layer may be formed on the dielectric layer 107, then a third hard mask layer may be formed on the polysilicon layer, and a fourth photoresist layer may be formed on the third hard mask layer. And etching the fourth hard mask layer to transfer the fourth groove position to the fourth hard mask layer, and removing the fourth photoresist layer. Etching the polysilicon layer along the fourth trench position to form a gate conductor 106 located on the dielectric layer 107;
And removing the fourth hard mask layer.
The material of the gate conductor 106 includes, but is not limited to, polysilicon.
Fig. 2i schematically shows a cross-sectional view after forming a source in an embodiment of the application. Referring to fig. 2i, a source 105 is formed in the well 104. In this step, a fifth photoresist layer is formed to cover the gate conductor 106 and the surface of the dielectric layer 107, then the fifth photoresist layer is patterned by photolithography to form a source electrode pattern on the photoresist layer, and then ion implantation is performed using the patterned fifth photoresist layer as a mask to form a source electrode 105. The source 105 is of a first doping type, and in one embodiment, the source 105 is of an N-type doping.
By the respective step schemes shown in fig. 2a to 2i, a superjunction VDMOS as shown in fig. 1 can be obtained. By depositing the epitaxial layer 102 twice, two sections of trenches 103 formed on the upper surface of the epitaxial layer 102 deposited each time by an etching process are penetrated in the longitudinal direction, and the conductive pillars 301 are deposited twice in the two sections of trenches 103. Therefore, the etching depth-width ratio of each etching groove 103 can be kept between 4.5 and 6, and the technical difficulty of etching is greatly relieved.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of manufacturing a superjunction VDMOS, comprising:
Forming a first epitaxial layer on a substrate, wherein the first epitaxial layer is of a first doping type;
forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof;
forming a first conductive column in the first groove, wherein the first conductive column is of a second doping type;
forming a second epitaxial layer positioned above the first epitaxial layer and the first conductive column, wherein the second epitaxial layer is of a first doping type;
Forming second trenches extending from the upper surface of the second epitaxial layer to the first trenches, wherein the second trenches are in one-to-one correspondence with the first trenches and are communicated longitudinally;
forming a second conductive column in the second groove, wherein the second conductive column is of a second doping type, and the first conductive column is connected with the second conductive column;
forming a well region extending from the upper surface of the second conductive column to the inside of the second conductive column, wherein the well region is of a second doping type;
forming a gate structure positioned on the upper surface of the second conductive column, wherein the gate structure comprises a dielectric layer covered on the second epitaxial layer and a gate conductor covered on the dielectric layer, and the gate conductor is positioned between the two second conductive columns;
And forming a source electrode positioned in the well region, wherein the source electrode is of a first doping type.
2. The method of claim 1, wherein the forming a first trench extending from an upper surface of the first epitaxial layer to an interior thereof comprises:
Forming a first hard mask layer on the first epitaxial layer;
forming a first photoresist layer on the first hard mask layer;
forming a first groove position on the first photoresist layer by adopting a photoetching process;
Etching the first hard mask layer, transferring the first groove position to the first hard mask layer, and removing the first photoresist layer;
the first epitaxial layer is etched along the first trench locations to form a first trench extending from the upper surface of the first epitaxial layer to the interior thereof.
3. The method of claim 2, wherein the forming a first conductive pillar within the first trench comprises:
forming the first conductive column in the first groove and on the upper surface of the first hard grinding layer by adopting an epitaxial process;
removing the first conductive column on the upper surface of the first hard grinding layer by adopting a chemical mechanical grinding process;
and removing the first hard grinding layer.
4. The method of claim 1, wherein forming a second trench extending from an upper surface of the second epitaxial layer to an interior thereof comprises:
Forming a second hard mask layer on the second epitaxial layer;
forming a second photoresist layer on the second hard mask layer;
Forming a second groove position on the second photoresist layer by adopting a photoetching process, wherein the second groove position corresponds to each first groove position along the longitudinal direction;
Etching the second hard mask layer, transferring the second groove position to the second hard mask layer, and removing the second photoresist layer;
and etching the second epitaxial layer along the second trench to form a second trench extending from the upper surface of the second epitaxial layer to the inside of the second epitaxial layer.
5. The method of claim 4, wherein the forming a second conductive pillar within the second trench comprises:
Forming a second conductive column in the second groove and on the upper surface of the second hard mask layer by adopting an epitaxial process;
Removing the second conductive column on the upper surface of the second hard mask layer by adopting a chemical mechanical polishing process;
and removing the second hard mask layer.
6. The method of claim 1, wherein forming a well region extending from an upper surface of a second conductive pillar to an interior thereof, the body region interfacing with the second conductive pillar, comprises:
Forming a third photoresist layer on the upper surface of the second epitaxial layer, wherein the third photoresist layer covers the upper surface of the second conductive column at the same time;
Forming a third groove position on the third photoresist layer, wherein the second conductive column is arranged right below the third groove position;
and forming a well region extending from the upper surface of the second conductive column to the inside of the second conductive column through the third groove by adopting an ion implantation process.
7. The method of claim 1, wherein forming a gate structure on an upper surface of the second conductive pillar comprises:
forming the dielectric layer on the second epitaxial layer;
forming a polysilicon layer on the dielectric layer;
Forming a third hard mask layer on the polysilicon layer;
forming a fourth photoresist layer on the third hard mask layer;
Forming a fourth groove position on the fourth photoresist layer by adopting a photoetching process;
Etching the fourth hard mask layer, transferring the fourth groove position to the fourth hard mask layer, and removing the fourth photoresist layer;
Etching the polysilicon layer along the fourth groove position to form a gate conductor positioned on the dielectric layer;
And removing the fourth hard mask layer.
8. The method of claim 7, wherein forming a source within a well region comprises;
Forming a fifth photoresist layer on the upper surface of the gate structure and the upper surface of the second epitaxial layer;
forming a fifth groove position on the fifth photoresist layer by adopting a photoetching process;
and forming a source electrode in the well region through the fifth groove position by adopting an ion implantation process.
9. A superjunction VDMOS comprising:
A substrate;
the epitaxial layer is positioned on the upper surface of the substrate, a groove is formed in the epitaxial layer, and the epitaxial layer is of a first doping type;
The conductive column is positioned in the groove and is of a second doping type;
The well region extends downwards from the upper surface of the epitaxial layer to the inside of the well region, the well region is connected with the epitaxial layer, and the source electrode is positioned in the body region;
The grid structure is positioned on the upper surface of the epitaxial layer and comprises a dielectric layer covered on the epitaxial layer and a grid conductor covered on the dielectric layer, and the grid conductor is positioned between the two conductive columns.
10. The super junction VDMOS of claim 8, wherein the epitaxial layer is configured to be doped with boron at a doping concentration of 5 x 10 15cm-3.
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| CN202311862235.7A CN117894683A (en) | 2023-12-29 | 2023-12-29 | Super junction VDMOS and manufacturing method thereof |
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