CN117892694B - FFT twiddle factor index generation circuit and design method thereof - Google Patents
FFT twiddle factor index generation circuit and design method thereof Download PDFInfo
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Abstract
The invention provides an FFT twiddle factor index generating circuit and a design method thereof, relating to the technical field of data processing, wherein the circuit comprises: twenty sequentially connected stage circuits, the first to nineteenth stage circuits including: eight butterfly operation circuits, a rotation multiplier, a routing circuit or a delay replacement circuit, wherein the first to nineteenth stage circuits further comprise a rotation factor index circuit, each butterfly operation circuit is provided with two data input channels and a data output channel corresponding to the two data input channels, one rotation multiplier is arranged on part of the data output channels, and the output of the rotation factor index circuit and the output of the butterfly operation circuit are input to the routing circuit or the delay replacement circuit after passing through the rotation multiplier; then input the butterfly circuit of the next stage circuit. The technical scheme of the invention solves the problems that the twiddle factor index cannot be generated in real time, the twiddle factor index depends on storage and consumes excessive memory resources during FFT operation of various point lengths in the prior art.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to an FFT twiddle factor index generating circuit and a design method thereof.
Background
Compared with the method for serially calculating FFT by a general processor, the design of the FFT processing circuit with multiple parallelism can effectively utilize hardware resources to improve the processing speed and the data throughput rate. The pipeline is a common circuit design method, and the processed data is processed by each module in sequence through serially linking a plurality of modules with single functions, so that the data efficiency is improved. The FFT processing circuit adopting the pipeline design method is subdivided into a delay substitution (DC) structure, a Delay Feedback (DF) structure, a single stream feedback Structure (SFF), a single stream substitution Structure (SC), etc., wherein the delay substitution structure is widely used by virtue of the characteristic of optimal utilization efficiency of hardware resources.
The twiddle factor is a set of complex constants commonly used in FFT algorithms for adjusting the phase of each frequency component during the transformation of the signal. When the twiddle factor is multiplied by a complex number, the twiddle factor is called twiddle factor because it has the effect of twiddling the complex number on the unit circle of the complex plane. Twiddle factorThe formula of (2) isWhere N is the length of the number of points of the FFT algorithm,Is a twiddle factor index. In FFT processors, twiddle factor indexes are typically employed instead of twiddle factor participation operations. The first reason is that in the circuit, the coordinate rotation digital computing method (Coordinate Rotation Digital Computer, CORDIC) is adopted to replace complex multiplication, so that the number of logic gates can be effectively reduced. The CORDIC algorithm can complete the operation by providing complex multiplier and twiddle factor index. And compared with twiddle factors, twiddle factor indexes have fewer bits, so that the storage cost is reduced.
Chinese patent (CN 206270957U) discloses an FFT processor, and uses a method of pre-storing twiddle factors, twiddle factors are stored in twiddle factor storage units, and twiddle factors are input to butterfly operation units for calculation during operation. Chinese patent (CN 103176949 a) discloses a circuit and method for implementing FFT/IFFT transformation, and uses a twiddle factor storage unit ROM to store twiddle factors. When the length of the point is longer, the prestored twiddle factor method of the two patents needs to occupy larger memory resources. The 1M point FFT algorithm has a total of about 1M twiddle factors. The memory consumption of these twiddle factors is not acceptable for high performance, low cost FFT processors. Meanwhile, FFTs with different point lengths use different twiddle factors, and if a pre-stored twiddle factor method is adopted by an FFT processor supporting variable points, multiple sets of twiddle factors need to be stored, which is also unacceptable for a high-performance and low-cost FFT processor.
Therefore, there is a need for a low-cost FFT twiddle factor index generation circuit and method of designing the same that can satisfy a variety of point length FFT operations.
Disclosure of Invention
The invention mainly aims to provide an FFT twiddle factor index generating circuit and a design method thereof, which are used for solving the problems that twiddle factor indexes cannot be generated in real time, are dependent on storage and consume excessive memory resources during FFT operation with multiple point lengths in the prior art.
To achieve the above object, the present invention provides an FFT rotation factor index generation circuit, comprising: twenty sequentially connected stage circuits, the first to nineteenth stage circuits including: eight butterfly operation circuits, a rotation multiplier, a routing circuit or a delay replacement circuit, wherein the first to nineteenth stage circuits further comprise a rotation factor index circuit, each butterfly operation circuit is provided with two data input channels and a data output channel corresponding to the two data input channels, one rotation multiplier is arranged on part of the data output channels, and the output of the rotation factor index circuit and the output of the butterfly operation circuit are input to the routing circuit or the delay replacement circuit after passing through the rotation multiplier; the output of the routing circuit or the delay replacement circuit is input into the butterfly circuit of the next stage circuit; the twentieth stage circuit includes: eight butterfly operation circuits.
Further, the first to third stage circuits include: eight butterfly circuits, a plurality of rotation multipliers and a routing circuit; the fourth to nineteenth stage circuits include: eight butterfly circuits, a plurality of rotation multipliers and eight delay permutators, one delay permutator for each butterfly circuit.
Further, the twiddle factor indexing circuit includes: the first adder, the second adder, the index increment register, the seven AND gates, the bit reverser, the index register and the CORDIC operation module; the output end of the first adder is connected with the index register and outputs 20 bits to the index register, and the index register is provided with two output ends which are respectively connected with a CORDIC operation module and a second input end of the first adder and outputs 20 bits to the CORDIC operation module and the first adder; the other input end of each AND gate inputs a logic control signal; the output end of the partial AND gate is also connected with the input end of the second adder and inputs 4bit numbers to the second adder, and the output end of the second adder is connected with the index increment register and outputs 4bit numbers to the index increment register; the reset terminal of the index register inputs a clock signal with a clock period of 4096T.
Further, a clock signal with a clock period of T is input to a clock input end of the first adder; the second input of the second adder inputs operand 1 and the clock input of the second adder inputs a clock signal with a clock period of 4096T.
The invention also provides a design method of the FFT twiddle factor index generating circuit, which comprises the following steps:
S1, designing a 16-path parallel processing FFT processing circuit according to a multi-path delay replacement structure.
S2, setting an FFT twiddle factor index generating circuit according to a Cooley-Tukey FFT algorithm formula on the basis of the step S1.
Further, the step S1 specifically includes the following steps:
s1.1,1M Point FFT The method comprises the steps of performing operation in each stage, designing a circuit with twenty operation stages, wherein each stage circuit comprises 8 butterfly operation circuits, each butterfly operation circuit has two channels of data input, forming an operation circuit with 16 parallelism, and binary encoding the 16 parallel channels into the circuitThe coding 0000 is the 1 st data output interface of the 1 st butterfly operation circuit; code 0011 is the 2 nd data output interface of the second butterfly circuit, and so on.
S1.2, setting a routing circuit in the first-stage circuit to the third-stage circuit, wherein eight butterfly circuits are connected with one routing circuit to binary encode 1M data into 1M data; According to the design method of the multi-path delay replacement structure, the data code input into the first stage is summarized asThat is, the first data input channel of the first butterfly circuit sequentially inputs the first sixteen of the data, the second data input channel sequentially inputs the first sixteen of the second half of the data, and so on, to generate binary encoding tables of the routing circuit input data in the second, third and fourth stage circuits.
Further, the step S1 further includes the following steps:
S1.3, each delay replacement circuit is provided with two input channels and two output channels, the two input channels are distributed in a fourth stage circuit to a nineteenth stage circuit, each stage circuit is provided with eight delay replacement circuits, and the eight delay replacement circuits are connected with eight butterfly operation circuits in a one-to-one correspondence manner; of the fourth stage circuit Channel and method for manufacturing the sameThe output data of the channel isAnd (3) withOf the fifth stage circuitEncoding of channel input data asAnd (3) withThe two data are combined to obtainAnd so on, a binary encoding table of the delay permute circuit input data in the sixth to twenty stage circuits is generated.
S1.4, when the length of the FFT point number is changed, the input port of the data also needs to be correspondingly changed: when the dot length of the FFT is 1M dots, data is input from an input port of the first-stage circuit; the number of points of the FFT is reduced by one time, and the input port of the data is shifted back by one stage circuit.
Further, the step S2 specifically includes the following steps:
s2.1, calculating a twiddle factor index of a 1M point FFT algorithm according to a Cooley-Tukey FFT algorithm formula, wherein the Cooley-Tukey FFT algorithm formula is shown in formula (1):
；
Wherein, Representing the time-domain data,Representing the frequency domain data,，、、Representing the rotation factor of the rotation of the rotor,Representing twiddle factor index, N represents the length of the number of points of the long sequence in the Cooley-Tukey FFT algorithm, L, C represents the length of the number of points of the short sequence.
S2.2 taking the twiddle factor index circuit of the 8 th stage as an example, when the FFT point length is 1048576, the twiddle factor index circuit has the expression ofI.e. the product of the inverse number of 8bit bits added by one per 4096 clocks and the natural ordinal number of 12bit added by one per clock; when the FFT point length is 512K, the expression of the twiddle factor index circuit isI.e. the product of an inverse number of 8 bits plus one every 4096 clocks and a 12 bits plus one every clock, with the highest order 0, since the 8 th stage of data encoding isTherefore, the expression of the rotation factor index circuit in the 16-channel delay substitution circuit isThe double-circulation bit anti-accumulation twiddle factor index circuit is designed according to the method.
The invention has the following beneficial effects:
The invention provides a double-circulation bit anti-accumulation twiddle factor index circuit which can provide twiddle factor indexes for twiddle factor multiplication circuits in FFT processing modes with different point lengths and solves the problem that twiddle factor indexes are generated in real time in a multi-point mode without being supported by twiddle factor multiplication circuits in a multi-path delay replacement structure. The FFT processing circuit provided by the invention can realize FFT operation of a plurality of point lengths such as 1048576 point, 524288 point, 26144 point, … point, 512 point, 256 point and the like through on-line configuration, and meanwhile, the calculation performance is kept unchanged.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art. In the drawings:
Fig. 1 shows a schematic diagram of an FFT twiddle factor index generation circuit of the present invention.
Fig. 2 shows a schematic diagram of a twiddle factor indexing circuit of the present invention.
Wherein, the reference numerals in the drawings are as follows:
10. an index increment register; 20. and an AND gate; 30. a bit inverter; 40. a first adder; 50. a second adder; 60. an index register; 70. and a CORDIC operation module.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An FFT twiddle factor index generation circuit as shown in fig. 1, comprising: twenty sequentially connected stage circuits, the first to nineteenth stage circuits including: eight butterfly operation circuits, a rotation multiplier, a routing circuit or a delay replacement circuit, wherein the first to nineteenth stage circuits further comprise a rotation factor index circuit, each butterfly operation circuit is provided with two data input channels and a data output channel corresponding to the two data input channels, one rotation multiplier is arranged on part of the data output channels, and the output of the rotation factor index circuit and the output of the butterfly operation circuit are input to the routing circuit or the delay replacement circuit after passing through the rotation multiplier; the output of the routing circuit or the delay replacement circuit is input into the butterfly circuit of the next stage circuit; the twentieth stage circuit includes: eight butterfly operation circuits.
Specifically, the first to third stage circuits include: eight butterfly circuits, a plurality of rotation multipliers and a routing circuit; the fourth to nineteenth stage circuits include: eight butterfly circuits, a plurality of rotation multipliers and eight delay permutators, one delay permutator for each butterfly circuit.
Specifically, the twiddle factor indexing circuit as shown in fig. 2 includes: first and second adders, an index increment register 10, seven AND gates 20, a bit inverter 30, an index register 60, and a CORDIC operation module 70; part of output bits of the index increment register 10 are respectively connected with the input end of the AND gate 20, other output bits of the index increment register 10 and the output end of the AND gate 20 are connected with the input end of the bit reverser 30 and output 8 bits to the bit reverser 30, the output end of the bit reverser 30 is connected with the first input end of the first adder 40 and inputs 8 bits to the first adder 40, the output end of the first adder 40 is connected with the index register 60 and outputs 20 bits to the index register 60, the index register 60 is provided with two output ends, and the two output ends are respectively connected with the second input ends of the CORDIC operation module 70 and the first adder 40 and output 20 bits to the CORDIC operation module 70 and the first adder 40; the other input terminal of each and gate 20 inputs a logic control signal; the output end of the partial AND gate 20 is also connected with the input end of the second adder 50 and inputs 4 bits to the second adder 50, and the output end of the second adder 50 is connected with the index increment register 10 and outputs 4 bits to the index increment register 10; the reset terminal of the index register 60 inputs a clock signal having a clock period of 4096T.
Specifically, a clock signal with a clock period of T is input to a clock input end of the first adder; the second input of the second adder inputs operand 1 and the clock input of the second adder inputs a clock signal with a clock period of 4096T. The invention also provides a design method of the FFT twiddle factor index generating circuit, which comprises the following steps:
S1, designing a 16-path parallel processing FFT processing circuit according to a multi-path delay replacement structure.
S2, setting an FFT twiddle factor index generating circuit according to a Cooley-Tukey FFT algorithm formula on the basis of the step S1.
Specifically, the step S1 specifically includes the steps of:
S1.1, according to the design method of the multipath delay replacement structure, 1M # ) Point FFT processingThe method comprises the steps of performing operation in each stage, designing a circuit with twenty operation stages, wherein each stage circuit comprises 8 butterfly operation circuits, each butterfly operation circuit has two channels of data input, forming an operation circuit with 16 parallelism, and binary encoding the 16 parallel channels into the circuitThe coding 0000 is the 1 st data output interface of the 1 st butterfly operation circuit; code 0011 is the 2 nd data output interface of the second butterfly circuit, and so on.
Wherein the first to nineteenth stage circuits include: eight butterfly operation circuits, a rotation multiplier, a routing circuit or a delay replacement circuit, wherein the first to nineteenth stage circuits further comprise a rotation factor index circuit, each butterfly operation circuit is provided with two data input channels and a data output channel corresponding to the two data input channels, one rotation multiplier is arranged on part of the data output channels, and the output of the rotation factor index circuit and the output of the butterfly operation circuit are input to the routing circuit or the delay replacement circuit after passing through the rotation multiplier; the output of the routing circuit or the delay replacement circuit is input into the butterfly circuit of the next stage circuit; the twentieth stage circuit includes: eight butterfly operation circuits.
S1.2, the function of the routing circuit is to convey the output data of the stage to the corresponding next stage data input interface. The FFT algorithm is an in-situ algorithm, and N time domain data are input, and after calculation, N frequency domain results are generated. Routing circuits are arranged in the first stage circuit to the third stage circuit, eight butterfly circuits are connected with one routing circuit, and 1M data are binary coded into the data; According to the design method of the multi-path delay replacement structure, the data code input into the first stage is summarized asThat is, the first data input channel of the first butterfly circuit sequentially inputs the first sixteen of the data, the second data input channel sequentially inputs the first sixteen of the second half of the data, and so on, to generate binary encoding tables of the routing circuit input data in the second, third and fourth stage circuits. As shown in table 1.
Specifically, step S1 further includes the steps of:
S1.3, each delay replacement circuit is provided with two input channels and two output channels, the two input channels are distributed in a fourth stage circuit to a nineteenth stage circuit, each stage circuit is provided with eight delay replacement circuits, and the eight delay replacement circuits are connected with eight butterfly operation circuits in a one-to-one correspondence manner; of the fourth stage circuit Channel and method for manufacturing the sameThe output data of the channel isAnd (3) withWherein 16 channels are encoded asWhen (when)When 0, 8 odd channels are indicated. When (when)For 1, 8 even channels are indicated. Of the fifth stage circuitEncoding of channel input data asAnd (3) withThe two data are combined to obtainAnd so on, generating a data encoding table input by a delay replacement circuit in the sixth to twenty-stage circuits. As shown in table 1.
Table 1 data encoding table for each stage
。
S1.4, when the length of the FFT point number is changed, the input port of the data also needs to be correspondingly changed: when the dot length of the FFT is 1M dots, data is input from an input port of the first-stage circuit; the number of points of the FFT is reduced by one time, and the input port of the data is shifted back by one stage circuit.
And similarly, for data encoding of other point length FFT processing,Length data needBits. In the 1M point FFT processing mode, the first stage input data is encoded as. According to the design method of the delay-substitution FFT processing circuit, in the 512K point FFT processing mode, only 19 stages of operations are needed, and stages 2 to 20 in the 1M point FFT processing mode are multiplexed. Meanwhile, the 512K point FFT processing mode only occupies 8 paths of data input paths, and the other 8 paths can simultaneously perform another group of 512K point FFT processing. The 256K point FFT processing only occupies 4 data input paths, and four groups of 256K point FFT processing are performed simultaneously; 128K to 256 points occupy two data input channels, and 4 groups of FFT are processed simultaneously. According to the design method of the multipath delay replacement structure, the coding of starting step sections of data under various FFT point number modes is obtained, as shown in a table 2.
TABLE 2 binary encoding table for starting step pieces of input data in multiple point modes
。
And similarly, for data encoding of other point length FFT processing,Length data needBits. In section 1.2, the encoding of the first stage input data in the 1M point FFT processing mode is described as. According to the design method of the delay-substitution FFT processing circuit, in the 512K point FFT processing mode, only 19 stages of operations are needed, and stages 2 to 20 in the 1M point FFT processing mode are multiplexed. Meanwhile, the 512K point FFT processing mode only occupies 8 paths of data input paths, and the other 8 paths can simultaneously perform another group of 512K point FFT processing. The 256K point FFT processing only occupies 4 data input paths, and four groups of 256K point FFT processing are performed simultaneously; 128K to 256 points occupy two data input channels, and 4 groups of FFT are processed simultaneously. According to the design method of the multipath delay replacement structure, the coding of starting step sections of data under various FFT point number modes is obtained, as shown in a table 2.
Specifically, the step S2 specifically includes the following steps:
S2.1, calculating a twiddle factor index of a 1M point FFT algorithm according to a Cooley-Tukey FFT algorithm formula, wherein the Cooley-Tukey FFT algorithm formula is shown in a table 3, and the Cooley-Tukey FFT algorithm formula is shown in a formula (1):
；
Wherein, Representing the time-domain data,Representing the frequency domain data,，、、Representing the rotation factor of the rotation of the rotor,Representing twiddle factor index, N represents the length of the number of points of the long sequence in the Cooley-Tukey FFT algorithm, L, C represents the length of the number of points of the short sequence.
Table 3 twiddle factor index table for each stage
。
Thus, a twiddle factor index of 1M point is obtained, and the design of each twiddle factor multiplication circuit in the FFT processing circuit can be determined by combining the data coding of each stage of circuit. Taking the second stage circuit as an example, the data passing through the stage is encoded asTwiddle factor index ofSubstituting data codes into twiddle factor indexesIt can be known that the twiddle factor index of 0011 channel isThe twiddle factor index of 0101 channel is。
When the length of the FFT point number is changed, the twiddle factor index circuit in the partial stage circuit is correspondingly changed. The twiddle factor indexes of the circuits at each stage in each FFT processing point mode are listed, and when the length of the FFT point is shortened in steps of 2 power, the highest bit in the representing binary coding is required to be set to 0.
S2.2 taking the twiddle factor index circuit of the 8 th stage as an example, when the FFT point length is 1048576, the twiddle factor index circuit has the expression ofI.e. the product of the inverse number of 8bit bits added by one per 4096 clocks and the natural ordinal number of 12bit added by one per clock; when the FFT point length is 512K, the expression of the twiddle factor index circuit isI.e. the product of an inverse number of 8 bits plus one every 4096 clocks and a 12 bits plus one every clock, with the highest order 0, since the 8 th stage of data encoding isTherefore, the expression of the rotation factor index circuit in the 16-channel delay substitution circuit isThe double-circulation bit anti-accumulation twiddle factor index circuit is designed according to the method.
The partial bit output bits of the index increment register are connected to the input of the AND gate and are controlled via the AND gate variable point control signal. The function of the bit inverter is to binary reverse-sequence the input signal and output it, for example, to reverse-sequence 10110 to 01101. In an index increment registerFour bits are self-added by the adder by 1 every 4096 clocks. In 1048576 point FFT processing mode, mode control signal=1111111, The bit inverter outputAnd 1 self-addition per clock is realized by the index register and the adder. The numerical value of the index register is used as a twiddle factor index to be input into a CORDIC operation module. When switching other point processing modes, the control signal is shielded bit by bit from high order to low orderAnd (3) obtaining the product.
The performance of the proposed circuit is compared as follows:
the 1M point variable point FFT processor circuit designed by the invention is converted into Verilog HDL language codes and is realized on a Xilinx Kintex UltraScale 115 FPGA platform. Simulation, synthesis and implementation were performed using the Vivado 2022.1 version, where the implementation employed the performance_ WLBlockPlacementFanoutOpt strategy using the Vivado Synthesis Defaults strategy. Table 4 is the main resource consumption of the FPGA platform.
TABLE 4 FPGA resource consumption Table
。
In order to evaluate the performance of the valve, performance parameters such as power consumption, working frequency and the like are evaluated, and compared with the former work for analysis.
As shown in Table 5, compared with the designs of F.Han and KANDERS, the FFT processing circuit provided by the invention achieves higher throughput at lower working frequency and is excellent in power consumption control. Because of the difference of the implementation platforms, the Wei Xing [2] design can stably run in the environment of a high-frequency clock, so that the throughput rate of a higher point is obtained, but the design only supports 2048-128 point variable point FFT processing, and compared with the design in the present invention, the design has the defect.
Table 5 FFT comparison of circuit index
。
In summary, the invention provides the FFT processing circuit with high throughput and supporting 1048576-256 variable points, and the physical implementation is completed based on the Sailingsi XCKU FPGA chip. The FFT processor has 16 paths of parallel data paths, can reach the throughput rate of 3.2GSPS of full points under the clock frequency of 200MHz, and has obvious advantages compared with the design of an FPGA platform, the power consumption throughput rate is improved by 5.6 times.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.
Claims (7)
1. An FFT rotation factor index generation circuit, comprising: twenty sequentially connected stage circuits, the first to nineteenth stage circuits including: eight butterfly operation circuits, a rotation multiplier, a routing circuit or a delay replacement circuit, wherein the first to nineteenth stage circuits further comprise a rotation factor index circuit, each butterfly operation circuit is provided with two data input channels and a data output channel corresponding to the two data input channels, one rotation multiplier is arranged on part of the data output channels, and the output of the rotation factor index circuit and the output of the butterfly operation circuit are input to the routing circuit or the delay replacement circuit after passing through the rotation multiplier; the output of the routing circuit or the delay replacement circuit is input into the butterfly circuit of the next stage circuit;
The twentieth stage circuit includes: eight butterfly operation circuits;
The twiddle factor indexing circuit includes: the first adder, the second adder, the index increment register, the seven AND gates, the bit reverser, the index register and the CORDIC operation module;
the output end of the first adder is connected with the index register and outputs 20 bits to the index register, and the index register is provided with two output ends which are respectively connected with a CORDIC operation module and a second input end of the first adder and outputs 20 bits to the CORDIC operation module and the first adder;
The other input end of each AND gate inputs a logic control signal;
the output end of the partial AND gate is also connected with the input end of the second adder and inputs 4bit numbers to the second adder, and the output end of the second adder is connected with the index increment register and outputs 4bit numbers to the index increment register;
The reset terminal of the index register inputs a clock signal with a period of 4096T.
2. The FFT twiddle factor index generation circuit as defined in claim 1, wherein the first to third stage circuits comprise: eight butterfly circuits, a plurality of rotation multipliers and a routing circuit;
the fourth to nineteenth stage circuits include: eight butterfly circuits, a plurality of rotation multipliers and eight delay permutators, one delay permutator for each butterfly circuit.
3. The FFT twiddle factor index generation circuit as claimed in claim 1, wherein the clock input terminal of the first adder inputs a clock signal with period T;
the second input of the second adder inputs operand 1, and the clock input of the second adder inputs a clock signal with a period of 4096T.
4. A method of designing an FFT twiddle factor index generation circuit, the circuit of any of claims 1-3, comprising the steps of:
s1, designing a 16-path parallel processing FFT processing circuit according to a multi-path delay replacement structure;
s2, setting an FFT twiddle factor index generating circuit according to a Cooley-Tukey FFT algorithm formula on the basis of the step S1.
5. The method for designing an FFT twiddle factor index generation circuit according to claim 4, wherein the step S1 comprises the steps of:
s1.1,1M Point FFT The method comprises the steps of performing operation in each stage, designing a circuit with twenty operation stages, wherein each stage circuit comprises 8 butterfly operation circuits, each butterfly operation circuit has two channels of data input, the two channels of data input form an operation circuit with 16 parallelism, and 16 parallel channels are binary coded as/>The coding 0000 is the 1 st data output interface of the 1 st butterfly operation circuit; coding 0011 is the 2 nd data output interface of the second butterfly operation circuit, and so on;
s1.2, setting a routing circuit in the first-stage circuit to the third-stage circuit, wherein eight butterfly circuits are connected with one routing circuit to binary encode 1M data into 1M data ; According to the design method of the multi-path delay replacement structure, the data code input into the first stage is summarized asThat is, the first data input channel of the first butterfly circuit sequentially inputs the first sixteen of the data, the second data input channel sequentially inputs the first sixteen of the second half of the data, and so on, to generate the binary encoding tables of the routing circuit input data of the second, third and fourth stage circuits.
6. The method for designing an FFT twiddle factor index creation circuit according to claim 5, wherein step S1 further comprises the steps of:
S1.3, each delay replacement circuit is provided with two input channels and two output channels, the two input channels are distributed in a fourth stage circuit to a nineteenth stage circuit, each stage circuit is provided with eight delay replacement circuits, and the eight delay replacement circuits are connected with eight butterfly operation circuits in a one-to-one correspondence manner; of the fourth stage circuit Channel and/>The output data of the channel isAnd (3) withOf the fifth stage circuitEncoding of channel input data asAnd (3) withThe two data are combined to obtainAnd so on, generating a binary coding table of the delay replacement circuit input data of the sixth-twenty-stage circuit;
S1.4, when the length of the FFT point number is changed, the input port of the data also needs to be correspondingly changed: when the dot length of the FFT is 1M dots, data is input from an input port of the first-stage circuit; the number of points of the FFT is reduced by one time, and the input port of the data is shifted back by one stage circuit.
7. The method for designing an FFT twiddle factor index generation circuit according to claim 4, wherein step S2 comprises the steps of:
s2.1, calculating a twiddle factor index of a 1M point FFT algorithm according to a Cooley-Tukey FFT algorithm formula, wherein the Cooley-Tukey FFT algorithm formula is shown in formula (1):
；
Wherein, Representing time domain data,/>Representing frequency domain data,/>，/>、/>、/>Represents a twiddle factor,/>Representing a twiddle factor index, wherein N represents the dot length of a long sequence in a Cooley-Tukey FFT algorithm, and L, C represents the dot length of a short sequence;
S2.2 taking the twiddle factor index circuit of the 8 th stage as an example, when the FFT point length is 1048576, the twiddle factor index circuit has the expression of I.e. the product of the inverse number of 8bit bits added by one per 4096 clocks and the natural ordinal number of 12bit added by one per clock; when the FFT point length is 512K, the expression of the twiddle factor index circuit isI.e. the product of an inverse number of 8 bits plus one every 4096 clocks and a 12 bits plus one every clock, with the highest order 0, since the 8 th stage of data encoding isTherefore, the expression of the rotation factor index circuit in the 16-channel delay substitution circuit isThe double-circulation bit anti-accumulation twiddle factor index circuit is designed according to the method.
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