CN117881211A

CN117881211A - Display device and method of manufacturing the same

Info

Publication number: CN117881211A
Application number: CN202311262500.8A
Authority: CN
Inventors: 郑多云; 裵水斌; 姜泰旭; 金湘甲; 吕伦钟; 丁有光
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-10-11
Filing date: 2023-09-27
Publication date: 2024-04-12

Abstract

The present disclosure relates to a display device and a method of manufacturing the display device. The display device includes: a first pixel electrode disposed in the first emission region on the substrate; an insulating layer covering edges of the first pixel electrode; a first light emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light emitting layer; a plurality of banks disposed on the insulating layer and surrounding the first emission region; and an organic pattern disposed on the plurality of banks around the first emission region and including the same material as the first emission layer. A side surface of each of the plurality of banks is spaced apart from a side surface of the insulating layer.

Description

Display device and method of manufacturing the same

Technical Field

The present disclosure relates to a display device and a method of manufacturing the display device.

Background

With the development of information society, demands for display devices for displaying images have been diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart televisions. Examples of the display device include a flat panel display device such as a liquid crystal display ("LCD") device, a field emission display ("FED") device, or an organic light emitting diode ("OLED") display device. Specifically, the OLED display device includes a light emitting element that can cause pixels of a display panel to emit light, and thus can display an image without a backlight unit that supplies light to the display panel.

Disclosure of Invention

Aspects of the present disclosure provide a display device and a method of manufacturing the same capable of preventing defects in a light emitting element and improving reliability by preventing a common electrode from being shorted in a process of forming the light emitting element in a separate emission region without performing a mask process.

However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an embodiment, a display device includes: a first pixel electrode disposed in the first emission region on the substrate; an insulating layer covering edges of the first pixel electrode; a first light emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light emitting layer; a plurality of banks disposed on the insulating layer and surrounding the first emission region; and a first organic pattern disposed on the plurality of banks around the first emission region and including the same material as the first emission layer. A side surface of each of the plurality of banks is spaced apart from a side surface of the insulating layer.

The plurality of banks may include: a first bank disposed on the insulating layer and including a metal material; a second bank disposed on the first bank; and a third bank disposed between the first bank and the insulating layer.

The side surfaces of the first and third banks may be recessed inward from the side surfaces of the second and third banks.

The second bank may include a tip protruding from a side surface of the first bank toward the first emission region.

The first common electrode may extend to a side surface of each of the first and third banks, and may be in contact with the side surfaces of the first and third banks.

The display device may further include: a second pixel electrode disposed in a second emission region on the substrate; a second light emitting layer disposed on the second pixel electrode; and a second common electrode disposed on the second light emitting layer.

The first and second common electrodes may be electrically connected via the first and third banks.

The plurality of banks may include: a first bank disposed on the insulating layer and including a metal material; and a second bank disposed on the first bank.

The side surface of the first bank may be recessed inward from the side surface of the second bank.

The display device may further include: a second pixel electrode disposed in a second emission region on the substrate; a second light emitting layer disposed on the second pixel electrode; and a second common electrode disposed on the second light emitting layer. The first common electrode and the second common electrode may be electrically connected via the first bank.

According to an embodiment, a method of manufacturing a display device includes: forming a first pixel electrode and a second pixel electrode on a substrate; sequentially depositing a sacrificial layer, an insulating layer, a third bank, a first bank and a second bank on the first pixel electrode and the second pixel electrode; forming a first photoresist on the second bank, the first photoresist not overlapping the first pixel electrode in a plan view; etching the second bank, the first bank, and the third bank using the first photoresist as a mask; forming a second photoresist covering side surfaces of each of the first, second, and third banks; and etching the insulating layer using the second photoresist as a mask.

The method may further include, after the etching of the insulating layer: the sacrificial layer is etched using the second photoresist as a mask to expose the first pixel electrode.

The method may further include, after the exposing of the first pixel electrode: forming a first light emitting layer on the first pixel electrode, and forming a first organic pattern on the second bank; forming a first common electrode on the first light emitting layer, and forming a first electrode pattern on the first organic pattern; forming a cap layer on the first common electrode, and forming a first cap pattern on the first electrode pattern; and forming a first inorganic layer covering the cap layer, the first cap pattern, and the side surface of the first bank.

The etching of the second, first and third banks may include recessing the side surface of the first bank inwardly from the side surface of each of the second and third banks.

The method may further include, after the etching of the insulating layer: the second photoresist is removed, and the sacrificial layer, and the side surfaces of the first bank are etched.

According to an embodiment, a method of manufacturing a display device includes: forming a first pixel electrode and a second pixel electrode on a substrate; sequentially depositing a sacrificial layer, an insulating layer, a first bank and a second bank on the first pixel electrode and the second pixel electrode; forming a first photoresist on the second bank, the first photoresist not overlapping the first pixel electrode in a plan view; etching the second bank and the first bank using the first photoresist as a mask; forming a second photoresist covering side surfaces of each of the first and second banks; and etching the insulating layer using the second photoresist as a mask.

The etching of the second bank and the first bank may include recessing the side surface of the first bank inward from the side surface of the second bank.

According to the foregoing and other embodiments of the present disclosure, when the banks are etched using the first photoresist as a mask and the insulating layer covering the side surface of each of the plurality of banks is etched using the second photoresist as a mask, the insulating layer may have an inclined side surface and may provide a relatively thin residual pattern. Further, since the common electrode can be prevented from being short-circuited, defects of the light emitting element can be prevented, and reliability can be effectively improved.

It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description.

Drawings

The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

Fig. 1 is a perspective view of a display device according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of the display device of FIG. 1;

FIG. 3 is a plan view of a display panel of the display device of FIG. 1;

fig. 4 is a cross-sectional view illustrating a portion of the display device of fig. 1;

FIG. 5 is an enlarged cross-sectional view of area A1 of FIG. 4;

fig. 6 to 15 are sectional views showing examples of how the display device of fig. 4 is fabricated;

fig. 16 to 18 are sectional views showing another example of how the display device of fig. 4 is fabricated;

fig. 19 is a cross-sectional view illustrating a portion of a display device according to another embodiment of the present disclosure;

FIG. 20 is an enlarged cross-sectional view of area A2 of FIG. 19;

fig. 21 to 26 are sectional views showing examples of how the display device of fig. 19 is fabricated; and is also provided with

Fig. 27 to 29 are sectional views showing another example of how the display device of fig. 19 is manufactured.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of an apparatus or method employing one or more embodiments of the disclosure disclosed herein. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but need not be exclusive, nor does it necessarily limit the present disclosure. For example, the particular shapes, configurations, and features of the embodiments may be used or implemented in other embodiments without departing from the disclosure.

The illustrated embodiments will be understood to provide features of different details in which some aspects of the disclosure may be implemented in practice, unless otherwise indicated. Thus, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and/or aspects of the various embodiments (hereinafter singly or collectively referred to as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the disclosure.

The use of cross-hatching and/or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless indicated otherwise, neither the presence nor absence of cross-hatching or shading conveys or indicates any preference or requirement for a particular material, material property, size, proportion, commonality between illustrated elements, and/or any other feature, attribute, property, or the like.

In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While embodiments may be implemented differently, the order of particular processes may be performed differently than what is described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Furthermore, like reference numerals refer to like elements.

When an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this extent, the term "connected" can refer to a physical, electrical, and/or fluid connection with or without intervening elements.

Further, the X-axis direction, the Y-axis direction, and the Z-axis direction are not limited to three axes of a rectangular coordinate system, and thus the X-axis direction, the Y-axis direction, and the Z-axis direction can be interpreted in a broader sense. For example, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of X only, Y only, Z only, or two or more of X, Y and Z (such as XYZ, XY, YZ or XZ, etc.). As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms such as "under … …," "under … …," "under … …," "lower," "above … …," "upper," "above … …," "above" and "side" (e.g., as in "sidewall") and the like may be used herein for descriptive purposes and thereby describing the relationship of one element to another element(s) as shown in the figures. In addition to the orientations depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below … …" may encompass both an orientation of above … … and below … …. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should therefore be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises (comprises, comprising)" and/or "comprising (includes, including)" when used in this specification specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms and, therefore, are used to describe inherent deviations of measured, calculated, and/or provided values that would be identified by one of ordinary skill in the art.

Various embodiments are described herein with reference to cross-sectional illustrations and/or exploded illustrations that are schematic illustrations of embodiments and/or intermediate structures. Thus, variations in the shape of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, will be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result, for example, from manufacturing. In this way, the regions illustrated in the figures may be schematic in nature and the shapes of the regions may not reflect the actual shape of the regions of the device and, thus, are not necessarily intended to be limiting.

As is conventional in the art, some embodiments are described and illustrated in the figures in the form of functional blocks, units, components and/or modules. Those skilled in the art will appreciate that the functional blocks, units, components, and/or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, or the like, that may be formed using semiconductor-based fabrication techniques or other fabrication techniques. In the case of functional blocks, units, components, and/or modules that are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions recited herein, and may optionally be driven by firmware and/or software. It is also contemplated that each of the functional blocks, units, components, and/or modules may be implemented by special purpose hardware, or as a combination of special purpose hardware to perform some of the functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Moreover, each functional block, unit, component, and/or module of some embodiments may be physically separated into two or more interacting and discrete functional blocks, units, components, and/or modules without departing from the scope of the present disclosure. Furthermore, the functional blocks, units, components, and/or modules of some embodiments may be physically combined into more complex functional blocks, units, components, and/or modules without departing from the scope of the present disclosure.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

Fig. 1 is a perspective view of a display device according to an embodiment of the present disclosure.

Referring to fig. 1, a display device 10 may be suitable for use in a mobile electronic device such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a mobile communication terminal, an electronic organizer, an electronic book reader, a portable multimedia player ("PMP"), a navigation system, or an ultra mobile PC ("UMPC"). For example, the display device 10 may be suitable as a display unit for a television ("TV") or notebook computer, monitor, electronic billboard, or internet of things ("IoT") device. In another example, the display device may be adapted for use with a wearable device such as a smart watch, a watch phone, a glasses display, or a head mounted display ("HMD").

The display device 10 may have an almost rectangular shape in a plan view. Here, the "plan view" is a view in the thickness direction (Z-axis direction). For example, the display device 10 may have a nearly rectangular shape having a short side extending in the X-axis direction and a long side extending in the Y-axis direction. The corners where the short sides and the long sides of the display device 10 meet may be rounded to have a predetermined curvature or may be right angles. The shape of the display device 10 is not particularly limited, and the display device 10 may be formed in various other shapes such as another polygonal shape, a circular shape, or an elliptical shape.

The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

The display panel 100 may include a main area MA and a sub area SBA.

The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light via a plurality of emission areas or openings. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining an emission region or an opening, and a self-light emitting element.

For example, the self-light emitting element may include an Organic Light Emitting Diode (OLED), a quantum dot Light Emitting Diode (LED) including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and/or a micro LED, but the disclosure is not limited thereto.

The non-display area NDA may be outside the display area DA. The non-display area NDA may be defined as an edge portion of the main area MA. The non-display area NDA may include a gate driver (not shown) that supplies a gate signal to gate lines and fan-out lines (not shown) connecting the display driver 200 and the display area DA.

The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may comprise a flexible material that is bendable, foldable or crimpable. For example, in the case where the sub-region SBA is bendable, the sub-region SBA may be bent to overlap with the main region MA in the thickness direction (Z-axis direction). The sub-area SBA may include the display driver 200 and a pad unit connected to the circuit board 300. The sub-area SBA may be optional, and the display driver 200 and the pad unit may be disposed in the non-display area NDA.

The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply the data voltage to the data line. The display driver 200 may supply a power supply voltage to the power supply line and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit ("IC") and may be mounted on the display panel 100 in a chip on glass ("COG") or a plastic flip chip ("COP") manner or via ultrasonic bonding. For example, the display driver 200 may be disposed in the sub-region SBA, and when the sub-region SBA is folded, the display driver 200 may overlap with the main region MA in the thickness direction (Z-axis direction). In another example, the display driver 200 may be mounted on the circuit board 300.

The circuit board 300 may be attached to the pad unit of the display panel 100 via an anisotropic conductive film ("ACF"). The leads of the circuit board 300 may be electrically connected to the pad units of the display panel 100. The circuit board 300 may be a printed circuit board ("PCB"), a flexible PCB ("FPCB"), or a flexible film such as a chip on film ("COF").

The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may provide touch driving signals to a plurality of touch electrodes of the touch sensing unit and may sense a change in capacitance between the touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate the presence and coordinates of an input based on the change in capacitance between the touch electrodes. The touch driver 400 may be formed as an Integrated Circuit (IC).

Fig. 2 is a cross-sectional view of the display device of fig. 1.

Referring to fig. 2, the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable or crimpable. For example, the substrate SUB may include a polymer resin such as polyimide ("PI"), but the disclosure is not limited thereto. In another example, the substrate SUB may include a glass material or a metal material.

The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors forming a pixel circuit of the pixel. The thin film transistor layer TFTL may further include gate lines, data lines, power lines, gate control lines, and fan-out lines connecting the display driver 200 and the data lines, and leads connecting the display driver 200 and the pad unit. The thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where the gate driver is formed at one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor of the thin film transistor layer TFTL, the gate line, the data line, and the power line may be disposed in the display area DA. The gate control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the sub-regions SBA.

The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements in which a pixel electrode, a light emitting layer, and a common electrode are sequentially stacked to emit light, and a pixel defining film defining pixels. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

For example, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. When the pixel electrode receives a voltage via the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer via the hole transporting layer and the electron transporting layer, respectively, and may be combined together in the organic light emitting layer to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode. However, the present disclosure is not limited to this example.

Alternatively, the light emitting element may be a quantum dot Light Emitting Diode (LED) including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

The encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EML, and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for capacitively sensing a touch input from a user and touch lines for connecting the touch electrodes and the touch driver 400. For example, the touch sensing unit TSU may sense a touch input from a user in a mutual capacitance manner or in a self capacitance manner.

In another example, the touch sensing unit TSU may be disposed on a separate substrate on the display unit DU. In this example, the substrate supporting the touch sensing unit TSU may be a base member for packaging the display unit DU.

The touch electrode of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to a plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength therethrough, and may block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced into the display device 10 from the outside, and thus may reduce reflected light of the external light. Accordingly, the color filter layer CFL can prevent any color distortion that may be caused by reflection of external light.

Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Accordingly, the thickness of the display device 10 can be reduced.

The sub-area SBA of the display panel 100 may extend from one side of the main area MA of the display panel 100. The sub-area SBA may comprise a flexible material that makes the sub-area SBA bendable, foldable or crimpable. For example, the sub-region SBA may be folded so as to overlap with the main region MA in the thickness direction (Z-axis direction). The sub-area SBA may include the display driver 200 and a pad unit electrically connected to the circuit board 300.

Fig. 3 is a plan view of a display panel of the display device of fig. 1.

Referring to fig. 3, the display unit DU may include a display area DA and a non-display area NDA.

The display area DA for displaying an image may be defined as a middle area of the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. The pixel SP may be defined as a minimum unit for emitting light.

The gate line GL may supply the gate signal received from the gate driver 210 to the pixel SP. The plurality of gate lines GL may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction crossing the X-axis direction.

The data line DL may supply the data voltage received from the display driver 200 to the pixel SP. The plurality of data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

The power supply line VL may supply the power supply voltage received from the display driver 200 to the pixel SP. Here, the power supply voltage includes a driving voltage, an initializing voltage, a reference voltage, and/or a low potential voltage. The plurality of power supply lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 210, a fan-out line sol, and a gate control line GCL. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL in a predetermined order.

The fanout line sol may extend from the display driver 200 to the display area DA. The fanout line sol may supply the data voltage received from the display driver 200 to the data line DL.

The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may provide the gate control signal received from the display driver 200 to the gate driver 210.

The sub-region SBA may include a display driver 200, a display pad region DPA, a first touch pad region TPA1, and a second touch pad region TPA2.

The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out line sol. The display driver 200 may supply the data voltage to the data line DL via the fan-out line sol. The data voltage may be supplied to the pixel SP, and the brightness of the pixel SP may be determined. The display driver 200 may provide a gate control signal to the gate driver 210 via the gate control line GCL.

The display pad region DPA, the first touch pad region TPA1, and the second touch pad region TPA2 may be disposed at edges of the sub-region SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 (see, e.g., fig. 1) via a low-resistance, high-reliability material such as an anisotropic conductive film ("ACF") or a self-assembled anisotropic conductive paste ("SAP").

The display pad area DPA may include a plurality of display pads DP. The display pad DP may be electrically connected to the graphics system via the circuit board 300. The display pad DP may be connected to the circuit board 300, and thus may receive digital video data and provide the digital video data to the display driver 200.

The first touch pad area TPA1 may be disposed at one side of the display pad area DPA, and may include a plurality of first touch pads TP1. The first touch pad TP1 may be electrically connected to a touch driver 400 (see, e.g., fig. 1) provided on the circuit board 300. The first touch pad TP1 may provide touch driving signals to the plurality of driving electrodes via the plurality of driving lines.

The second touch pad area TPA2 may be disposed at the other side of the display pad area DPA, and may include a plurality of second touch pads TP2. The second touch pad TP2 may be electrically connected to the touch driver 400 provided on the circuit board 300. The touch driver 400 may receive touch sensing signals via a plurality of sensing lines connected to the second touch pad TP2 and may sense a change in mutual capacitance between the driving electrode and the sensing electrode.

Fig. 4 is a sectional view showing a part of the display device of fig. 1, and fig. 5 is an enlarged sectional view of a region A1 of fig. 4.

Referring to fig. 4 and 5, a display panel 100 (see fig. 1, for example) of the display device 10 (see fig. 1, for example) may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML (see fig. 2), and an encapsulation layer TFEL.

The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable or crimpable. For example, the substrate SUB may include a polymer resin such as PI, but the present disclosure is not limited thereto. In another example, the substrate SUB may include a glass material or a metal material.

The thin film transistor layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing permeation of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

The light blocking layer BML may be disposed on the first buffer layer BF 1. For example, the light blocking layer BML may be formed to include a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, but the present disclosure is not limited thereto. In another example, the light blocking layer BML may be an organic film including a black pigment.

The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing permeation of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

The thin film transistor TFT may be disposed on the second buffer layer BF2, and may form a pixel circuit of a plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor. The thin film transistor TFT may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF 2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML in the thickness direction (Z-axis direction). The semiconductor region ACT may overlap the gate electrode GE in the thickness direction (Z-axis direction), and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be obtained by converting the material of the semiconductor region ACT into a conductor.

The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

The gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, and the drain electrode DE. For example, the gate insulating layer GI may cover the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2, and may insulate the semiconductor region ACT and the gate electrode GE.

The first interlayer insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may insulate the gate electrode GE and the capacitor electrode CPE.

The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD 1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

A second interlayer insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first interlayer insulating layer ILD 1. The second interlayer insulating layer ILD2 may insulate the capacitor electrode CPE and the first connection electrode CNE 1.

The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD 2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE 2. The first connection electrode CNE1 may be inserted into a contact hole of each of the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI, and thus may contact the drain electrode DE of the thin film transistor TFT.

The first passivation layer PAS1 may be disposed on the first connection electrode CNE1 and the second interlayer insulating layer ILD 2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may insulate the first connection electrode CNE1 and the second connection electrode CNE 2.

The second connection electrode CNE2 may be disposed on the first passivation layer PAS 1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the first pixel electrode AE1 of the first light emitting element ED 1. The second connection electrode CNE2 may be inserted into the contact hole of the first passivation layer PAS1, and thus may be in contact with the first connection electrode CNE 1.

The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS 1.

The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include first light emitting elements ED1, second light emitting elements ED2 and third light emitting elements ED3, residual patterns RP, a first insulating layer IL1, CAP layers, banks BNK, first organic patterns ELP1, second organic patterns ELP2 and third organic patterns ELP3, first electrode patterns CEP1, second electrode patterns CEP2 and third electrode patterns CEP3, first CAP patterns CLP1, second CAP patterns CLP2 and third CAP patterns CLP3, and first inorganic layers TL1, second inorganic layers TL2 and third inorganic layers TL3.

The display device 10 may include a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each of the plurality of pixels may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 defined by the bank BNK or the pixel defining film, and may emit light having a predetermined peak wavelength via the first emission area EA1, the second emission area EA2, and the third emission area EA 3. The first, second, and third emission areas EA1, EA2, and EA3 may be areas that output light generated by the first, second, and third light emitting elements ED1, ED2, and ED3 to the outside of the display device 10.

The first, second, and third emission areas EA1, EA2, and EA3 may each emit light having a predetermined peak wavelength to the outside of the display device 10. The first emission area EA1 may emit the first color light, the second emission area EA2 may emit the second color light, and the third emission area EA3 may emit the third color light. For example, the first color light may be red light having a peak wavelength of about 610 nanometers (nm) to about 650nm, the second color light may be green light having a peak wavelength of about 510nm to about 550nm, and the third color light may be blue light having a peak wavelength of about 440nm to about 480 nm. However, the present disclosure is not limited to this example.

For example, the third emission area EA3 may be larger in size than the first emission area EA1, and the first emission area EA1 may be larger in size than the second emission area EA 2. However, the present disclosure is not limited to this example. In another example, the first, second, and third emission areas EA1, EA2, and EA3 may have substantially the same size.

The first light emitting element ED1 may be disposed in the first emission area EA1 on the thin film transistor layer TFTL. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1. The second light emitting element ED2 may be disposed in the second emission area EA2 on the thin film transistor layer TFTL. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2. The third light emitting element ED3 may be disposed in the third emission area EA3 on the thin film transistor layer TFTL. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

The first, second, and third pixel electrodes AE1, AE2, AE3 may be disposed on the second passivation layer PAS 2. The first, second, and third pixel electrodes AE1, AE2, and AE3 may be connected to the drain electrode DE of the thin film transistor TFT via the first and second connection electrodes CNE1 and CNE 2. The first, second, and third pixel electrodes AE1, AE2, AE3 may be insulated from each other by a first insulating layer IL 1. For example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include at least one of Ag, cu, al, ni and lanthanum (La). In another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include a material such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or indium tin zinc oxide ("ITZO"). In still another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may have a stacked structure such as ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the residual pattern RP. The first insulating layer IL1 may cover edges of each of the first, second, and third pixel electrodes AE1, AE2, and AE3 and the residual pattern RP, and may expose portions of top surfaces of the first, second, and third pixel electrodes AE1, AE2, and AE 3. For example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE 1. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

Referring to fig. 5, the first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface BKS1 of the first bank BNK1, the side surface BKS2 of the second bank BNK2, and the side surface BKS3 of the third bank BNK 3.

The first insulating layer IL1 and the bank BNK may be etched by separate etching processes. The first insulating layer IL1 and the bank BNK may be etched using different photoresists as masks. The bank BNK may be etched using the first photoresist as a mask, and the first insulating layer IL1 may be etched using the second photoresist as a mask. The first photoresist may cover a top surface of the bank BNK. The second photoresist may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist may have a larger planar area than the first photoresist. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched through separate etching processes, damage to the residual pattern RP may be controlled, and the display device 10 may include a relatively thin residual pattern RP.

Referring to fig. 4 and 5, since the display device 10 (see, for example, fig. 1) includes the first insulating layer IL1 having the inclined side surface ILS and the relatively thin residual pattern RP, it is possible to prevent the first, second and third common electrodes CE1, CE2 and CE3 from being shorted. For example, the first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the first emission area EA1, and may extend to a side surface of each of the first and third banks BNK1 and BNK3 to be in contact with a side surface BKS1 of the first and third banks BNK1 and BNK 3. Accordingly, defects of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be prevented, and reliability can be improved.

The residual pattern RP may be disposed on an edge of each of the first, second, and third pixel electrodes AE1, AE2, and AE 3. The first insulating layer IL1 may not be in direct contact with the top surfaces of the first, second, and third pixel electrodes AE1, AE2, and AE3 due to the presence of the residual pattern RP. During fabrication of the display device 10, the residual pattern RP may be formed by removing the sacrificial layer (the sacrificial layer SFL of fig. 6) from above the first, second, and third pixel electrodes AE1, AE2, AE 3.

The first, second, and third light emitting layers EL1, EL2, and EL3 may be organic light emitting layers formed of an organic material, and may be formed on the first, second, and third pixel electrodes AE1, AE2, and AE3, respectively, via a deposition process. For example, during deposition of the first, second, and third light emitting layers EL1, EL2, and EL3, the organic material may be deposited in diagonal directions with respect to the top surface of the substrate SUB.

In the first emission area EA1, the first light emitting layer EL1 may be disposed on the first pixel electrode AE 1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1. In the second emission area EA2, the second light emitting layer EL2 may be directly disposed on the second pixel electrode AE 2. A portion of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1. In the third emission area EA3, the third light emitting layer EL3 may be directly disposed on the third pixel electrode AE 3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1.

The first common electrode CE1 may be disposed on the first light emitting layer EL1, the second common electrode CE2 may be disposed on the second light emitting layer EL2, and the third common electrode CE3 may be disposed on the third light emitting layer EL 3. The first, second, and third common electrodes CE1, CE2, and CE3 may include a transparent conductive material, and may transmit light generated by the first, second, and third light emitting layers EL1, EL2, and EL3 therethrough. The first, second and third common electrodes CE1, CE2 and CE3 may be in contact with the side surfaces BKS1 and BNK3 of the first and third banks BNK1 and BNK3 and may be electrically connected through the first and third banks BNK1 and BNK 3. For example, the first common electrode CE1 may receive a common voltage or a low potential voltage.

The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from one of the plurality of thin film transistors TFT, and the first common electrode CE1 may receive a common voltage or a cathode voltage. In this case, when a potential difference is generated between the first pixel electrode AE1 and the first common electrode CE1, holes and electrons move to the first light emitting layer EL1 via the hole transporting layer and the electron transporting layer, respectively, and as a result, the first light emitting layer EL1 emits light.

The CAP layer CAP may be disposed on the first, second, and third common electrodes CE1, CE2, and CE3. The CAP layer CAP may include an inorganic insulating material, and may cover the first, second, and third common electrodes CE1, CE2, and CE3. The CAP layer CAP may prevent the first, second, and third light emitting elements ED1, ED2, and ED3 from being damaged by external air. For example, the CAP layer CAP may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

The bank BNK may be disposed on the first insulating layer IL1 to define a first emission area EA1, a second emission area EA2, and a third emission area EA3. The bank BNK may surround the first, second, and third emission areas EA1, EA2, and EA3 in a plan view. The plurality of dike BNKs may include a first dike BNK1, a second dike BNK2, and a third dike BNK3.

The third bank BNK3 may be disposed on the first insulating layer IL1, the first bank BNK1 may be disposed on the third bank BNK3, and the second bank BNK2 may be disposed on the first bank BNK 1. Referring to fig. 5, the side surface BKS1 of the first bank BNK1, the side surface BKS2 of the second bank BNK2, and the side surface BKS3 of the third bank BNK3 may be spaced apart from the side surface ILs of the first insulating layer IL 1. The side surface BKS1 of the first bank BNK1 may be recessed inwardly from the side surface BKS2 of the second bank BNK2 and from the side surface BKS3 of the third bank BNK3. That is, the side surface BKS2 of the second bank BNK2 and the side surface BKS3 of the third bank BNK3 may protrude from the side surface BKS1 of the first bank BNK1 toward the first emission area EA1, and thus may include protruding tips (hereinafter, also referred to as tips). Thus, an undercut may be formed under the tip of the second dike BNK 2. The first bank BNK1 may be thicker than each of the second bank BNK2 and the third bank BNK3.

At least one of the first, second and third dykes BNK1, BNK2 and BNK3 may comprise a different metallic material than the other dyke(s) of the first, second and third dykes BNK1, BNK2 and BNK 3. The first bank BNK1 may have a different etch rate than the second and third banks BNK2 and BNK 3. For example, in the wet etching process, during formation of the first, second and third emission areas EA1, EA2 and EA3, the first bank BNK1 may be etched faster than the second and third banks BNK2 and BNK3 and in a larger amount than the second and third banks BNK2 and BNK 3. Therefore, the shape of the side surfaces BKS1, BKS2 and BKS3 of the first, second and third banks BNK1, BNK2 and BNK3 may be determined by the difference in etching rate between the first, second and third banks BNK1, BNK2 and BNK 3. The first bank BNK1 may include a metal material having high conductivity, and the second and third banks BNK2 and BNK3 may include a metal material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second and third banks BNK2 and BNK3 may include titanium (Ti). However, the present disclosure is not limited to this example.

Referring to fig. 4 and 5, the bank BNK may define openings therein forming the first, second, and third emission areas EA1, EA2, and EA3, and may overlap the light blocking member BM of the color filter layer CFL in a plan view. The first and third banks BNK1 and BNK3 may electrically connect the first, second and third common electrodes CE1, CE2 and CE3 spaced apart from each other. The second bank BNK2 may include a metal material having a low reflectivity, and thus can reduce reflection of external light.

The bank BNK may form the first, second, and third emission areas EA1, EA2, and EA3 via a mask process, and the first, second, and third emission layers EL1, EL2, and EL3 may be formed in the first, second, and third emission areas EA1, EA2, and EA3, respectively. The masking process may require an excessively large non-display area NDA (see, e.g., fig. 1) for mounting the mask structure and for distribution control (distribution control). If the mask process can be minimized, a structure for mounting the mask may not be provided, and the size of the non-display area NDA for distribution control may be minimized.

The first, second, and third light emitting elements ED1, ED2, and ED3 may be formed through a deposition process and an etching process, not through a mask process. Since at least one of the first, second and third banks BNK1, BNK2 and BNK3 includes a different metal material from the other bank(s) of the first, second and third banks BNK1, BNK2 and BNK3, an inner sidewall of each of the plurality of banks BNK may have a tip, and different layers may be separately formed in each of the first, second and third emission areas EA1, EA2 and EA3 via a deposition process. For example, the first light emitting layer EL1 and the first organic pattern ELP1 may be formed of the same organic material by a deposition process without using a mask, and may be cut and separated from each other by a tip on an inner sidewall of each of the plurality of bank BNKs. The first light emitting layer EL1 may be disposed in the first emission area EA1, and the first organic pattern ELP1 may be disposed on the bank BNK between the first emission area EA1, the second emission area EA2, and the third emission area EA 3.

The organic material for forming the first light emitting layer EL1 may be deposited on the entire surface of the display device 10 and may be removed from the second and third emission areas EA2 and EA 3. The organic material for forming the second light emitting layer EL2 may be deposited on the entire surface of the display device 10 and may be removed from the first and third emission areas EA1 and EA 3. The organic material for forming the third light emitting layer EL3 may be deposited on the entire surface of the display device 10 and may be removed from the first and second emission areas EA1 and EA 2. Thus, in the different emission regions, different organic layers may be formed through a deposition process and an etching process, instead of being formed through a mask process. Since unnecessary processes may be omitted, the manufacturing cost of the display device 10 may be reduced, and the size of the non-display area NDA may be minimized.

The first organic pattern ELP1 may include the same organic material as the first light emitting layer EL1, and may be disposed on the second bank BNK 2. The first organic pattern ELP1 may cover a side surface BKS2 of a portion of the second bank BNK2 adjacent to the first emission area EA 1. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited by the same process, and may be cut by tips formed on the inner sidewall of each of the plurality of banks BNK and separated from each other. Accordingly, the first organic pattern ELP1 may be disposed on the second bank BNK2 in regions other than the first, second, and third emission regions EA1, EA2, and EA 3.

The first electrode pattern CEP1 may include the same metal material as the first common electrode CE1, and may be disposed on the first organic pattern ELP 1. The first electrode pattern CEP1 may cover a side surface of a portion of the first organic pattern ELP1 adjacent to the first emission area EA 1. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in regions other than the first, second and third emission regions EA1, EA2 and EA 3.

The first CAP pattern CLP1 may include the same inorganic material as the CAP layer CAP, and may be disposed on the first electrode pattern CEP 1. The first cover pattern CLP1 may cover a side surface of a portion of the first electrode pattern CEP1 adjacent to the first emission area EA 1. The CAP layer CAP and the first CAP pattern CLP1 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, the first cover pattern CLP1 may be disposed on the first electrode pattern CEP1 in regions other than the first, second and third emission regions EA1, EA2 and EA 3.

In the first emission area EA1, the first inorganic layer TL1 may be disposed on a portion of the CAP layer CAP in the first emission area EA1 and on the first CAP pattern CLP 1. The first inorganic layer TL1 may cover the side surface BKS1 of the portion of the first bank BNK1 surrounding the first emission area EA 1. The first inorganic layer TL1 may include an inorganic material, and may prevent oxygen or moisture from penetrating the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

The second organic pattern ELP2 may include the same organic material as the second light emitting layer EL2, and may be disposed on the first inorganic layer TL 1. The second organic pattern ELP2 may cover the second bank BNK2, the first organic pattern ELP1, the first electrode pattern CEP1, the first cover pattern CLP1, and a side surface of a portion of the first inorganic layer TL1 adjacent to the second emission area EA 2. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited by the same process, and may be cut by tips formed on the inner sidewalls of each of the plurality of banks BNK. Accordingly, the second organic pattern ELP2 may be disposed on the first inorganic layer TL1 in a region adjacent to the second or third emission region EA2 or EA 3.

The second electrode pattern CEP2 may include the same material as the second common electrode CE2, and may be disposed on the second organic pattern ELP 2. The second electrode pattern CEP2 may cover a side surface of a portion of the second organic pattern ELP2 adjacent to the second emission region EA 2. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in a region adjacent to the second emission region EA2 or the third emission region EA 3.

The second CAP pattern CLP2 may include the same inorganic material as the CAP layer CAP, and may be disposed on the second electrode pattern CEP 2. The second cover pattern CLP2 may cover a side surface of a portion of the second electrode pattern CEP2 adjacent to the second emission region EA 2. The CAP layer CAP and the second CAP pattern CLP2 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in a region adjacent to the second emission region EA2, the second cover pattern CLP2 may be disposed on the second electrode pattern CEP 2.

The second inorganic layer TL2 may be disposed on a portion of the CAP layer CAP in the second emission area EA2 and on the second CAP pattern CLP 2. The second inorganic layer TL2 may cover the side surface BKS1 of the portion of the first dike BNK1 surrounding the second emission area EA 2. The second inorganic layer TL2 may include an inorganic material, and may prevent oxygen or moisture from penetrating the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. For example, the second inorganic layer TL2 may be formed from one of the plurality of aforementioned exemplary materials used to form the first inorganic layer TL 1.

The third organic pattern ELP3 may include the same organic material as the third light emitting layer EL3, and may be disposed on the second inorganic layer TL 2. The third organic pattern ELP3 may cover the second bank BNK2, the first organic pattern ELP1, the first electrode pattern CEP1, the first cover pattern CLP1, the first inorganic layer TL1, the second organic pattern ELP2, the second electrode pattern CEP2, the second cover pattern CLP2, and a side surface of a portion of the second inorganic layer TL2 adjacent to the third emission region EA 3. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited by the same process, and may be cut by tips formed on the inner sidewalls of each of the plurality of banks BNK. Accordingly, in a region adjacent to the third emission region EA3, the third organic pattern ELP3 may be disposed on the second inorganic layer TL 2.

The third electrode pattern CEP3 may include the same metal material as the third common electrode CE3, and may be disposed on the third organic pattern ELP 3. The third electrode pattern CEP3 may cover a side surface of a portion of the third organic pattern ELP3 adjacent to the third emission region EA 3. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in a region adjacent to the third emission region EA3, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP 3.

The third CAP pattern CLP3 may include the same inorganic material as the CAP layer CAP, and may be disposed on the third electrode pattern CEP 3. The third cover pattern CLP3 may cover a side surface of a portion of the third electrode pattern CEP3 adjacent to the third emission region EA 3. The CAP layer CAP and the third CAP pattern CLP3 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in an area adjacent to the third emission area EA3, the third cover pattern CLP3 may be disposed on the third electrode pattern CEP 3.

The third inorganic layer TL3 may be disposed on a portion of the CAP layer CAP in the third emission region EA3 and on the third CAP pattern CLP 3. The third inorganic layer TL3 may cover the side surface BKS1 of the portion of the first dike BNK1 surrounding the third emission area EA 3. The third inorganic layer TL3 may include an inorganic material, and may prevent oxygen or moisture from penetrating the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. For example, the third inorganic layer TL3 may be formed from one of the plurality of aforementioned exemplary materials used to form the first inorganic layer TL 1.

The encapsulation layer TFEL may be disposed on the first, second, and third inorganic layers TL1, TL2, and TL3 to cover the light emitting element layer EML (see fig. 2). The encapsulation layer TFEL may include a first encapsulation layer TFE1 and a second encapsulation layer TFE2.

The first encapsulation layer TFE1 may be disposed on the first, second, and third inorganic layers TL1, TL2, and TL3 to planarize the top of the light emitting element layer EML. The first encapsulation layer TFE1 may include an organic material, and may protect the light emitting element layer EML from foreign matter such as dust. For example, the first encapsulation layer TFE1 may include an organic film formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a PI resin. The first encapsulation layer TFE1 may be formed by curing a monomer or applying a polymer.

The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE 1. The second encapsulation layer TFE2 may include an inorganic material, and may prevent oxygen or moisture from penetrating the light emitting element layer EML. For example, the second encapsulation layer TFE2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may have an insulating function and an optical function. The third buffer layer BF3 may include at least one inorganic film. The third buffer layer BF3 may be optional.

The bridge electrode BRG may be disposed on the third buffer layer BF 3. The bridge electrode BRG may be disposed in a different layer from the touch electrode TE, and may electrically connect a plurality of touch electrodes TE to each other.

The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF 3. The second insulating layer IL2 may have an insulating function and an optical function. For example, the second insulating layer IL2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

The touch electrode TE may be disposed on the second insulating layer IL 2. The touch electrode TE may include a driving electrode and a sensing electrode, and may sense a change in mutual capacitance between the driving electrode and the sensing electrode. The touch electrode TE may not overlap the first, second, and third emission areas EA1, EA2, and EA3 in a plan view. The touch electrode TE may be formed as a single layer including Mo, ti, cu, al or ITO, or as a stack of Al and Ti (e.g., ti/Al/Ti), a stack of Al and ITO (e.g., ITO/Al/ITO), a layer of silver (Ag) -palladium (Pd) -copper (Cu) ("APC") alloy, or a stack of APC alloy and ITO (e.g., ITO/APC/ITO).

The third insulating layer IL3 may be disposed on the touch electrode TE and the second insulating layer IL 2. The third insulating layer IL3 may have an insulating function and an optical function. The third insulating layer IL3 may be formed of one of the plurality of aforementioned exemplary materials for forming the second insulating layer IL 2.

The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a light blocking member BM, a plurality of color filters CF, and a planarization layer OC.

The light blocking member BM may be disposed on the third insulating layer IL3, and may surround the first, second, and third optical regions OPT1, OPT2, and OPT3. The light blocking member BM may overlap the touch electrode TE in a plan view. The light blocking member BM may include a light absorbing material, and may prevent reflection of light. For example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may be carbon black or a metal oxide such as titanium (Ti) black, the organic black pigment may be at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be c.i. pigment blue. However, the present disclosure is not limited thereto. The light blocking member BM may improve color reproducibility of the display device 10 by preventing visible light from transmitting through the regions between the first, second, and third emission regions EA1, EA2, and EA3 to cause color mixing.

The color filters CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first, second, and third color filters CF1, CF2, and CF3 may be disposed on the third insulating layer IL3 to correspond to the first, second, and third emission areas EA1, EA2, and EA3, respectively.

The first color filter CF1 may be disposed in the first emission area EA1 on the third insulating layer IL 3. In a plan view, the first color filter CF1 may correspond to the first emission area EA 1. The edge of the first color filter CF1 may cover a portion of the top surface of the light blocking member BM, but the present disclosure is not limited thereto. The first color filter CF1 may selectively transmit a first color light (e.g., red light) therethrough, and may block or absorb a second color light (e.g., green light) and a third color light (e.g., blue light). For example, the first color filter CF1 may be a red color filter, and may include a red colorant.

The second color filter CF2 may be disposed in the second emission area EA2 on the third insulating layer IL 3. In a plan view, the second color filter CF2 may correspond to the second emission area EA 2. The edge of the second color filter CF2 may cover a portion of the top surface of the light blocking member BM, but the present disclosure is not limited thereto. The second color filter CF2 may selectively transmit the second color light (e.g., green light) therethrough, and may block or absorb the first color light (e.g., red light) and the third color light (e.g., blue light). For example, the second color filter CF2 may be a green color filter, and may include a green colorant.

The third color filter CF3 may be disposed in the third emission area EA3 on the third insulating layer IL 3. In a plan view, the third color filter CF3 may correspond to the third emission area EA 3. An edge of the third color filter CF3 may cover a portion of the top surface of the light blocking member BM, but the present disclosure is not limited thereto. The third color filter CF3 may selectively transmit a third color light (e.g., blue light) therethrough, and may block or absorb the first color light (e.g., red light) and the second color light (e.g., green light). For example, the third color filter CF3 may be a blue color filter, and may include a blue colorant.

The first, second, and third color filters CF1, CF2, and CF3 may reduce reflection of external light by absorbing some of the external light. Accordingly, the first, second, and third color filters CF1, CF2, and CF3 may prevent color distortion that may be caused by reflection of external light.

The planarization layer OC may be disposed on the light blocking member BM and the first, second and third color filters CF1, CF2 and CF 3. The planarization layer OC may planarize the top of the color filter layer CFL. For example, the planarization layer OC may include an organic insulating material.

Fig. 6 to 15 are sectional views showing examples of how the display device of fig. 4 is manufactured.

Referring to fig. 6, the first, second, and third pixel electrodes AE1, AE2, and AE3 may be disposed to be spaced apart from each other on the thin film transistor layer TFTL. For example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include at least one of Ag, cu, al, ni and La. In another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include ITO, IZO, or ITZO. In another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may have a stacked structure such as ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The sacrificial layer SFL may be disposed on the first, second, and third pixel electrodes AE1, AE2, AE 3. The sacrificial layer SFL may be disposed between top surfaces of the first, second, and third pixel electrodes AE1, AE2, AE3 and the first insulating layer IL 1. The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide ("IGZO"), zinc tin oxide ("ZTO"), and IZO.

The first insulating layer IL1 may be disposed on the thin film transistor layer TFTL and the sacrificial layer SFL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

The third bank BNK3 may be disposed on the first insulating layer IL1, the first bank BNK1 may be disposed on the third bank BNK3, and the second bank BNK2 may be disposed on the first bank BNK 1. The first bank BNK1 may be thicker than the second bank BNK2 or the third bank BNK3.

The first photoresist PR1 may be disposed on the second bank BNK2 so as not to overlap the first pixel electrode AE1 in a plan view. The first photoresist PR1 may be provided in a region other than a region in which the first emission region EA1 (see fig. 4) is to be formed.

Referring to fig. 7, the second, first and third banks BNK2, BNK1 and BNK3 may be sequentially etched, thereby forming the first hole HOL1. The first hole HOL1 may overlap with the first emission area EA1 (see fig. 4). The first, second and third banks BNK1, BNK2 and BNK3 may be etched by at least one of dry etching and wet etching. For example, the first, second and third banks BNK1, BNK2 and BNK3 may be primarily etched by dry etching, and the first, second and third banks BNK1, BNK2 and BNK3 may be secondarily etched by wet etching, but the disclosure is not limited thereto. At least one of the first, second and third banks BNK1, BNK2 and BNK3 may comprise a different metal material than the other bank(s) of the first, second and third banks BNK1, BNK2 and BNK3 and may have a different etch rate than the other bank(s) of the first, second and third banks BNK1, BNK2 and BNK3. In the wet etching process, the first bank BNK1 may be etched faster than the second and third banks BNK2 and BNK3 and etched in a larger amount than the second and third banks BNK2 and BNK3. Therefore, the shape of the side surfaces BKS1, BKS2 and BKS3 of the first, second and third banks BNK1, BNK2 and BNK3 may be determined by the difference in etching rate between the first, second and third banks BNK1, BNK2 and BNK3. The second and third dykes BNK2 and BNK3 may comprise tips protruding from the first dykes BNK1 towards the first holes HOL1. The side surface BKS1 of the first bank BNK1 may be recessed inward from the side surface BKS2 of the second bank BNK2 and the side surface BKS3 of the third bank BNK3. An undercut may be formed under the tip of the second bank BNK 2. The first bank BNK1 may be thicker than each of the second bank BNK2 and the third bank BNK3.

The first bank BNK1 may include a metal material having high conductivity, and the second and third banks BNK2 and BNK3 may include a metal material having low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second and third banks BNK2 and BNK3 may include titanium (Ti). However, the present disclosure is not limited to this example.

Referring to fig. 8, the first insulating layer IL1 may be etched using a second photoresist PR2 different from the first photoresist PR1 (see, for example, fig. 7). The second photoresist PR2 may further cover a side surface of each of the plurality of banks BNK as compared to the first photoresist PR 1. The second photoresist PR2 may cover a side surface BKS1 of the first bank BNK1, a side surface BKS2 of the second bank BNK2, and a side surface BKS3 of the third bank BNK 3. The second photoresist PR2 may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist PR2 may have a larger planar area than the first photoresist PR 1. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist PR2 may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched through separate etching processes, damage to the residual pattern RP (see fig. 4) may be controlled, and the display device 10 (see fig. 1, for example) may include a relatively thin residual pattern RP.

Referring to fig. 9, the first insulating layer IL1 and the sacrificial layer SFL may be etched by at least one of dry etching and wet etching. For example, the first insulating layer IL1 may be etched by dry etching, and the sacrificial layer SFL may be etched by wet etching. However, the present disclosure is not limited to this example. As the first insulating layer IL1 and the sacrificial layer SFL are etched, at least a portion of the top surface of the first pixel electrode AE1 may be exposed. In the wet etching process, the sacrificial layer SFL may be etched in a larger amount than the first insulating layer IL 1. As the sacrificial layer SFL is etched, the residual pattern RP may remain between the first insulating layer IL1 and the first pixel electrode AE 1. Accordingly, a side surface of each of the plurality of residual patterns RP may be recessed inward from the side surface ILs of the first insulating layer IL 1.

The first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The tilt angle of the side surface ILs of the first insulating layer IL1 may be determined by the tilt angle of the second photoresist PR 2. For example, if the slope of the side surface of the second photoresist PR2 is steep (e.g., almost vertical), the side surface ILs of the first insulating layer IL1 may have a steep slope. In contrast, if the slope of the side surface of the second photoresist PR2 is gentle (e.g., almost flat), the side surface ILs of the first insulating layer IL1 may have a gentle slope. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface BKS1 of the first bank BNK1, the side surface BKS2 of the second bank BNK2, and the side surface BKS3 of the third bank BNK 3.

Referring to fig. 10, after etching the first insulating layer IL1 and the sacrificial layer SFL, the second photoresist PR2 may be removed by a strip (strip) process (see fig. 9).

Referring to fig. 11, in the first emission area EA1 (see fig. 4), the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE 1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1.

The organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device 10 (see, for example, fig. 1). The first organic pattern ELP1 may include the same organic material as the first light emitting layer EL1, and the first organic pattern ELP1 may be disposed on the second bank BNK 2. The first organic pattern ELP1 may cover a side surface BKS2 of a portion of the second bank BNK2 adjacent to the first emission area EA1 (see fig. 10). The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited by the same process, and may be cut by tips formed on the inner sidewall of each of the plurality of banks BNK and separated from each other. Accordingly, the first organic pattern ELP1 may be disposed on the second bank BNK2 in an area other than the first emission area EA 1.

The first common electrode CE1 may be disposed on the first light emitting layer EL 1. The first common electrode CE1 may include a transparent conductive material, and may transmit light generated by the first light emitting layer EL1 therethrough. The first common electrode CE1 may be in contact with a side surface BKS1 (see fig. 10) of the first bank BNK1 and a top surface of the third bank BNK 3. Accordingly, the first light emitting element ED1 may be formed in the first hole HOL1, and may emit light via the first emission area EA 1.

A metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device 10. The first electrode pattern CEP1 may include the same metal material as the first common electrode CE1, and may be disposed on the first organic pattern ELP 1. The first electrode pattern CEP1 may cover a side surface of a portion of the first organic pattern ELP1 adjacent to the first emission area EA 1. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area other than the first emission area EA 1.

The CAP layer CAP may be disposed on the first common electrode CE 1. The CAP layer CAP may include an inorganic insulating material, and may cover the first light emitting element ED1. The CAP layer CAP may prevent the first common electrode CE1 from being damaged by external air. For example, the CAP layer CAP may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

An inorganic material for forming the CAP layer CAP and the first CAP pattern CLP1 may be deposited on the entire surface of the display device 10. The first CAP pattern CLP1 may include the same inorganic material as the CAP layer CAP, and may be disposed on the first electrode pattern CEP 1. The first cover pattern CLP1 may cover a side surface of a portion of the first electrode pattern CEP1 adjacent to the first emission area EA 1. The CAP layer CAP and the first CAP pattern CLP1 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in an area other than the first emission area EA1, the first cover pattern CLP1 may be disposed on the first electrode pattern CEP 1.

The first inorganic layer TL1 may be disposed on a portion of the CAP layer CAP in the first emission area EA1 and on the first CAP pattern CLP 1. The first inorganic layer TL1 may cover the side surface BKS1 of the portion of the first bank BNK1 surrounding the first emission area EA 1. The first inorganic layer TL1 may include an inorganic material, and may prevent oxygen or moisture from penetrating the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. For example, the first inorganic layer TL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the present disclosure is not limited thereto.

Referring to fig. 12, the second hole HOL2 may overlap the second emission area EA 2. The second hole HOL2 may be formed by sequentially etching the first inorganic layer TL1, the first cap pattern CLP1, the first electrode pattern CEP1, the first organic pattern ELP1, the second bank BNK2, the first bank BNK1, the third bank BNK3, the first insulating layer IL1, and the sacrificial layer SFL. During the formation of the second hole HOL2, the first, second and third dykes BNK1, BNK2 and BNK3, the first insulating layer IL1 and the sacrificial layer SFL may be etched in substantially the same manner as described above with reference to fig. 7 to 9.

In the second emission area EA2 (see fig. 4), the second light emitting layer EL2 may be directly disposed on the second pixel electrode AE 2. A portion of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1.

The organic material for forming the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited on the entire surface of the display device 10 (see, for example, fig. 1). The second organic pattern ELP2 may include the same organic material as the second light emitting layer EL2, and may be disposed on the first inorganic layer TL 1. The second organic pattern ELP2 may cover the second bank BNK2, the first organic pattern ELP1, the first electrode pattern CEP1, the first cover pattern CLP1, and a side surface of a portion of the first inorganic layer TL1 adjacent to the second emission area EA 2. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited by the same process, and may be cut by tips formed on the inner sidewalls of each of the plurality of banks BNK. Accordingly, the second organic pattern ELP2 may be disposed on the first inorganic layer TL1 in regions other than the second emission region EA 2.

The second common electrode CE2 may be disposed on the second light emitting layer EL 2. The second common electrode CE2 may include a transparent conductive material, and may transmit light generated by the second light emitting layer EL2 therethrough. The second common electrode CE2 may be in contact with the side surface BKS1 (see fig. 10) of the first bank BNK1 and the top surface of the third bank BNK 3. Accordingly, the second light emitting layer EL2 may be formed in the second hole HOL2, and may emit light via the second emission area EA 2.

A metal material for forming the second common electrode CE2 and the second electrode pattern CEP2 may be deposited on the entire surface of the display device 10. The second electrode pattern CEP2 may include the same metal material as the second common electrode CE2, and may be disposed on the second organic pattern ELP 2. The second electrode pattern CEP2 may cover a side surface of a portion of the second organic pattern ELP2 adjacent to the second emission region EA 2. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in regions other than the second emission region EA2, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP 2.

The CAP layer CAP may be disposed on the second common electrode CE 2. The CAP layer CAP may include an inorganic insulating material, and may cover the second light emitting element ED2. The CAP layer CAP may prevent the second light emitting element ED2 from being damaged by external air.

An inorganic material for forming the CAP layer CAP and the second CAP pattern CLP2 may be deposited on the entire surface of the display device 10. The second CAP pattern CLP2 may include the same inorganic material as the CAP layer CAP, and may be disposed on the second electrode pattern CEP 2. The second cover pattern CLP2 may cover a side surface of a portion of the second electrode pattern CEP2 adjacent to the second emission region EA 2. The CAP layer CAP and the second CAP pattern CLP2 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in an area other than the second emission area EA2, the second cover pattern CLP2 may be disposed on the second electrode pattern CEP 2.

Referring to fig. 13, the third hole HOL3 may overlap with the third emission area EA3 (see fig. 4). The third hole HOL3 may be formed by sequentially etching the second inorganic layer TL2, the second cap pattern CLP2, the second electrode pattern CEP2, the second organic pattern ELP2, the first inorganic layer TL1, the first cap pattern CLP1, the first electrode pattern CEP1, the first organic pattern ELP1, the second bank BNK2, the first bank BNK1, the third bank BNK3, the first insulating layer IL1, and the sacrificial layer SFL (see fig. 12). During the formation of the third hole HOL3, the first, second and third dykes BNK1, BNK2 and BNK3, the first insulating layer IL1 and the sacrificial layer SFL may be etched in substantially the same manner as described above with reference to fig. 7 to 9.

In the third emission area EA3, the third light emitting layer EL3 may be directly disposed on the third pixel electrode AE 3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1.

The organic material for forming the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited on the entire surface of the display device 10 (see, for example, fig. 1). The third organic pattern ELP3 may include the same organic material as the third light emitting layer EL3, and may be disposed on the second inorganic layer TL 2. The third organic pattern ELP3 may cover the second bank BNK2, the first organic pattern ELP1, the first electrode pattern CEP1, the first cover pattern CLP1, the first inorganic layer TL1, the second organic pattern ELP2, the second electrode pattern CEP2, the second cover pattern CLP2, and a side surface of a portion of the second inorganic layer TL2 adjacent to the third emission region EA 3. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited by the same process, and may be cut by tips formed on the inner sidewalls of each of the plurality of banks BNK. Accordingly, in regions other than the third emission region EA3, the third organic pattern ELP3 may be disposed on the second inorganic layer TL 2.

The third common electrode CE3 may be disposed on the third light emitting layer EL 3. The third common electrode CE3 may include a transparent conductive material, and may transmit light generated by the third light emitting layer EL3 therethrough. The third common electrode CE3 may be in contact with a side surface BKS1 (see fig. 10) of the first bank BNK1 and a top surface of the third bank BNK 3. Accordingly, the third light emitting layer EL3 may be formed in the third hole HOL3, and may emit light via the third emission area EA 3.

A metal material for forming the third common electrode CE3 and the third electrode pattern CEP3 may be deposited on the entire surface of the display device 10. The third electrode pattern CEP3 may include the same metal material as the third common electrode CE3, and may be disposed on the third organic pattern ELP 3. The third electrode pattern CEP3 may cover a side surface of a portion of the third organic pattern ELP3 adjacent to the third emission region EA 3. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in regions other than the third emission region EA3, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP 3.

The CAP layer CAP may be disposed on the third common electrode CE 3. The CAP layer CAP may include an inorganic insulating material, and may cover the third light emitting element ED3. The CAP layer CAP can prevent the third light emitting element ED3 from being damaged by the outside air.

An inorganic material for forming the CAP layer CAP and the third CAP pattern CLP3 may be deposited on the entire surface of the display device 10. The third CAP pattern CLP3 may include the same inorganic material as the CAP layer CAP, and may be disposed on the third electrode pattern CEP 3. The third cover pattern CLP3 may cover a side surface of a portion of the third electrode pattern CEP3 adjacent to the third emission region EA 3. The CAP layer CAP and the third CAP pattern CLP3 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. Accordingly, in an area other than the third emission area EA3, the third cover pattern CLP3 may be disposed on the third electrode pattern CEP 3.

Referring to fig. 14, the third inorganic layer TL3, the third cap pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be sequentially etched in the first emission region EA1 (see fig. 4), the region adjacent to the first emission region EA1, the second emission region EA2 (see fig. 4), and the region adjacent to the second emission region EA 2. The third inorganic layer TL3, the third cover pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may remain in regions adjacent to the third emission region EA 3. The third inorganic layer TL3, the third cover pattern CLP3, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by at least one of dry etching and wet etching.

Referring to fig. 15, the second inorganic layer TL2, the second cap pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be sequentially etched in the first emission region EA1 (see fig. 4) and regions adjacent to the first emission region EA 1. The second inorganic layer TL2, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may remain in regions adjacent to the second and third emission regions EA2 (see fig. 4) and EA3 (see fig. 4). The second inorganic layer TL2, the second cover pattern CLP2, the second electrode pattern CEP2, and the second organic pattern ELP2 may be etched by at least one of dry etching and wet etching.

Fig. 16 to 18 are sectional views showing another example of how the display device of fig. 4 is manufactured. Fig. 16 to 18 show a manufacturing process that may replace the manufacturing process described above with reference to fig. 7 to 9. For example, fig. 16 illustrates a manufacturing process that may be performed after the manufacturing process of fig. 6, and fig. 18 illustrates a manufacturing process that may be performed before the manufacturing process of fig. 10.

Referring to fig. 16, a first photoresist PR1 may be disposed on the second bank BNK2 so as not to overlap the first pixel electrode AE1 in a plan view. The first photoresist PR1 may be provided in a region other than the region in which the first emission region EA1 is to be formed.

The second, first and third banks BNK2, BNK1 and BNK3 may be etched in order, thereby forming the first hole HOL1. The first hole HOL1 may overlap the first emission area EA 1. The first, second and third banks BNK1, BNK2 and BNK3 may be etched by at least one of dry etching and wet etching. For example, the first, second, and third banks BNK1, BNK2, and BNK3 may be etched by dry etching, but the disclosure is not limited thereto. In the dry etching process, the first, second and third banks BNK1, BNK2 and BNK3 may have substantially the same etching rate. Thus, the second bank BNK2 may be etched earlier than the first bank BNK1 and in a smaller amount than the first bank BNK1, and the first bank BNK1 may be etched earlier than the third bank BNK3 and in a larger amount than the third bank BNK3. The side surface BKS1 of the first bank BNK1, the side surface BKS2 of the second bank BNK2, and the side surface BKS3 of the third bank BNK3 may be connected to each other.

Referring to fig. 17, the first insulating layer IL1 may be etched using a second photoresist PR2 different from the first photoresist PR1 (see fig. 16). The second photoresist PR2 may further cover a side surface of each of the plurality of banks BNK as compared to the first photoresist PR 1. The second photoresist PR2 may cover a side surface BKS1 of the first bank BNK1, a side surface BKS2 of the second bank BNK2, and a side surface BKS3 of the third bank BNK 3. The second photoresist PR2 may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist PR2 may have a larger planar area than the first photoresist PR 1. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist PR2 may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched through separate etching processes, damage to the residual pattern RP (see fig. 4) may be controlled, and the display device 10 (see fig. 1, for example) may include a relatively thin residual pattern RP.

Referring to fig. 18, the first insulating layer IL1 may be etched by at least one of dry etching and wet etching. For example, the first insulating layer IL1 may be etched by dry etching, but the present disclosure is not limited thereto. As the first insulating layer IL1 is etched, a portion of the top surface of the sacrificial layer SFL may be exposed.

The first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The tilt angle of the side surface ILs of the first insulating layer IL1 may be determined by the tilt angle of the second photoresist PR2. For example, if the slope of the side surface of the second photoresist PR2 is steep (e.g., almost vertical), the side surface ILs of the first insulating layer IL1 may have a steep slope. In contrast, if the slope of the side surface of the second photoresist PR2 is gentle (e.g., almost flat), the side surface ILs of the first insulating layer IL1 may have a gentle slope. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface BKS1 of the first bank BNK1, the side surface BKS2 of the second bank BNK2, and the side surface BKS3 of the third bank BNK 3.

After etching of the first insulating layer IL1, the second photoresist PR2 may be removed by a stripping process. For example, after the removal of the second photoresist PR2, the side surface BKS1 of the first bank BNK1 and the sacrificial layer SFL may be etched by wet etching, but the disclosure is not limited thereto. At least one of the first, second and third banks BNK1, BNK2 and BNK3 may comprise a different metal material than the other bank(s) of the first, second and third banks BNK1, BNK2 and BNK3 and may have a different etch rate than the other bank(s) of the first, second and third banks BNK1, BNK2 and BNK 3. In the wet etching process, the first bank BNK1 may be etched faster than the second and third banks BNK2 and BNK3 and etched in a larger amount than the second and third banks BNK2 and BNK 3. Therefore, the shape of the side surfaces BKS1, BKS2 and BKS3 of the first, second and third banks BNK1, BNK2 and BNK3 may be determined by the difference in etching rate between the first, second and third banks BNK1, BNK2 and BNK 3. The second and third dykes BNK2 and BNK3 may comprise tips protruding from the first dykes BNK1 towards the first holes HOL 1. The side surface BKS1 of the first bank BNK1 may be recessed inward from the side surface BKS2 of the second bank BNK2 and the side surface BKS3 of the third bank BNK 3. An undercut may be formed under the tip of the second bank BNK 2. The first bank BNK1 may be thicker than each of the second bank BNK2 and the third bank BNK 3.

The first bank BNK1 may comprise a metal material having a high conductivity and the second bank BNK2 may comprise a metal material having a low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second and third banks BNK2 and BNK3 may include titanium (Ti). However, the present disclosure is not limited to this example.

As the sacrificial layer SFL is etched, at least a portion of the top surface of the first pixel electrode AE1 may be exposed. In the wet etching process, the sacrificial layer SFL may be etched in a larger amount than the first insulating layer IL 1. As the sacrificial layer SFL is etched, a residual pattern RP (see fig. 4) may remain between the first insulating layer IL1 and the first pixel electrode AE 1. Accordingly, a side surface of each of the plurality of residual patterns RP may be recessed inward from the side surface ILs of the first insulating layer IL 1.

Fig. 19 is a cross-sectional view showing a part of a display device according to another embodiment of the present disclosure, and fig. 20 is an enlarged cross-sectional view of a region A2 of fig. 19. The display device of fig. 19 and 20 is different from the display device of fig. 4 and 5 in the structure of the bank BNK, and will be described hereinafter mainly focusing on the differences from the display device of fig. 4 and 5.

Referring to fig. 19 and 20, the display panel 100 (e.g., see fig. 1) may include a display unit DU (see fig. 2), a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML (see fig. 2), and an encapsulation layer TFEL. The light emitting element layer EML may include first light emitting elements ED1, second light emitting elements ED2 and third light emitting elements ED3, residual patterns RP, a first insulating layer IL1, CAP layers, banks BNK, first organic patterns ELP1, second organic patterns ELP2 and third organic patterns ELP3, first electrode patterns CEP1, second electrode patterns CEP2 and third electrode patterns CEP3, first CAP patterns CLP1, second CAP patterns CLP2 and third CAP patterns CLP3, and first inorganic layers TL1, second inorganic layers TL2 and third inorganic layers TL3.

Referring to fig. 20, the first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surfaces BKS1 and BKS2 of the first and second banks BNK1 and BNK 2.

The first insulating layer IL1 and the bank BNK may be etched by separate etching processes. The first insulating layer IL1 and the bank BNK may be etched using different photoresists as masks. The bank BNK may be etched using the first photoresist as a mask, and the first insulating layer IL1 may be etched using the second photoresist as a mask. The first photoresist may cover a top surface of the bank BNK. The second photoresist may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist may have a larger planar area than the first photoresist. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched by separate etching processes, damage to the residual pattern RP may be controlled and a relatively thin residual pattern RP may be provided.

Referring to fig. 19 and 20, since the display device includes the first insulating layer IL1 having the inclined side surface ILS and the relatively thin residual pattern RP, the first, second and third common electrodes CE1, CE2 and CE3 may be prevented from being shorted. For example, the first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the first emission area EA1, and may extend to a side surface of the first bank BNK1 to be in contact with a side surface BKS1 of the first bank BNK 1. Accordingly, defects of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be prevented, and reliability can be improved.

The bank BNK may be disposed on the first insulating layer IL1, and may define a first emission area EA1, a second emission area EA2, and a third emission area EA3. In a plan view, the bank BNK may surround the first, second, and third emission areas EA1, EA2, and EA3. The dike BNK may comprise a first dike BNK1 and a second dike BNK2.

The first bank BNK1 may be disposed on the first insulating layer IL1, and the second bank BNK2 may be disposed on the first bank BNK 1. Referring to fig. 20, the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK2 may be spaced apart from the side surface ILs of the first insulating layer IL 1. The side surface BKS1 of the first bank BNK1 may be recessed inward from the side surface BKS2 of the second bank BNK2. The side surface BKS2 of the second bank BNK2 may protrude from the side surface BKS1 of the first bank BNK1 toward the first emission area EA1, and thus may include protruding tips. Thus, an undercut may be formed under the tip of the second dike BNK2. The first dike BNK1 may be thicker than the second dike BNK2.

Referring to fig. 19 and 20, the first and second dike BNKs 1 and 2 may include different metal materials. The first bank BNK1 and the second bank BNK2 may have different etch rates. For example, in the wet etching process, during formation of the first, second and third emission areas EA1, EA2 and EA3, the first bank BNK1 may be etched faster than the second bank BNK2 and in a larger amount than the second bank BNK2. Therefore, the shape of the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may comprise a metal material having a high conductivity and the second bank BNK2 may comprise a metal material having a low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited to this example.

The bank BNK may define openings therein forming the first, second, and third emission areas EA1, EA2, and EA3, and may overlap the light blocking member BM of the color filter layer CFL in a plan view. The first bank BNK1 may electrically connect the first, second and third common electrodes CE1, CE2 and CE3 spaced apart from each other. The second bank BNK2 may include a metal material having a low reflectivity, and thus can reduce reflection of external light.

The bank BNK may form the first, second, and third emission areas EA1, EA2, and EA3 via a mask process, and the first, second, and third emission layers EL1, EL2, and EL3 may be formed in the first, second, and third emission areas EA1, EA2, and EA3, respectively. The masking process may require a structure for mounting the mask and an excessively large non-display area NDA for distribution control (see, e.g., fig. 1). If the mask process can be minimized, a structure for mounting the mask may not be provided, and the size of the non-display area NDA for distribution control may be minimized.

Fig. 21 to 26 are sectional views showing examples of how the display device of fig. 19 is fabricated.

Referring to fig. 21, the first, second, and third pixel electrodes AE1, AE2, and AE3 may be disposed to be spaced apart from each other on the thin film transistor layer TFTL. For example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include at least one of Ag, cu, al, ni and La. In another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may include ITO, IZO, or ITZO. In another example, the first, second, and third pixel electrodes AE1, AE2, and AE3 may have a stacked structure such as ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The sacrificial layer SFL may be disposed on the first, second, and third pixel electrodes AE1, AE2, AE 3. The sacrificial layer SFL may be disposed between top surfaces of the first, second, and third pixel electrodes AE1, AE2, AE3 and the first insulating layer IL 1. The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide ("IZO"), zinc tin oxide ("ZTO"), and IZO.

The first bank BNK1 may be disposed on the first insulating layer IL1, and the second bank BNK2 may be disposed on the first bank BNK 1. The first dike BNK1 may be thicker than the second dike BNK2.

The first photoresist PR1 may be disposed on the second bank BNK2 so as not to overlap the first pixel electrode AE1 in a plan view. The first photoresist PR1 may be provided in a region other than a region in which the first emission region EA1 (see fig. 19) is to be formed.

Referring to fig. 22, the second dike BNK2 may be etched and then the first dike BNK1 may be etched, thereby forming the first hole HOL1. The first hole HOL1 may overlap with the first emission area EA1 (see fig. 19). The first and second banks BNK1 and BNK2 may be etched by at least one of dry etching and wet etching. For example, the first and second banks BNK1 and BNK2 may be primarily etched by dry etching and the first and second banks BNK1 and BNK2 may be secondarily etched by wet etching, but the disclosure is not limited thereto. The first and second dykes BNK1 and BNK2 may comprise different metallic materials and may have different etch rates. In the wet etching process, the first bank BNK1 may be etched faster than the second bank BNK2 and etched in a larger amount than the second bank BNK2. Therefore, the shape of the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The second dike BNK2 may include a tip protruding from the first dike BNK1 toward the first hole HOL1. The side surface BKS1 of the first bank BNK1 may be recessed inward from the side surface BKS2 of the second bank BNK2. An undercut may be formed under the tip of the second bank BNK2. The first dike BNK1 may be thicker than the second dike BNK2.

The first bank BNK1 may comprise a metal material having a high conductivity and the second bank BNK2 may comprise a metal material having a low reflectivity. For example, the first bank BNK1 may include aluminum (Al), and the second bank BNK2 may include titanium (Ti). However, the present disclosure is not limited to this example.

Referring to fig. 23, the first insulating layer IL1 may be etched using a second photoresist PR2 different from the first photoresist PR1 (see, for example, fig. 22). The second photoresist PR2 may further cover a side surface of each of the plurality of banks BNK as compared to the first photoresist PR 1. The second photoresist PR2 may cover the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK 2. The second photoresist PR2 may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist PR2 may have a larger planar area than the first photoresist PR 1. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist PR2 may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched by separate etching processes, damage to the residual pattern RP (see fig. 19) may be controlled, and the display device may include a relatively thin residual pattern RP.

Referring to fig. 24, the first insulating layer IL1 and the sacrificial layer SFL may be etched by at least one of dry etching and wet etching. For example, the first insulating layer IL1 may be etched by dry etching, and the sacrificial layer SFL may be etched by wet etching. However, the present disclosure is not limited to this example. As the first insulating layer IL1 and the sacrificial layer SFL are etched, at least a portion of the top surface of the first pixel electrode AE1 may be exposed. In the wet etching process, the sacrificial layer SFL may be etched in a larger amount than the first insulating layer IL 1. As the sacrificial layer SFL is etched, the residual pattern RP may remain between the first insulating layer IL1 and the first pixel electrode AE 1. Accordingly, a side surface of each of the plurality of residual patterns RP may be recessed inward from the side surface ILs of the first insulating layer IL 1.

The first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The tilt angle of the side surface ILs of the first insulating layer IL1 may be determined by the tilt angle of the second photoresist PR 2. For example, if the slope of the side surface of the second photoresist PR2 is steep (e.g., almost vertical), the side surface ILs of the first insulating layer IL1 may have a steep slope. In contrast, if the slope of the side surface of the second photoresist PR2 is gentle (e.g., almost flat), the side surface ILs of the first insulating layer IL1 may have a gentle slope. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surfaces BKS1 and BKS2 of the first and second banks BNK1 and BNK 2.

Referring to fig. 25, after etching the first insulating layer IL1 and the sacrificial layer SFL, the second photoresist PR2 may be removed by a lift-off process (see fig. 24).

Referring to fig. 26, in the first emission area EA1 (see fig. 19), the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE 1. A portion of the first light emitting layer EL1 may fill a space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a portion of the top surface of the first insulating layer IL1 and some of the plurality of side surfaces ILs of the first insulating layer IL 1.

The organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited by the same process, and may be cut by tips formed on the inner sidewall of each of the plurality of banks BNK and separated from each other. In the region other than the first emission region EA1, the first organic pattern ELP1 may be disposed on the second bank BNK 2.

The first common electrode CE1 may be disposed on the first light emitting layer EL 1. The first common electrode CE1 may include a transparent conductive material, and may transmit light generated by the first light emitting layer EL1 therethrough. The first common electrode CE1 may be in contact with a side surface BKS1 (see fig. 25) of the first bank BNK 1. Accordingly, the first light emitting element ED1 may be formed in the first hole HOL1, and may emit light via the first emission area EA 1.

A metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited by the same process, and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. In the region other than the first emission region EA1, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP 1.

The CAP layer CAP may be disposed on the first common electrode CE 1. The CAP layer CAP may include an inorganic insulating material, and may cover the first light emitting element ED1. The CAP layer CAP may prevent the first common electrode CE1 from being damaged by external air.

An inorganic material for forming the CAP layer CAP and the first CAP pattern CLP1 may be deposited on the entire surface of the display device. The CAP layer CAP and the first CAP pattern CLP1 may be deposited by the same process and may be cut by a tip formed on an inner sidewall of each of the plurality of banks BNK. In the region other than the first emission region EA1, the first cover pattern CLP1 may be disposed on the first electrode pattern CEP 1.

The first inorganic layer TL1 may be disposed on a portion of the CAP layer CAP in the first emission area EA1 and on the first CAP pattern CLP 1. The first inorganic layer TL1 may cover the side surface BKS1 of the portion of the first bank BNK1 surrounding the first emission area EA 1. The first inorganic layer TL1 may include an inorganic material, and may prevent oxygen or moisture from penetrating the first light emitting element ED1.

Fig. 27 to 29 are sectional views showing another example of how the display device of fig. 19 is manufactured. Fig. 27 to 29 show a manufacturing process that may replace the manufacturing process described above with reference to fig. 22 to 24. For example, fig. 27 illustrates a manufacturing process that may be performed after the manufacturing process of fig. 21, and fig. 29 illustrates a manufacturing process that may be performed before the manufacturing process of fig. 25.

Referring to fig. 27, a first photoresist PR1 may be disposed on the second bank BNK2 so as not to overlap the first pixel electrode AE1 in a plan view. The first photoresist PR1 may be provided in a region other than the region in which the first emission region EA1 is to be formed.

The second bank BNK2 may be etched and then the first bank BNK1 may be etched, thereby forming the first hole HOL1. The first hole HOL1 may overlap with the first emission area EA1 (see fig. 19). The first and second banks BNK1 and BNK2 may be etched by at least one of dry etching and wet etching. For example, the first and second banks BNK1 and BNK2 may be etched by dry etching, but the present disclosure is not limited thereto. In the dry etching process, the first bank BNK1 and the second bank BNK2 may have substantially the same etching rate. Thus, the second bank BNK2 may be etched earlier than the first bank BNK1 and in a smaller amount than the first bank BNK 1. The side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK2 may be connected to each other.

Referring to fig. 28, the first insulating layer IL1 may be etched using a second photoresist PR2 different from the first photoresist PR1 (see fig. 27). The second photoresist PR2 may further cover a side surface of each of the plurality of BNK dykes, as compared to the first photoresist PR 1. The second photoresist PR2 may cover the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK 2. The second photoresist PR2 may cover both side surfaces and top surfaces of each of the plurality of bank BNKs and may protect the side surfaces of each of the plurality of bank BNKs. The second photoresist PR2 may have a larger planar area than the first photoresist PR 1. For example, in the case where the first bank BNK1 includes aluminum (Al) and the first insulating layer IL1 is formed by dry etching, the second photoresist PR2 may prevent the first bank BNK1 from being oxidized by plasma. Since the first insulating layer IL1 and the bank BNK are etched by separate etching processes, damage to the residual pattern RP (see fig. 19) may be controlled and a relatively thin residual pattern RP may be provided.

Referring to fig. 29, the first insulating layer IL1 may be etched by at least one of dry etching and wet etching. For example, the first insulating layer IL1 may be etched by dry etching, but the present disclosure is not limited thereto. As the first insulating layer IL1 is etched, a portion of the top surface of the sacrificial layer SFL may be exposed.

The first insulating layer IL1 may have an inclined side surface ILs. The first insulating layer IL1 may be etched from above, and a side surface ILs of the first insulating layer IL1 may face the top of the light emitting element layer EML (see fig. 2). The tilt angle of the side surface ILs of the first insulating layer IL1 may be determined by the tilt angle of the second photoresist PR2. For example, if the slope of the side surface of the second photoresist PR2 is steep (e.g., almost vertical), the side surface ILs of the first insulating layer IL1 may have a steep slope. In contrast, if the slope of the side surface of the second photoresist PR2 is gentle (e.g., almost flat), the side surface ILs of the first insulating layer IL1 may have a gentle slope. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surface of each of the plurality of banks BNK. The side surface ILs of the first insulating layer IL1 may be spaced apart from the side surfaces BKS1 and BKS2 of the first and second banks BNK1 and BNK 2.

After etching the first insulating layer IL1, the second photoresist PR2 may be removed by a stripping process. For example, after the removal of the second photoresist PR2, the side surface BKS1 of the first bank BNK1 and the sacrificial layer SFL may be etched by wet etching, but the disclosure is not limited thereto. The first and second dykes BNK1 and BNK2 may comprise different metallic materials and may have different etch rates. In the wet etching process, the first bank BNK1 may be etched faster than the second bank BNK2 and etched in a larger amount than the second bank BNK 2. Therefore, the shape of the side surface BKS1 of the first bank BNK1 and the side surface BKS2 of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK 2. The second dike BNK2 may include a tip protruding from the first dike BNK1 toward the first hole HOL 1. The side surface BKS1 of the first bank BNK1 may be recessed inward from the side surface BKS2 of the second bank BNK 2. An undercut may be formed under the tip of the second bank BNK 2. The first dike BNK1 may be thicker than the second dike BNK 2.

As the sacrificial layer SFL is etched, at least a portion of the top surface of the first pixel electrode AE1 may be exposed. In the wet etching process, the sacrificial layer SFL may be etched in a larger amount than the first insulating layer IL 1. As the sacrificial layer SFL is etched, a residual pattern RP (see fig. 19) may remain between the first insulating layer IL1 and the first pixel electrode AE 1. Accordingly, a side surface of each of the plurality of residual patterns RP may be recessed inward from the side surface ILs of the first insulating layer IL 1.

Claims

1. A display device, wherein the display device comprises:

a first pixel electrode disposed in the first emission region on the substrate;

an insulating layer covering edges of the first pixel electrode;

a first light emitting layer disposed on the first pixel electrode and the insulating layer;

a first common electrode disposed on the first light emitting layer;

a plurality of banks disposed on the insulating layer and surrounding the first emission region; and

An organic pattern disposed on the plurality of banks around the first emission region and including the same material as the first light emitting layer,

wherein a side surface of each of the plurality of banks is spaced apart from a side surface of the insulating layer.

2. The display device according to claim 1, wherein the plurality of banks includes:

a first bank disposed on the insulating layer and including a metal material;

a second bank disposed on the first bank; and

and a third bank disposed between the first bank and the insulating layer.

3. A display device according to claim 2, wherein side surfaces of the first bank are recessed inwardly from side surfaces of the second bank and side surfaces of the third bank.

4. A display device according to claim 2, wherein the second bank comprises a tip protruding from a side surface of the first bank toward the first emission region.

5. The display device according to claim 2, wherein the first common electrode extends to a side surface of each of the first bank and the third bank and is in contact with the side surface of the first bank and a top surface of the third bank.

6. The display device according to claim 2, wherein the display device further comprises:

a second pixel electrode disposed in a second emission region on the substrate;

a second light emitting layer disposed on the second pixel electrode; and

and a second common electrode disposed on the second light emitting layer.

7. The display device according to claim 6, wherein the first common electrode and the second common electrode are electrically connected via the first bank and the third bank.

8. The display device according to claim 1, wherein the plurality of banks includes:

a first bank disposed on the insulating layer and including a metal material; and

and a second bank disposed on the first bank.

9. A display device according to claim 8, wherein a side surface of the first bank is recessed inwardly from a side surface of the second bank.

10. The display device according to claim 8, wherein the display device further comprises:

a second pixel electrode disposed in a second emission region on the substrate;

a second light emitting layer disposed on the second pixel electrode; and

a second common electrode disposed on the second light emitting layer,

Wherein the first common electrode and the second common electrode are electrically connected via the first bank.

11. A method of manufacturing a display device, wherein the method comprises:

forming a first pixel electrode and a second pixel electrode on a substrate;

sequentially depositing a sacrificial layer, an insulating layer, a third bank, a first bank and a second bank on the first pixel electrode and the second pixel electrode;

forming a first photoresist on the second bank, the first photoresist not overlapping the first pixel electrode in a plan view;

etching the second bank, the first bank, and the third bank using the first photoresist as a mask;

forming a second photoresist covering side surfaces of each of the first, second, and third banks; and

the insulating layer is etched using the second photoresist as a mask.

12. The method of claim 11, wherein the method further comprises, after the etching of the insulating layer:

the sacrificial layer is etched using the second photoresist as a mask to expose the first pixel electrode.

13. The method of claim 12, wherein the method further comprises, after the exposing of the first pixel electrode:

forming a first light emitting layer on the first pixel electrode and forming an organic pattern on the second bank;

forming a first common electrode on the first light emitting layer, and forming a first electrode pattern on the organic pattern;

forming a cap layer on the first common electrode, and forming a first cap pattern on the first electrode pattern; and

a first inorganic layer is formed to cover the cap layer, the first cap pattern, and the side surface of the first bank.

14. The method of claim 11, wherein the etching of the second, first, and third banks comprises recessing the side surface of the first bank inward from the side surface of each of the second and third banks.

15. The method of claim 11, wherein the method further comprises, after the etching of the insulating layer:

the second photoresist is removed, and the sacrificial layer, and the side surfaces of the first bank are etched.

16. A method of manufacturing a display device, wherein the method comprises:

forming a first pixel electrode and a second pixel electrode on a substrate;

sequentially depositing a sacrificial layer, an insulating layer, a first bank and a second bank on the first pixel electrode and the second pixel electrode;

etching the second bank and the first bank using the first photoresist as a mask;

forming a second photoresist covering side surfaces of each of the first and second banks; and

the insulating layer is etched using the second photoresist as a mask.

17. The method of claim 16, wherein the method further comprises, after the etching of the insulating layer:

18. The method of claim 17, wherein the method further comprises, after the exposing of the first pixel electrode:

19. A method as claimed in claim 16, wherein the etching of the second bank and the first bank comprises recessing the side surface of the first bank inwardly from the side surface of the second bank.

20. The method of claim 16, wherein the method further comprises, after the etching of the insulating layer: