CN117879589A

CN117879589A - Multi-level output circuit and method for multi-voltage domain unified architecture

Info

Publication number: CN117879589A
Application number: CN202311743046.8A
Authority: CN
Inventors: 刘颖; 吕俊盛; 李岩; 邵刚; 邓广真; 马洁
Original assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2023-12-18
Filing date: 2023-12-18
Publication date: 2024-04-12

Abstract

The invention relates to a multi-level output circuit and a method for a multi-voltage domain unified architecture, wherein the multi-level output circuit comprises a positive differential signal INP input end, a negative differential signal INN input end, a power supply circuit, a first-stage pre-driving circuit, a second-stage pre-driving circuit, an output driving circuit, a positive differential signal OUTP output end and a negative differential signal OUTN output end; the positive differential signal INP input end and the negative differential signal INN input end are connected into the output driving circuit through the first-stage pre-driving circuit and the second-stage pre-driving circuit respectively; the power supply circuit is respectively connected with the first-stage pre-driving circuit, the second-stage pre-driving circuit and the output driving circuit; the output driving circuit is respectively connected with the output end of the positive differential signal OUTP and the output end of the negative differential signal OUTN. The invention has the advantages of simple circuit structure, strong power supply adaptability and easy realization of the process.

Description

Multi-level output circuit and method for multi-voltage domain unified architecture

Technical Field

The invention belongs to the field of microelectronics, relates to a multi-level output circuit, and in particular relates to a multi-level output circuit and a multi-level output method for a multi-voltage domain unified architecture.

Background

In high performance computing, communication, data processing and other electronic systems, particularly in high performance electronic systems, the noise requirements of the power supply system are high, and dual power supplies of 3.3V and 2.5V are required, and different protocol and level standards are required to be applied, corresponding to multiple power supply voltages and level types. The traditional design method is realized by adopting a standard triode type current mode logic (CML structure), and the differential level output of LVPECL, LVDS, CML and the like is realized through the configuration of output tail current. The method is closely related to the process, has extremely high requirements on devices and has great design difficulty. In most cases, the CMOS process platform needs to design LVPECL, LVDS, CML and other level output circuits respectively to meet the requirement of output level, but the complexity of circuit and layout design is improved, the output parasitism is large, and the CMOS process platform cannot be suitable for the field of high-frequency high-performance communication.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a multi-level output circuit and a method for a multi-voltage domain unified architecture, which have the advantages of simple circuit structure, strong power supply adaptability and easy process realization.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

a multi-level output circuit for a multi-voltage domain unified architecture, characterized by: the multi-level output circuit for the multi-voltage domain unified architecture comprises a positive differential signal INP input end, a negative differential signal INN input end, a power supply circuit, a first-stage pre-driving circuit, a second-stage pre-driving circuit, an output driving circuit, a positive differential signal OUTP output end and a negative differential signal OUTN output end; the positive differential signal INP input end and the negative differential signal INN input end are respectively connected into the output driving circuit through the first-stage pre-driving circuit; the positive differential signal INP input end and the negative differential signal INN input end are respectively connected into the output driving circuit through the second-stage pre-driving circuit; the power supply circuit is respectively connected with the first-stage pre-driving circuit, the second-stage pre-driving circuit and the output driving circuit; the output driving circuit is respectively connected with the output end of the positive differential signal OUTP and the output end of the negative differential signal OUTN.

The power supply circuit comprises a power supply VDD and a low dropout linear regulator LDO; the power supply VDD forms a secondary power supply VDDL through a low dropout linear regulator LDO; the power supply VDD is respectively connected with the first-stage pre-driving circuit and the output driving circuit; the secondary power supply VDDL is respectively connected to the first-stage pre-driving circuit and the second-stage pre-driving circuit.

The first-stage pre-driving circuit comprises a dynamic current source I1, a switch phi 2, a switch phi 3, a switch phi 4, a resistor R1, a resistor R2, a transistor MN1, a transistor MN2, a first-stage pre-driving positive differential signal OUTP1 output end and a first-stage pre-driving negative differential signal OUTN1 output end; one end of the dynamic current source I1 is grounded, and the other end of the dynamic current source I1 is respectively connected with the transistor MN1 and the transistor MN2; the input end of the forward differential signal INP is connected to the transistor MN1; the negative differential signal INN input end is connected to the transistor MN2; the power supply VDD is respectively connected with a switch phi 1 and a switch phi 2; the secondary power supply VDDL is respectively connected with a switch phi 3 and a switch phi 4; the transistor MN1 is connected to a switch phi 1 or a switch phi 3 through a resistor R1; the transistor MN2 is connected to a switch phi 2 or a switch phi 4 through a resistor R2; the resistor R1 is connected to an output driving circuit through the output end of the first-stage pre-driving negative differential signal OUTN1; the resistor R2 is connected to the output driving circuit through the output end of the first-stage pre-driving forward differential signal OUTP 1.

The dynamic current source I1 is connected to the source of the transistor MN1 and the source of the transistor MN2, respectively; the input end of the forward differential signal INP is connected with the grid electrode of the transistor MN1; the negative differential signal INN input end is connected with the grid electrode of the transistor MN2; the drain electrode of the transistor MN1 is connected to a switch phi 1 or a switch phi 3 through a resistor R1; the drain of the transistor MN2 is connected to the switch Φ2 or the switch Φ4 through the resistor R2.

The second-stage pre-driving circuit comprises a resistor R3, a resistor R4, a transistor MN3, a transistor MN4, a second-stage pre-driving positive differential signal OUTP2 output end, a second-stage pre-driving negative differential signal OUTN2 output end and a stable current source I2; one end of the stable current source I2 is grounded, and the other end of the stable current source I2 is respectively connected with the transistor MN3 and the transistor MN4; the input end of the forward differential signal INP is connected to the transistor MN3; the negative differential signal INN input end is connected to the transistor MN4; the secondary power supply VDDL is connected to the transistor MN3 through a resistor R3; the secondary power supply VDDL is connected to the transistor MN4 through a resistor R4; the resistor R3 is connected to an output driving circuit through the output end of the second-stage pre-driving negative differential signal OUTN2; the resistor R4 is connected to the output driving circuit through the output end of the second-stage pre-driving forward differential signal OUTP 2.

The stable current source I2 is connected to the source of the transistor MN3 and the source of the transistor MN4, respectively; the input end of the forward differential signal INP is connected with the grid electrode of the transistor MN3; the negative differential signal INN input end is connected with the grid electrode of the transistor MN4; the drain electrode of the transistor MN3 is connected with the resistor R3; the drain of the transistor MN4 is connected to the resistor R4.

The output driving circuit comprises a switch phi 5, a switch phi 6, a switch phi 7, a switch phi 8 and a dynamic current source I3; the power supply VDD is respectively connected with the switch phi 5 and the switch phi 6; one end of the dynamic current source I3 is grounded, and the other end of the dynamic current source I is connected with the switch phi 7 and the switch phi 8 respectively; the output end of the first-stage pre-driving forward differential signal OUTP1 is connected to the output end of the forward differential signal OUTP through a switch phi 5; the output end of the first-stage pre-driving negative differential signal OUTN1 is connected to the output end of the negative differential signal OUTN through a switch phi 6; the output end of the second-stage pre-driving forward differential signal OUTP2 is connected to the output end of the forward differential signal OUTP through a switch phi 8, a switch phi 6 and a switch phi 5; the output end of the second-stage pre-driving negative differential signal OUTN2 is connected to the output end of the negative differential signal OUTN through a switch phi 7, a switch phi 5 and a switch phi 6.

A multi-level output method based on a multi-level output circuit for a multi-voltage domain unified architecture as described above, characterized by: the method comprises the following steps:

1) Acquiring a power supply VDD and a secondary power supply VDDL;

2) Based on the obtained power supply VDD and the secondary power supply VDDL obtained in the step 1), respectively regulating and controlling a first-stage pre-driving circuit, a second-stage pre-driving circuit and an output driving circuit according to the type of the level to be output; the type of the level to be output is LVPECL level output, LVDS level output or CML level output;

3) And respectively outputting LVPECL level, LVDS level or CML level according to the regulation result.

In the step 1), the voltage of the secondary power supply VDDL is lower than the voltage of the power supply VDD; the power supply VDD generates the secondary power supply VDDL through a low dropout linear regulator LDO.

When the type of the level to be output is LVPECL level output, the specific implementation manner of the step 2) is as follows: under the action of a power supply VDD or a secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, switches phi 1 and phi 2 are controlled to be opened, and switches phi 3 and phi 4 are controlled to be closed, and meanwhile, a dynamic current source I1 is increased to form and promote a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 to rise in high level; receiving a positive differential signal INP through a transistor MN3, receiving a negative differential signal INN through a transistor MN4, and generating a second-stage pre-driving positive differential signal OUTP2 and a second-stage pre-driving negative differential signal OUTN2 through a stable current source I2 and a resistor R3 or a resistor R4 under the action of a secondary power supply VDDL;

when the type of the level to be output is LVDS level output, the specific implementation manner of the step 2) is as follows: under the action of the secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, the switches phi 3 and phi 4 are controlled to be opened, the switches phi 1 and phi 2 are controlled to be closed, and meanwhile, a dynamic current source I1 is reduced, so that a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 are formed and output; receiving the positive differential signal INP through the transistor MN3, receiving the negative differential signal INN through the transistor MN4, and generating the second-stage pre-driving positive differential signal OUTP2 and the second-stage pre-driving negative differential signal OUTN2 through the stable current source I2 and the resistor R3 or the resistor R4 under the secondary power supply VDDL;

when the type of the level to be output is CML level output, the specific implementation manner of the step 2) is as follows: under the action of the secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, the switches phi 3 and phi 4 are controlled to be opened, the switches phi 1 and phi 2 are controlled to be closed, and meanwhile, a dynamic current source I1 is reduced, so that a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 are formed and output; the positive differential signal INP is received through the transistor MN3, the negative differential signal INN is received through the transistor MN4, and the second-stage pre-driving positive differential signal OUTP2 and the second-stage pre-driving negative differential signal OUTN2 are generated through the stable current source I2 and the resistor R3 or the resistor R4 under the secondary power supply VDDL.

The invention has the advantages that:

the invention provides a multi-level output circuit and a method for a multi-voltage domain unified architecture, which consists of a two-stage pre-driving circuit and an output driving circuit, wherein an internal secondary power supply VDDL is generated by a low dropout linear regulator LDO, the two-stage pre-driving circuit outputs two groups of differential pairs OUTP1/OUTN1 and OUTP2/OUTN2 through the cooperation of a power supply VDD, the secondary power supply VDDL, a plurality of groups of logic control switches phi 1-phi 4 and tail currents I1-I2, so that phi 5-phi 6 and phi 7-phi 8 in the output driving circuit are normally open, and the phi 5-phi 8 can be realized by a transmission gate consisting of NMOS (N-channel metal oxide semiconductor) tubes, PMOS (P-channel metal oxide semiconductor) tubes or NMOS (N-channel metal oxide semiconductor) tubes; the phi 5-phi 8 switching tube is matched with the tail current I3, and the driving output of various differential levels such as LVPECL, LVDS, CML is realized through the output impedance of the switching tube and the magnitude of the tail current. The invention can effectively isolate power supply noise, has strong adaptability, is matched with a plurality of groups of logic control switches and tail currents, realizes the driving output of a plurality of differential levels such as LVPECL, LVDS, CML, has simple and easy realization of circuit principle, strong process portability, small layout scale and small parasitism, and has good signal performance especially in communication application above GHz.

Drawings

FIG. 1 is a schematic circuit diagram of a multi-level output circuit for a multi-voltage domain unified architecture provided by the present invention;

FIG. 2 is a schematic circuit diagram of a first stage pre-drive circuit employed in the present invention;

FIG. 3 is a schematic circuit diagram of a second stage pre-drive circuit employed in the present invention;

fig. 4 is a schematic circuit diagram of an output drive circuit employed in the present invention.

Detailed Description

Referring to fig. 1, the present invention provides a multi-level output circuit for a multi-voltage domain unified architecture, which includes a positive differential signal INP input terminal, a negative differential signal INN input terminal, a power supply circuit, a first stage pre-driving circuit, a second stage pre-driving circuit, an output driving circuit, a positive differential signal OUTP output terminal, and a negative differential signal OUTN output terminal; the input end of the positive differential signal INP and the input end of the negative differential signal INN are respectively connected into the output driving circuit through the first-stage pre-driving circuit; the input end of the positive differential signal INP and the input end of the negative differential signal INN are respectively connected into the output driving circuit through the second-stage pre-driving circuit; the power supply circuit is respectively connected with the first-stage pre-driving circuit, the second-stage pre-driving circuit and the output driving circuit; the output driving circuit is respectively connected with the output end of the positive differential signal OUTP and the output end of the negative differential signal OUTN. The principle of the invention is as follows: the low-dropout linear voltage regulator (LDO) is used for generating an internal secondary power supply VDDL, the pre-driving circuit outputs two groups of differential pairs OUTP1/OUTN1 and OUTP2/OUTN2 through the cooperation of the power supply VDD, the secondary power supply VDDL, a plurality of groups of logic control switches phi 1-phi 4 and tail currents I1-I2, and the switches phi 5-phi 6 and the switches phi 7-phi 8 in the output driving circuit are normally opened and closed respectively, wherein the switches phi 5-phi 8 can be realized by using NMOS tubes, PMOS tubes or transmission gates formed by NMOS tubes and PMOS tubes; the phi 5-phi 8 switching tube is matched with the tail current I3, and the driving output of various differential levels such as LVPECL, LVDS, CML is realized through the output impedance of the switching tube and the magnitude of the tail current.

Referring to fig. 1, the power supply circuit includes a power supply VDD and a low dropout linear regulator LDO; the power supply VDD forms a secondary power supply VDDL through a low dropout linear regulator LDO; the power supply VDD is respectively connected with the first-stage pre-driving circuit and the output driving circuit; the secondary power supply VDDL is respectively connected to the first-stage pre-driving circuit and the second-stage pre-driving circuit.

Referring to fig. 2, the first stage pre-driving circuit adopted in the present invention includes a dynamic current source I1, a switch Φ1, a switch Φ2, a switch Φ3, a switch Φ4, a resistor R1, a resistor R2, a transistor MN1, a transistor MN2, a first stage pre-driving positive differential signal OUTP1 output end, and a first stage pre-driving negative differential signal OUTN1 output end; one end of the dynamic current source I1 is grounded, and the other end of the dynamic current source I1 is respectively connected with the transistor MN1 and the transistor MN2; the forward differential signal INP input end is connected to the transistor MN1; the negative differential signal INN input end is connected to the transistor MN2; the power supply VDD is respectively connected with the switch phi 1 and the switch phi 2; the secondary power supply VDDL is respectively connected with a switch phi 3 and a switch phi 4; the transistor MN1 is connected to the switch phi 1 or the switch phi 3 through a resistor R1; the transistor MN2 is connected to the switch phi 2 or the switch phi 4 through a resistor R2; the resistor R1 is connected to an output driving circuit through the output end of the first-stage pre-driving negative differential signal OUTN1; the resistor R2 is connected to the output driving circuit through the output end of the first-stage pre-driving forward differential signal OUTP 1. Illustratively, the dynamic current source I1 is connected to the source of the transistor MN1 and the source of the transistor MN2, respectively; the forward differential signal INP input terminal is connected to the gate of the transistor MN1; the negative differential signal INN input end is connected with the grid electrode of the transistor MN2; the drain electrode of the transistor MN1 is connected to the switch phi 1 or the switch phi 3 through a resistor R1; the drain of the transistor MN2 is connected to the switch Φ2 or the switch Φ4 via the resistor R2.

Referring to fig. 3, the second-stage pre-driving circuit includes a resistor R3, a resistor R4, a transistor MN3, a transistor MN4, a second-stage pre-driving positive differential signal OUTP2 output terminal, a second-stage pre-driving negative differential signal OUTN2 output terminal, and a stable current source I2; one end of the stable current source I2 is grounded, and the other end of the stable current source I2 is respectively connected with the transistor MN3 and the transistor MN4; the forward differential signal INP input end is connected to the transistor MN3; the negative differential signal INN input end is connected to the transistor MN4; the secondary power supply VDDL is connected to the transistor MN3 through the resistor R3; the secondary power supply VDDL is connected to the transistor MN4 through the resistor R4; the resistor R3 is connected to the output driving circuit through the output end of the second-stage pre-driving negative differential signal OUTN2; the resistor R4 is connected to the output driving circuit through the output end of the second-stage pre-driving forward differential signal OUTP 2. Illustratively, the stable current source I2 is connected to the source of the transistor MN3 and the source of the transistor MN4, respectively; the forward differential signal INP input terminal is connected to the gate of the transistor MN3; the negative differential signal INN input end is connected with the grid electrode of the transistor MN4; the drain of the transistor MN3 is connected with the resistor R3; the drain of transistor MN4 is connected to resistor R4.

Referring to fig. 4, the output driving circuit adopted by the present invention includes a switch Φ5, a switch Φ6, a switch Φ7, a switch Φ8, and a dynamic current source I3; the power supply VDD is respectively connected with the switch phi 5 and the switch phi 6; one end of the dynamic current source I3 is grounded, and the other end of the dynamic current source I is respectively connected with the switch phi 7 and the switch phi 8; the output end of the first-stage pre-driving forward differential signal OUTP1 is connected to the output end of the forward differential signal OUTP through a switch phi 5; the output end of the first-stage pre-driving negative differential signal OUTN1 is connected to the output end of the negative differential signal OUTN through a switch phi 6; the output end of the second-stage pre-driving forward differential signal OUTP2 is connected to the output end of the forward differential signal OUTP through a switch phi 8, a switch phi 6 and a switch phi 5; the output end of the second-stage pre-driving negative differential signal OUTN2 is connected with the output end of the negative differential signal OUTN through a switch phi 7, a switch phi 5 and a switch phi 6.

The invention provides a multi-level output circuit for a multi-voltage domain unified architecture, and also provides a multi-level output method based on the circuit, which comprises the following steps:

1) Acquiring a power supply VDD and a secondary power supply VDDL; the voltage of the secondary power supply VDDL is lower than the voltage of the power supply VDD; the power supply VDD generates a secondary power supply VDDL through a low dropout linear regulator LDO

2) Based on the obtained power supply VDD and the secondary power supply VDDL obtained in the step 1), respectively regulating and controlling a first-stage pre-driving circuit, a second-stage pre-driving circuit and an output driving circuit according to the type of the level to be output; the type of the level to be output is LVPECL level output, LVDS level output or CML level output; because of the determination of the output impedance, in order to ensure multi-level output, the high level and the low level of the output signal of the pre-driving circuit need to be dynamically adjusted so as to meet the level requirements of signals with different output types.

When the type of the output level is LVPECL level output, the specific implementation manner of the step 2) is as follows: under the action of a power supply VDD or a secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, switches phi 1 and phi 2 are controlled to be opened, and switches phi 3 and phi 4 are turned off, and meanwhile, a dynamic current source I1 is increased to form and promote the high level rise of a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 so as to meet the opening and closing of the switches phi 5 to phi 6 of a later-stage output driving circuit; receiving a positive differential signal INP through a transistor MN3, receiving a negative differential signal INN through a transistor MN4, controlling on of phi 5, phi 6 and phi 7 under the action of a secondary power supply VDDL, controlling off of phi 8, and generating a second-stage pre-driving positive differential signal OUTP2 and a second-stage pre-driving negative differential signal OUTN2 through a stable current source I2 and a resistor R3 or a resistor R4; so as to meet the opening and closing of the output driving circuit switches phi 7-phi 8 of the later stage.

When the type of the output level is LVDS level output, the specific implementation mode of the step 2) is as follows: under the action of the secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, the switches phi 3 and phi 4 are controlled to be opened, the switches phi 1 and phi 2 are turned off, and meanwhile, a dynamic current source I1 is reduced, and a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 are formed and output so as to meet the requirement of the on-off of the switches phi 5 to phi 6 of the output driving circuit of the later stage; receiving a positive differential signal INP through a transistor MN3, receiving a negative differential signal INN through a transistor MN4, controlling on of phi 5 and phi 8 and off of phi 6 and phi 7 under the condition of a secondary power supply VDDL, and generating a second-stage pre-driving positive differential signal OUTP2 and a second-stage pre-driving negative differential signal OUTN2 through a stable current source I2 and a resistor R3 or a resistor R4; so as to meet the opening and closing of the output driving circuit switches phi 7-phi 8 of the later stage.

When the type of the output level is CML level output, especially the on state and the control state, the same as the type of the output level is LVDS, namely: the specific implementation mode of the step 2) is as follows: under the action of the secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, the switches phi 3 and phi 4 are controlled to be opened, the switches phi 1 and phi 2 are turned off, and meanwhile, a dynamic current source I1 is reduced, and a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 are formed and output so as to meet the requirement of the on-off of the switches phi 5 to phi 6 of the output driving circuit of the later stage; the transistor MN3 receives the positive differential signal INP, the transistor MN4 receives the negative differential signal INN, the phi 5, the phi 7 and the phi 8 are controlled to be opened and the phi 6 is controlled to be closed under the condition of the secondary power supply VDDL, and the second-stage pre-driving positive differential signal OUTP2 and the second-stage pre-driving negative differential signal OUTN2 are generated through the stable current source I2 and the resistor R3 or the resistor R4 so as to meet the opening and closing of the switches phi 7-phi 8 of the output driving circuit of the later stage.

3) And respectively outputting LVPECL level, LVDS level or CML level according to the regulation result. That is, in the output driving circuit, the switches Φ5 to Φ8 are matched with the tail current I3, and the driving output of various differential levels such as LVPECL, LVDS, CML and the like is realized by the output impedance of the switch and the magnitude of the tail current. Wherein phi 5-phi 8 can be realized by NMOS tube, PMOS tube or transmission gate composed of NMOS tube and PMOS tube.

Claims

1. A multi-level output circuit for a multi-voltage domain unified architecture, characterized by: the multi-level output circuit for the multi-voltage domain unified architecture comprises a positive differential signal INP input end, a negative differential signal INN input end, a power supply circuit, a first-stage pre-driving circuit, a second-stage pre-driving circuit, an output driving circuit, a positive differential signal OUTP output end and a negative differential signal OUTN output end; the positive differential signal INP input end and the negative differential signal INN input end are respectively connected into the output driving circuit through the first-stage pre-driving circuit; the positive differential signal INP input end and the negative differential signal INN input end are respectively connected into the output driving circuit through the second-stage pre-driving circuit; the power supply circuit is respectively connected with the first-stage pre-driving circuit, the second-stage pre-driving circuit and the output driving circuit; the output driving circuit is respectively connected with the output end of the positive differential signal OUTP and the output end of the negative differential signal OUTN.

2. The multi-level output circuit for a multi-voltage domain unified architecture of claim 1, wherein: the power supply circuit comprises a power supply VDD and a low dropout linear regulator LDO; the power supply VDD forms a secondary power supply VDDL through a low dropout linear regulator LDO; the power supply VDD is respectively connected with the first-stage pre-driving circuit and the output driving circuit; the secondary power supply VDDL is respectively connected to the first-stage pre-driving circuit and the second-stage pre-driving circuit.

3. The multi-level output circuit for a multi-voltage domain unified architecture of claim 2, wherein: the first-stage pre-driving circuit comprises a dynamic current source I1, a switch phi 2, a switch phi 3, a switch phi 4, a resistor R1, a resistor R2, a transistor MN1, a transistor MN2, a first-stage pre-driving positive differential signal OUTP1 output end and a first-stage pre-driving negative differential signal OUTN1 output end; one end of the dynamic current source I1 is grounded, and the other end of the dynamic current source I1 is respectively connected with the transistor MN1 and the transistor MN2; the input end of the forward differential signal INP is connected to the transistor MN1; the negative differential signal INN input end is connected to the transistor MN2; the power supply VDD is respectively connected with a switch phi 1 and a switch phi 2; the secondary power supply VDDL is respectively connected with a switch phi 3 and a switch phi 4; the transistor MN1 is connected to a switch phi 1 or a switch phi 3 through a resistor R1; the transistor MN2 is connected to a switch phi 2 or a switch phi 4 through a resistor R2; the resistor R1 is connected to an output driving circuit through the output end of the first-stage pre-driving negative differential signal OUTN1; the resistor R2 is connected to the output driving circuit through the output end of the first-stage pre-driving forward differential signal OUTP 1.

4. A multi-level output circuit for a multi-voltage domain unified architecture as recited in claim 3 wherein: the dynamic current source I1 is connected to the source of the transistor MN1 and the source of the transistor MN2, respectively; the input end of the forward differential signal INP is connected with the grid electrode of the transistor MN1; the negative differential signal INN input end is connected with the grid electrode of the transistor MN2; the drain electrode of the transistor MN1 is connected to a switch phi 1 or a switch phi 3 through a resistor R1; the drain of the transistor MN2 is connected to the switch Φ2 or the switch Φ4 through the resistor R2.

5. The multi-level output circuit for a multi-voltage domain unified architecture of claim 4, wherein: the second-stage pre-driving circuit comprises a resistor R3, a resistor R4, a transistor MN3, a transistor MN4, a second-stage pre-driving positive differential signal OUTP2 output end, a second-stage pre-driving negative differential signal OUTN2 output end and a stable current source I2; one end of the stable current source I2 is grounded, and the other end of the stable current source I2 is respectively connected with the transistor MN3 and the transistor MN4; the input end of the forward differential signal INP is connected to the transistor MN3; the negative differential signal INN input end is connected to the transistor MN4; the secondary power supply VDDL is connected to the transistor MN3 through a resistor R3; the secondary power supply VDDL is connected to the transistor MN4 through a resistor R4; the resistor R3 is connected to an output driving circuit through the output end of the second-stage pre-driving negative differential signal OUTN2; the resistor R4 is connected to the output driving circuit through the output end of the second-stage pre-driving forward differential signal OUTP 2.

6. The multi-level output circuit for a multi-voltage domain unified architecture of claim 5, wherein: the stable current source I2 is connected to the source of the transistor MN3 and the source of the transistor MN4, respectively; the input end of the forward differential signal INP is connected with the grid electrode of the transistor MN3; the negative differential signal INN input end is connected with the grid electrode of the transistor MN4; the drain electrode of the transistor MN3 is connected with the resistor R3; the drain of the transistor MN4 is connected to the resistor R4.

7. The multi-level output circuit for a multi-voltage domain unified architecture of claim 6, wherein: the output driving circuit comprises a switch phi 5, a switch phi 6, a switch phi 7, a switch phi 8 and a dynamic current source I3; the power supply VDD is respectively connected with the switch phi 5 and the switch phi 6; one end of the dynamic current source I3 is grounded, and the other end of the dynamic current source I is connected with the switch phi 7 and the switch phi 8 respectively; the output end of the first-stage pre-driving forward differential signal OUTP1 is connected to the output end of the forward differential signal OUTP through a switch phi 5; the output end of the first-stage pre-driving negative differential signal OUTN1 is connected to the output end of the negative differential signal OUTN through a switch phi 6; the output end of the second-stage pre-driving forward differential signal OUTP2 is connected to the output end of the forward differential signal OUTP through a switch phi 8, a switch phi 6 and a switch phi 5; the output end of the second-stage pre-driving negative differential signal OUTN2 is connected to the output end of the negative differential signal OUTN through a switch phi 7, a switch phi 5 and a switch phi 6.

8. A multi-level output method based on the multi-level output circuit for the multi-voltage domain unified architecture according to claim 7, characterized in that: the method comprises the following steps:

1) Acquiring a power supply VDD and a secondary power supply VDDL;

9. The multi-level output method for a multi-level output circuit of a multi-voltage domain unified architecture of claim 8, wherein: in the step 1), the voltage of the secondary power supply VDDL is lower than the voltage of the power supply VDD; the power supply VDD generates the secondary power supply VDDL through a low dropout linear regulator LDO.

10. The multi-level output method for a multi-level output circuit of a multi-voltage domain unified architecture of claim 9, wherein: when the type of the level to be output is LVPECL level output, the specific implementation manner of the step 2) is as follows: under the action of a power supply VDD or a secondary power supply VDDL, a positive differential signal INP is received through a transistor MN1, a negative differential signal INN is received through a transistor MN2, switches phi 1 and phi 2 are controlled to be opened, and switches phi 3 and phi 4 are controlled to be closed, and meanwhile, a dynamic current source I1 is increased to form and promote a first-stage pre-driving positive differential signal OUTP1 and a first-stage pre-driving negative differential signal OUTN1 to rise in high level; receiving a positive differential signal INP through a transistor MN3, receiving a negative differential signal INN through a transistor MN4, and generating a second-stage pre-driving positive differential signal OUTP2 and a second-stage pre-driving negative differential signal OUTN2 through a stable current source I2 and a resistor R3 or a resistor R4 under the action of a secondary power supply VDDL;