CN117878059A

CN117878059A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN117878059A
Application number: CN202311755990.5A
Authority: CN
Inventors: 黄麒; 许哲嘉; 曹志彬; 黄至鸿
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-12-19
Filing date: 2023-12-19
Publication date: 2024-04-12

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The method comprises the following steps: first and second channel structures are formed, and a first type of source/drain structure attached to opposite sides of the first channel structure and a second type of source/drain structure attached to opposite sides of the second channel structure are formed. The method further comprises the steps of: a first gate dielectric layer is formed having a first portion overlying the first channel structure and a second portion overlying the second channel structure, and a first metal element is driven into the first portion of the first gate dielectric layer. The method further comprises the steps of: a cap layer is formed over the first portion and the second portion of the first gate dielectric layer and an annealing process is performed on the first gate dielectric layer under the cap layer.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to semiconductor structures and methods of fabricating the same.

Background

The electronics industry is increasingly demanding smaller, faster electronic devices that are capable of performing more and more complex and complex functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance, and low power Integrated Circuits (ICs). Up to now, these objectives have been largely achieved by shrinking the semiconductor IC size (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into the semiconductor manufacturing process. Accordingly, similar advances in semiconductor manufacturing processes and techniques are needed to realize continued advances in semiconductor ICs and devices.

Recently, multi-gate devices have been introduced in order to improve gate control by increasing gate-to-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). However, the fabrication of integrated multi-gate devices can still be challenging.

Disclosure of Invention

According to an aspect of embodiments of the present application, there is provided a method for manufacturing a semiconductor structure, comprising: forming a first channel structure in the first region and forming a second channel structure in the second region; forming a first type of source/drain structure attached to opposite sides of the first channel structure and a second type of source/drain structure attached to opposite sides of the second channel structure; forming a first gate dielectric layer having a first portion overlying the first channel structure and a second portion overlying the second channel structure; driving a first metal element into a first portion of the first gate dielectric layer; forming a cap layer over the first portion and the second portion of the first gate dielectric layer after driving the first metal element into the first portion of the first gate dielectric layer; performing an annealing process on the first gate dielectric layer under the cap layer; and forming a work function metal layer that extends continuously from the first region to the second region and covers the first channel structure and the second channel structure.

According to another aspect of embodiments of the present application, there is provided a method for manufacturing a semiconductor structure, comprising: forming a first type of source/drain structure and a second type of source/drain structure over a substrate; forming a first channel structure vertically suspended above the substrate and sandwiched between source/drain structures of a first type; forming a second channel structure vertically suspended above the substrate and sandwiched between source/drain structures of a second type; forming a first gate dielectric layer having a first portion wrapped around the first channel structure and a second portion wrapped around the second channel structure; forming a first dipole layer in physical contact with a first portion of the first gate dielectric layer and spaced apart from a second portion of the first gate dielectric layer; forming a second gate dielectric layer over the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of the same dielectric material; forming a cap layer surrounding the first channel structure and the second channel structure over the second gate dielectric layer; and annealing the first gate dielectric layer and the second gate dielectric layer after forming the cap layer.

According to yet another aspect of embodiments of the present application, there is provided a semiconductor structure comprising: a first type of source/drain structure formed in a first region over the substrate and a second type of source/drain structure formed in a second region over the substrate; first channel structures separated from each other along a first direction and interposed with source/drain structures of a first type along a second direction different from the first direction; the second channel structure, separate each other along the first direction, and insert the source/drain structure of the second type along the second direction; a gate dielectric layer having a first portion wrapped around the first channel structure in a first region and a second portion wrapped around the second channel structure in a second region, wherein the first portion of the gate dielectric layer is doped with a first metal element and a concentration of the first metal element in a lower portion of the first portion of the gate dielectric layer is greater than a concentration of the first metal element in an upper portion of the first portion of the gate dielectric layer; and a work function metal layer formed over the first portion and the second portion of the gate dielectric layer.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1C illustrate schematic perspective views of intermediate stages in the manufacture of a semiconductor structure, in accordance with some embodiments.

FIGS. 2A-1 through 2J-1, 2A-2 through 2J-2, and 2A-3 through 2J-3 illustrate the respective lines Y in FIG. 1C according to some embodiments _SD -Y _SD ' i.e. in the Y direction, Y _MG -Y _MG 'i.e., in the Y-direction, and X-X' (i.e., in the X-direction) at an intermediate stage of the fabrication of the semiconductor structure.

FIGS. 2J-4 illustrate the block BK illustrated in FIGS. 2J-2, according to some embodiments _2J An enlarged cross-sectional view of a semiconductor structure of (a).

Fig. 2J-5 illustrate schematic top views of semiconductor structures according to some embodiments.

FIGS. 2J '-1 and 2J' -2 illustrate the respective lines Y along FIG. 1C according to some embodiments _MG -Y _MG Cross-sectional views of the semiconductor structure shown in 'and X-X'.

FIGS. 3A-3H illustrate gate structures (i.e., block BK shown in FIGS. 2I-2) for fabricating semiconductor structures according to some embodiments _2I An enlarged cross-sectional view of the intermediate stage of (a) the region(s).

Fig. 3H' illustrates an enlarged cross-sectional view of a semiconductor structure in accordance with some embodiments.

Fig. 4A and 4B illustrate enlarged cross-sectional views of intermediate stages in the manufacture of a semiconductor structure in accordance with some embodiments.

Fig. 5A-5G illustrate enlarged cross-sectional views of intermediate stages in the manufacture of a semiconductor structure in accordance with some embodiments.

Fig. 6A-1 through 6J-1, 6A-2 through 6J-2, and 6A-3 through 6J-3 illustrate cross-sectional views of intermediate stages in the fabrication of a semiconductor structure according to some embodiments.

FIG. 6J-4 illustrates the block BK illustrated in FIG. 6J-2, according to some embodiments _6J An enlarged cross-sectional view of a semiconductor structure of (a).

Fig. 6J-5 illustrate schematic top views of semiconductor structures according to some embodiments.

Fig. 6J '-1 and 6J' -2 illustrate cross-sectional views of semiconductor structures according to some embodiments.

Fig. 7A-1 through 7Q-1, fig. 7A-2 through 7Q-2, and fig. 7A-3 through 7Q-3 illustrate cross-sectional views of intermediate stages in the fabrication of a semiconductor structure in accordance with some embodiments.

FIG. 7Q-4 illustrates the block BK illustrated in FIG. 7Q-3, according to some embodiments _7Q An enlarged cross-sectional view of a semiconductor structure of (a).

Fig. 7Q-5 illustrate schematic top views of semiconductor structures according to some embodiments.

Fig. 7Q '-1 and 7Q' -2 illustrate cross-sectional views of semiconductor structures according to some embodiments.

Fig. 8-1, 8-2, and 8-3 illustrate cross-sectional views of semiconductor structures according to some embodiments.

8-4 illustrate the block BK illustrated in FIGS. 8-3 according to some embodiments ₈ An enlarged cross-sectional view of a semiconductor structure of (a).

Fig. 9-1, 9-2, and 9-3 illustrate cross-sectional views of semiconductor structures according to some embodiments.

Fig. 9-4 illustrate schematic top views of semiconductor structures according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. In the various views and illustrative embodiments, identical reference numerals are used to designate identical elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the operations described may be replaced or eliminated for other embodiments of the method.

Nanostructure transistors (e.g., nanoplate transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, and full-gate-all-around (GAA) transistors) described below may be patterned by any suitable method. For example, structures may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the nanostructures.

Embodiments of semiconductor structures and methods of forming the same are provided. The semiconductor structure may include a first type (e.g., n-type) transistor formed in a first region and a second type (e.g., p-type) transistor formed in a second region adjacent to the first region. Both the first type and the second type of transistor may include a channel structure, such as a nanostructure, formed on the substrate, and a gate structure formed over the channel structure. Further, the forming of the gate structure may include forming a dielectric material in both the first region and the second region, and treating the dielectric material with an additional metal element in the first region but not in the second region. After processing the dielectric material, a single work function metal layer (e.g., a p-type work function metal layer) may be formed over the dielectric material in the first region and the second region.

In the first type and the second type transistors, a dielectric material may be used as a gate dielectric layer of the gate structure, and threshold voltages of the first type and the second type transistors may be different. That is, although the same work function metal layer is formed in both the first type and the second type transistors, the first type and the first type transistors may have different threshold voltages due to the additional metal element being processed in the first region of the dielectric material. Thus, by treating the gate dielectric layer with additional metal elements, the threshold voltage of the transistor can be adjusted and additional work function metal layers are not required. Therefore, there will be no material boundary of work function metallic material between the transistors of the first type and the second type, and the performance and reliability of the resulting transistor can be improved.

Fig. 1A-1C illustrate schematic perspective views of intermediate stages in the manufacture of a semiconductor structure 100 in accordance with some embodiments. FIGS. 2A-1 through 2J-1, 2A-2 through 2J-2, and 2A-3 through 2J-3 illustrate the respective lines Y in FIG. 1C according to some embodiments _SD -Y _SD ' i.e. in the Y direction, Y _MG -Y _MG 'i.e., in the Y-direction, and X-X' (i.e., in the X-direction) show cross-sectional views at intermediate stages of the fabrication of semiconductor structure 100. More specifically, fig. 2A-1, 2A-2, and 2A-3 illustrate cross-sectional views of an intermediate stage of the semiconductor structure 100 illustrated in fig. 1C, and fig. 2B-1 through 2J-1, 2B-2 through 2J-2, and 2B-3 through 2J-3 illustrate cross-sectional views after an intermediate stage of fabricating the semiconductor structure 100 in accordance with some embodiments.

Semiconductor structure 100 may include a multi-gate device and may be included in a microprocessor, memory, or other IC device. For example, semiconductor structure 100 may be part of an IC chip, including various passive and/or active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.

According to some embodiments, a substrate 102 including a first region 10 and a second region 20 is formed, and a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed over the first region 10 and the second region 20 of the substrate 102, as shown in fig. 1A. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and/or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide. The alloy semiconductor material may include, but is not limited to SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP.

In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are alternately stacked on the substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe and the second semiconductor material layer 108 is made of silicon. It should be noted that although four first semiconductor material layers 106 and three second semiconductor material layers 108 are shown in fig. 1A, the semiconductor stack may include fewer or more first semiconductor material layers 106 and second semiconductor material layers 108 alternately stacked. For example, the semiconductor stack may include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed using Low Pressure Chemical Vapor Deposition (LPCVD), an epitaxial growth process, other suitable methods, or a combination thereof. In some embodiments, the epitaxial growth process includes Molecular Beam Epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), or Vapor Phase Epitaxy (VPE).

After forming the first semiconductor material layer 106 and the second semiconductor material layer 108 as semiconductor stacks over the substrate 102, the semiconductor stacks are patterned to form the fin structure 104-1 in the first region 10 and the fin structure 104-2 in the second region 20, as shown in fig. 1B, according to some embodiments. Fin structures 104-1 and 104-2 may extend longitudinally in the X-direction. In some embodiments, the patterning process includes forming a mask structure 110 over the stack of semiconductor material and etching the stack of semiconductor material and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure including a pad oxide layer and a nitride layer formed on the pad oxide layer. The pad oxide layer may be made of silicon oxide formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride formed by CVD such as LPCVD or Plasma Enhanced CVD (PECVD). In some embodiments, the fin structures 104-1 and 104-2 include a base fin structure 104B and a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 formed over the base fin structure 104.

According to some embodiments, after forming fin structures 104-1 and 104-2, isolation structures 116 are formed around fin structures 104-1 and 104-2, as shown in fig. 1C, 2A-1, 2A-2, and 2A-3. Isolation structure 116 is configured to electrically isolate active regions of the semiconductor structure (e.g., fin structures 104-1 and 104-2), and is also referred to as a Shallow Trench Isolation (STI) feature according to some embodiments.

More specifically, an insulating layer may be formed around the fin structures 104-1 and 104-2 and covering the fin structures 104-1 and 104-2, and the insulating layer may be recessed to form the isolation structure 116, with the fin structures 104-1 and 104-2 protruding from a top surface of the isolation structure 116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In addition, a liner layer (not shown) may be formed prior to forming the insulating layer, and the liner layer may also be recessed with the insulating layer to form isolation structures 116. In some embodiments, the liner layer includes multiple layers of dielectric material.

Thereafter, in accordance with some embodiments, as shown in FIGS. 2B-1, 2B-2, and 2B-3, a dummy gate structure 130 is formed across fin structures 104-1 and 104-2. The dummy gate structure 130 may be used to define a channel region of the resulting semiconductor structure 100.

In some embodiments, dummy gate structure 130 includes a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, dummy gate dielectric layer 132 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), hfO ₂ HfZrO, hfSiO, hfTiO, hfAlO or combinations thereof. In some embodiments, dummy gate dielectric layer 132 is formed using thermal oxidation, CVD, ALD, physical Vapor Deposition (PVD), another suitable method, or combinations thereof.

In some embodiments, the dummy gate electrode layer 134 is made of a conductive material, such as polysilicon (poly-Si), polysilicon germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed using CVD, PVD, or combinations thereof.

In some embodiments, a hard mask layer 136 is formed over the dummy gate electrode layer 134. In some embodiments, the hard mask layer 136 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride.

The formation of the dummy gate structure 130 may include conformally forming a dielectric material as the dummy gate dielectric layer 132. Then, a conductive material may be formed over the dielectric material as the dummy gate electrode layer 134, and a hard mask layer 136 may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer 136 to form the dummy gate structure 130.

After forming the dummy gate structure 130, a spacer layer 138 is formed to cover the dummy gate structure 130 and the fin structures 104-1 and fin structures according to some embodiments104-2 as shown in fig. 2C-1, 2C-2 and 2C-3. In some embodiments, spacer layer 138 is made of one or more dielectric materials. The dielectric material may include silicon oxide (SiO ₂ ) Silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), and/or combinations thereof.

According to some embodiments, after forming spacer layer 138, an etching process is performed to form gate spacers 140 and fin spacers 142 along with spacer layer 138 and to form source/drain recesses 144 in fin structures 104-1 and 104-2, as shown in fig. 2D-1, 2D-2, and 2D-3. The gate spacers 140 may be configured to separate the source/drain structures (subsequently formed) from the dummy gate structures 130, and the fin spacers 142 may be configured to limit the growth of the source/drain structures formed therein.

More specifically, according to some embodiments, spacer layer 138 is etched to form gate spacers 140 on opposite sidewalls of dummy gate structure 130 and to form fin spacers 142 that cover sidewalls of fin structures 104-1 and 104-2. Furthermore, during the etching process, portions of fin structures 104-1 and 104-2 not covered by dummy gate structure 130 and gate spacers 140 are etched to form source/drain recesses 144, according to some embodiments. The etching process may be an anisotropic etching process, such as a dry plasma etch, and the dummy gate structure 130 and the gate spacer 140 may be used as an etching mask during the etching process. In some embodiments, the isolation structures 116 are also slightly etched during the etching process.

According to some embodiments, after forming the source/drain recesses 144, the first semiconductor material layer 106 exposed by the source/drain recesses 144 is laterally recessed to form recesses 146, as shown in fig. 2E-1, 2E-2, and 2E-3. In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structures 104-1 and 104-2 from the source/drain recesses 144. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etch rate (or amount of etching) than the second semiconductor material layer 108, thereby forming recesses 146 between adjacent second semiconductor material layers 108. In some embodiments, the second semiconductor material layer 108 is also slightly etched during the etching process, such that the portion of the second semiconductor material layer 108 exposed by the recess 146 becomes thinner than other portions, according to some embodiments. In some embodiments, the etching process is an isotropic etch, such as a dry chemical etch, a remote plasma etch, a wet chemical etch, another suitable technique, and/or combinations thereof.

Next, according to some embodiments, an internal spacer 148 is formed in the recess 146 between the second semiconductor material layers 108, as shown in fig. 2F-1, 2F-2, and 2F-3. The internal spacers 148 may be configured to separate the source/drain structures and the gate structures formed in a subsequent manufacturing process. As previously described, according to some embodiments, since the second semiconductor material layer 108 is also partially etched when forming the recess 146, the inner spacer 148 formed in the recess 146 is thicker than the thickness of the first semiconductor material layer 106. Furthermore, according to some embodiments, the inner spacer 148 has curved sidewalls. In some embodiments, the inner spacer 148 is made of a dielectric material, such as silicon oxide (SiO ₂ ) Silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), or combinations thereof.

According to some embodiments, after forming the internal spacers 148, source/drain structures 150-1 and 150-2 are formed in the source/drain recesses 144 of the fin structures 104-1 and 104-2, respectively, as shown in fig. 2G-1, 2G-2, and 2G-3. The source/drain structures described herein may refer to the source or drain, individually or collectively, depending on the context.

In some embodiments, the source/drain structures 150-1 and 150-2 are formed using a separate epitaxial growth process, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or a combination thereof. In some embodiments, the source/drain structures 150-1 and 150-2 are made of any suitable material, such as Ge, si, gaAs, alGaAs, siGe, gaAsP, siP, siC, siCP, or a combination thereof. In some embodiments, the source/drain structures 150-1 and 150-2 are doped in-situ during the epitaxial growth process. In some embodiments, source/drain structures 150-1 and 150-2 are doped in one or more implantation processes after the epitaxial growth process.

In some embodiments, the source/drain structures 150-1 and 150-2 are made of materials having different conductivity types. In some embodiments, source/drain structure 150-1 is an n-type source/drain structure and source/drain structure 150-2 is a p-type source/drain structure. For example, the source/drain structure 150-1 may be epitaxially grown Si and doped with carbon to form a silicon: carbon (Si: C) source/drain feature, and doped with phosphorus to form silicon: phosphorus (Si: P) source/drain features, or carbon and phosphorus doped to form carbon silicon phosphorus (SiCP) source/drain features. For example, the source/drain structure 150-2 may be epitaxially grown SiGe doped with boron (B).

According to some embodiments, after forming the source/drain structures 150-1 and 150-2, a Contact Etch Stop Layer (CESL) 160 is conformally formed to cover the source/source structures 150-2 and 150-2, and an interlayer dielectric (ILD) layer 162 is formed over the contact etch stop layer 160, as shown in fig. 2H-1, 2H-2, and 2H-3.

In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used to contact the etch stop layer 160 may be conformally deposited on the semiconductor structure by performing CVD, ALD, other application methods, or combinations thereof.

Interlayer dielectric layer 162 may include multiple layers made of various dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other suitable low-k dielectric materials. Interlayer dielectric layer 162 may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other applicable processes.

According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process such as a CMP or an etchback process is performed until the dummy gate electrode layer 134 is exposed, as shown in fig. 2H-2 and 2H-3.

Next, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench 166, as shown in fig. 2I-1, 2I-2, and 2I-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'-1 and 108' -2 with the second semiconductor material layer 108 of the fin structures 104-1 and 104-2, respectively. As shown in fig. 2I-3, channel structures 108'-1 and 108' -2 are vertically suspended on the substrate and spaced apart from each other in the Z-direction, according to some embodiments. Furthermore, according to some embodiments, channel structures 108'-1 and 108' -2 extend laterally between source/drain structures 105-1 and 150-2, respectively, in the X direction and interpose source/drain structure 105-2. Although not explicitly shown in the figures, the channel structures 108'-1 and 108' -2 and the base fin structure 104B may have rounded corners.

The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 134 may be made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 134. Thereafter, the dummy gate dielectric layer 132 may be removed using a plasma dry etch, a dry chemical etch, and/or a wet etch. The first semiconductor material layer 106 may be removed by performing a selective wet etch process, such as an APM (e.g., ammonia-hydrogen peroxide-water mixture) etch process. For example, wet etching processes use etchants such as ammonium hydroxide (NH ₄ OH), TMAH, ethylenediamine catechol (EDP), and/or potassium hydroxide (KOH) solutions.

According to some embodiments, after forming the gate trench 166, a gate structure 168 is formed in the gate trench 166, as shown in fig. 2J-1, 2J-2, and 2J-3. Fig. 3A-3H illustrate intermediate stages of forming the gate structure 168 of the semiconductor structure 100 (i.e., block BK shown in fig. 2I-2) according to some embodiments _2I An enlarged cross-sectional view of the region).

More specifically, according to some embodiments, after forming channel structures 108'-1 and 108' -2, interface layer 170, gate dielectric layer 172, and dipole layer 174 are formed to encapsulate channel structures 108'-1 and 108' -2 and cover the exposed top portions of base fin structure 104B of fin structures 104-1 and 104-2, as shown in fig. 3A.

Interface layer 170 may be used to improve the interface between channel structures 108'-1 and 108' -2 and subsequently formed dielectric layers. In addition, interface layer 170 may help suppress mobility degradation of charge carriers in channel structures 108'-1 and 108' -2 that serve as channel regions for transistors. In some embodiments, interface layer 170 is an oxide layer formed by performing a thermal process. In some embodiments, the thickness of interface layer 170 is in the range from about 0.5nm to about 1.5 nm.

According to some embodiments, after forming interface layer 170, gate dielectric layer 172 is conformally formed to cover the bottom surfaces and sidewalls of interface layer 170 and gate trench 166. In some embodiments, the gate dielectric layer 172 includes a first portion 172-1 surrounding the channel structure 108'-1 and a second portion 172-2 surrounding the channel structure 108' -2. In some embodiments, gate dielectric layer 172 is made of a dielectric material, such as HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloy, la ₂ O ₃ –Al ₂ O ₃ Or LaO, other suitable high-k dielectric material, or a combination thereof. In some embodiments, CVD, ALD, other applicable methods, or combinations thereof are used to form gate dielectric layer 172. In some embodiments, the thickness of the gate dielectric layer 172 is in the range from about 1nm to about 2 nm.

According to some embodiments, after forming the gate dielectric layer 172, a dipole layer 174 is formed over the top surface of the gate dielectric layer 172 in the first region 10 and the second region 20, and the dipole layer 174 is in physical contact with the top surface of the gate dielectric layer 172. The dipole layer 174 is configured to modify the gate dielectric layer 172 to increase or decrease the effect of the voltage applied to the gate electrode when turning on or off the resulting transistor. That is, the threshold voltage of the resulting transistor can be adjusted. In some embodiments, the dipole layer 174 includes a metal element, such as La, Y, al, sr, er, zn, sc, ti, nb. In some embodiments, the thickness of the dipole layer 174 is in the range from about 0.5nm to about 2.5 nm.

According to some embodimentsAfter the interfacial layer 170, the gate dielectric layer 172, and the dipole layer 174 are formed to encapsulate the channel structures 108'-1 and 108' -2, a hard mask layer 176 is formed to cover the channel structures 108'-1 and 108' -2 in the first region 10 and the second region 20, as shown in fig. 3A. In some embodiments, the space between adjacent stacked channel structures 108'-1 and the space between adjacent stacked channel structures 108' -2 are completely filled by the hard mask layer 176, according to some embodiments. In some embodiments, the hard mask layer 176 is made of an oxide or nitride, such as SiO _x 、AlO _x 、ZrO ₂ SiN, tiN, etc. In some embodiments, the hard mask layer 176 has a thickness in a range from about 1nm to about 5 nm.

Next, according to some embodiments, as shown in fig. 3B, a photoresist layer 178 is formed to cover the structures in the first region 10, and the hard mask layer 176 and the dipole layer 174 in the second region 20 that are not covered by the photoresist layer 178 are removed. According to some embodiments, after removing the dipole layer 174 in the second region 20, the photoresist layer 178 at the first region 10 is also removed, and a treatment process 180 is performed to form a modified first portion 172' -1 of the gate dielectric layer 172 in the first region 10, as shown in fig. 3C. More specifically, the metal element of the dipole layer 174 is driven (e.g., diffused) into the first portion 172-1 of the gate dielectric layer 172 in the first region 10 to form a modified first portion 172' -1. The metal element driven into the first portion 172-1 of the gate dielectric layer 172 causes a dipole effect that increases or decreases the effect of the voltage applied to the gate electrode on turning on or off the transistor formed in the first region 10. That is, the effective work function of the resulting transistor is modulated, thereby increasing or decreasing the threshold voltage of the transistor formed in the first region 10. In some embodiments, the threshold voltage of the resulting transistor in the first region 10 is different from the threshold voltage of the resulting crystal in the second region 20 by treating the first portion 172-1 of the gate dielectric layer 172 with the metal element of the dipole layer 174 in the first region 10.

Meanwhile, according to some embodiments, since the dipole layer 174 in the second region 20 has been removed prior to the processing process 180, the second portion 172-2 of the gate dielectric layer 172 in the second region is not processed (e.g., modified), and thus the threshold voltage of the transistor in the second region 20 is different from the threshold voltage of the transistor in the first region 10.

In some embodiments, the treatment process 180 is an annealing process. In some embodiments, the annealing process is performed at a temperature in the range of about 400 ℃ to about 1000 ℃. In some embodiments, the annealing process is performed for about 0.5 seconds to about 30 seconds.

According to some embodiments, after performing the treatment process 180, the dipole layer 174 in the first region 10 is removed, as shown in fig. 3D. The dipole layer 174 may be removed by performing an etching process such as a dry etching process or a wet etching process.

Next, according to some embodiments, as shown in fig. 3E, an additional gate dielectric layer 182 is formed over the modified first portion 172' -1 of the gate dielectric layer 172 in the first region 10 and over the second portion 172-2 of the gate dielectric layer 172 in the second region 20. As previously described, according to some embodiments, the first portion 172-1 of the gate dielectric layer 172 is processed to adjust the threshold voltage of the resulting transistor. However, if the gate dielectric layer 172 is too thick, modification of the first portion 172-1 of the gate dielectric layer 172 may be challenging. On the other hand, if the gate dielectric layer in the gate structure is not thick enough, the risk of electrical leakage may increase. Thus, the relatively thin gate dielectric layer 172 is first formed and processed (i.e., tightly adhered to the channel structure 108 '-1) to form a modified first portion 172' -1 of the gate dielectric layer 172, and an additional gate dielectric layer 182 is formed over the gate dielectric layer 172 such that the combination of gate dielectric layers 172 and 182 can achieve a desired thickness.

In some embodiments, the sum of the thickness of gate dielectric layer 172 and the thickness of gate dielectric layer 182 is in the range from about 1nm to about 5 nm. In some embodiments, gate dielectric layer 182 is thinner than gate dielectric layer 172. In some embodiments, gate dielectric layer 182 is made of the same dielectric material as gate dielectric layer 172, but gate dielectric layer 180 does not include the metal element of dipole layer 174.

In some embodiments, gate dielectric layer 182 is made of a dielectric material, such as HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hf ZrO, zirconia, alumina, titania, hafnium oxide-alumina (HfO) ₂ -Al ₂ O ₃ ) Alloys, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, CVD, ALD, other applicable methods, or a combination thereof are used to form the gate dielectric layer 182.

According to some embodiments, after forming the gate dielectric layer 182, a cap layer 184 is formed over the gate dielectric layer 182 and a post-deposition annealing process 186 is performed, as shown in fig. 3F. Since gate dielectric layer 182 and gate dielectric layer 172 are covered by cap layer 184 during post-deposition anneal process 186, gate dielectric layer 182 and gate dielectric layer 172 may be densified during post-deposition anneal process 186. In some embodiments, gate dielectric layer 172 and gate dielectric layer 182 are made of the same dielectric material, and thus no interface is shown between them after post-deposition annealing process 186 is performed. That is, gate dielectric layer 172 and gate dielectric layer 182 may form a gate dielectric structure having a first portion wrapped around channel structure 108'-1 and a second portion wrapped around channel structure 108' -2. Furthermore, according to some embodiments, a lower portion of the first portion of the gate dielectric structure (i.e., the modified first portion 172' -1 of the gate dielectric layer 172) includes the metal elements of the dipole layer 174, while an upper portion of the first portion of the gate dielectric structure and the entire second portion (i.e., the second portion 172-1 of the gate dielectric layer 172 and the gate dielectric layer 182) do not include the metal elements of the dipole layer 174. In some embodiments, the concentration of the first metal element in a lower portion of the first portion of the gate dielectric layer is greater than the concentration of the first metal element in an upper portion of the first portion of the gate dielectric layer.

In some embodiments, the cap layer 184 is made of a metal-containing material, including metals such as Ti, ta, and the like. In some embodiments, the metal-containing material further comprises N and/or Si. In some embodiments, cap layer 184 is made of TiN. In some embodiments, the thickness of the cap layer 184 is in the range from about 1nm to about 3 nm. In some embodiments, the post-deposition annealing process 186 is performed at a temperature in the range of about 800 ℃ to about 1000 ℃. Furthermore, since the threshold voltage of the resulting transistor in the first region 10 may be achieved by modification of the gate dielectric layer 172, the cap layer 184 may not need to be removed after the post-deposition annealing process 186. Thus, the gate dielectric 182 under the cap layer 184 is not damaged by removing the cap layer 184. In addition, cap layer 184 may help trap oxygen in interface layer 170, and thus interface layer 170 may become thinner.

According to some embodiments, after performing the post-deposition annealing process 186, a functional metal layer 190 is formed over the cap layer 184 in the first region 10 and the second region 20, as shown in fig. 3G. More specifically, according to some embodiments, the channel structure 108'-1 in the first region 10 and the channel structure 108' -2 in the second region 20 are both surrounded by the work function metal layer 190. In some embodiments, work function metal layer 190 is a p-type work function metal layer. In some embodiments, work function metal layer 190 is made of titanium nitride, tantalum nitride, tungsten nitride, tantalum, and the like. As previously described, since the threshold voltage of the resulting transistor in the first region 10 may be adjusted by modification of the gate dielectric layer 172, the resulting transistors in the first region 10 and the second region 20 may have different threshold voltages without the need to form an additional work function metal layer (e.g., an additional n-type work function metal layer).

According to some embodiments, after forming the work function metal layer 190, a gate fill layer 192 is formed to completely fill the gate trench 166, and a polishing process is performed until the interlayer dielectric layer 162 is exposed, as shown in fig. 3H, 2J-1, 2J-2, 2J-3, 2J-4, and 2J-5.

In some embodiments, a gate fill layer 192 is formed over the work function metal layer 190. In some embodiments, gate fill layer 192 is made of a conductive material, such as tungsten, titanium, tantalum, cobalt, copper, and the like. In some embodiments, the gate fill layer 192 is formed using CVD, ALD, electroplating, otherwise applicable methods, or a combination thereof. In some embodiments, the polishing process is a CMP process. In some embodiments, the gate fill layer 192 includes tungsten and fluorine. In some embodiments, fluorine in gate fill layer 192 diffuses into work function metal layer 190 and gate dielectric layers 182 and 172. The risk of leakage of gate dielectric layers 182 and 172 may be reduced due to the fluorine diffused therein.

FIGS. 2J-4 illustrate the block BK illustrated in FIGS. 2J-2, according to some embodiments _2J An enlarged cross-sectional view of semiconductor structure 100. Fig. 2J-5 illustrate schematic top views of semiconductor structure 100 according to some embodiments. For clarity, fig. 2J-5 are simplified to better understand the inventive concepts of the present disclosure. Additional components may be included in semiconductor structure 100, and some of the components described below may be replaced, modified, or eliminated.

As shown in fig. 2J-5, according to some embodiments, semiconductor structure 100 includes a transistor T-1 in first region 10 and a transistor T-2 in second region 20. Furthermore, according to some embodiments, the gate structure 168 extends over the channel structure 108'-1 of the fin structure 104-1 in the first region 10 and the channel structure 108' -2 of the fin structure 104-2 in the second region 20 and is oriented longitudinally in the Y-direction. In some embodiments, transistor T-1 is an n-type transistor and transistor T-2 is a p-type transistor.

In some embodiments, the transistor T-1 includes a channel structure 108' -1 separated from each other along the Z-direction, a source/drain structure 150-1 (e.g., an n-type source/drain structure) attached to opposite sides of the channel structure 108' -1, and a first portion 168-1 surrounding a gate structure 168 surrounding the channel structure 108' -1. Similarly, transistor T-2 includes channel structure 108' -2, source/drain structure 150-2 (e.g., a p-type source/drain structure) attached to opposite sides of channel structure 108' -2, and a second portion 168-2 surrounding gate structure 168 of channel structure 108' -2.

As previously described, according to some embodiments, although transistors T-1 and T-2 have different conductivity types and different threshold voltages, both the first portion 168-1 and the second portion 168-2 of the gate structure 168 have the same and single work function metal layer 190 (e.g., p-type work function metal layer) and the same gate fill layer 192. In some embodiments, the distance in the Z-direction between the gate fill layer 192 and the top surface of the topmost structure of the channel structure 108'-1 is substantially equal to the distance in the Z-direction between the gate fill layer 192 and the top surface of the topmost structure of the channel structure 108' -2.

In some embodiments, the work function metal layer 190 and the gate fill layer 192 extend continuously from the transistor T-1 in the first region 10 to the transistor T-2 in the second region 20. That is, according to some embodiments, there are no different types of work function metal layers stacked on top of each other at the boundary of transistors T-1 and T-2, nor are boundaries of the two work function metal layers. Therefore, it is possible to prevent a boundary effect due to metal diffusion in the different types of work function metal layers.

Further, by forming the modified first portion 172' -1 of the gate dielectric layer 172, the threshold voltages of the transistors T-1 and T-2 may be different from each other. In some embodiments, the gate dielectric layer 172 is an oxide layer, so that the metal elements therein will not readily diffuse. That is, although there is a boundary between the modified first portion 172' -1 of the gate dielectric layer 172 in the first region 10 and the second portion 172-2 of the gate dielectric layer 172 in the second region 20, as shown in fig. 2J-5, the boundary effect may not occur or may be less severe.

Furthermore, since the threshold voltages of transistors T-1 and T-2 are tuned by processing first portion 172-1 of gate dielectric layer 172, it may no longer be necessary to form multiple work function metal layers. That is, more space is available for forming the gate fill layer 192, and thus the performance of the transistors T-1 and T-2 may be improved.

FIGS. 2J '-1 and 2J' -2 illustrate the respective lines Y along FIG. 1C according to some embodiments _MG -Y _MG 'i.e., in the Y direction, and X-X' (i.e., in the X direction). Fig. 3H 'illustrates an enlarged cross-sectional view of semiconductor structure 100' in accordance with some embodiments. According to some embodiments, the semiconductor structure 100' may be similar to the semiconductor structure 100 described previously, except that the cap layer 184 between the channel structures 108' -1 and 108' -2 is incorporated. That is, according to some embodiments, the work function metal layer 190 does not extend between the channel structures 108'-1 and 108' -2. In some embodiments, the thickness of the cap layer 184 in the semiconductor structure 100' is greater than about 3nm. For forming semiconductorsThe processes and materials of structure 100' may be similar or identical to those previously described for forming semiconductor structure 100 and are not repeated here.

Fig. 4A and 4B illustrate enlarged cross-sectional views of intermediate stages in the manufacture of a semiconductor structure 100a in accordance with some embodiments. According to some embodiments, the semiconductor structure 100a may be similar to the previously described semiconductor structure 100, except that the cap layer 184 is removed. The processes and materials used to form the semiconductor structure 100a may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here. For example, according to some embodiments, other elements in the semiconductor structure 100a not shown in fig. 4B may be similar or identical to the elements shown in fig. 2J-1, 2J-2, 2J-3, 2J-4, and 2J-5 described previously.

More specifically, the processes shown in FIGS. 2A-1 through 2I-1, 2A-2 through 2I-2, 2A-3 through 2I-3, and 3A through 3F may be performed. According to some embodiments, after performing post-deposition anneal process 186 (not shown in fig. 4A, see fig. 3F), capping layer 184 (not shown in fig. 4A, see fig. 3F) is removed as shown in fig. 4A. After cap layer 184 is removed, the process shown in FIGS. 3G and 3H is performed to form semiconductor structure 100a including transistors Ta-1 and Ta-2. Since the gate dielectric layer 172 is covered by the additional gate dielectric layer 182, the gate dielectric layer 172 is not damaged by removing the cap layer 184. In addition, a space for forming the work function metal layer 190 and the gate filling layer 192 may be increased.

Fig. 5A-5G illustrate enlarged cross-sectional views of intermediate stages in the manufacture of a semiconductor structure 100b in accordance with some embodiments. The processes and materials used to form the semiconductor structure 100b may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here. For example, according to some embodiments, other elements in semiconductor structure 100b not shown in fig. 5G may be similar or identical to elements shown in fig. 2J-1, 2J-2, 2J-3, 2J-4, and 2J-5, previously described.

More specifically, according to some embodiments, channel structures 108'b-1, 108' b-2, 108'b3, and 108' b-4 are formed in regions 10b, 20b, 30b, and 40b, respectively, as shown in FIG. 5A. According to some embodiments, after forming channel structures 108'b-1, 108' b-2, 108'b3, and 108' b-4, interface layer 170, gate dielectric layer 172b, dipole layer 174b, and hard mask layer 176 are formed to cover channel structures 108'b-1, 108' b-2, 108'b3, and 108' b-4 in regions 10b, 20b, 30b, and 40b, as shown in FIG. 5A. Furthermore, according to some embodiments, gate dielectric layer 172b includes portions 172b-1, 172b-2, 172b-3, and 172b-4 that wrap around channel structures 108'b-1, 108' b-2, 108'b3, and 108' b-4, respectively.

Next, according to some embodiments, a photoresist layer 178b is formed in regions 10b and 20b, while exposing regions 30b and 40b. Thereafter, according to some embodiments, as shown in fig. 5B, portions of hard mask layer 176 and dipole layer 174B in regions 30B and 40B are removed.

According to some embodiments, after removing portions of dipole layer 174b in regions 30b and 40b, portions of photoresist layer 178b and hard mask layer 176 at regions 10b and 20b are also removed. Thereafter, a treatment process (e.g., treatment process 180 previously described) is performed to form modified portions 172'b-1 and 172b' -2 in regions 10b and 20b, while during the treatment process, portions 172b-3 and 172b-4 remain untreated since the remaining portions of dipole layer 174b are spaced apart from portions 172b-4 and 172 b-3. In some embodiments, the first metal element in dipole layer 174b is driven into portions 172b-1 and 172b-2 of gate dielectric layer 172 b. After performing the treatment process, according to some embodiments, as shown in fig. 5C, portions of dipole layer 174b at regions 10b and 20b are removed.

Next, according to some embodiments, another dipole layer 274b and another hard mask layer 276b are formed over the regions 10b, 20b, 30b, and 40b, as shown in fig. 5D. The dipole layer 274b is configured to modify the gate dielectric layer 272b. In some embodiments, the dipole layer 274b includes a second metal element, such as La, Y, al, sr, er, zn, sc, ti, nb. In some embodiments, the thickness of the dipole layer 274b is in the range from about 0.5nm to about 2.5 nm. In some embodiments, dipole layer 174b and dipole layer 274b include different metal elements.

Thereafter, according to some embodiments, a photoresist layer 278b is formed over regions 10b and 30b while regions 20b and 40b are exposed, and portions of hard mask layer 276b and dipole layer 274b at regions 20b, 40b are removed, as shown in fig. 5E. According to some embodiments, after removing portions of dipole layer 274b at regions 20b and 40b, portions of photoresist layer 278b and hard mask layer 276b are removed and a treatment process (e.g., treatment process 180 previously described) is performed to form modified portions 172"b-1 and 172' b-3 in regions 10b and 30b, as shown in FIG. 5F. In some embodiments, the second metallic element in the dipole layer 274b is driven into the portions 172'b-1 and 172b-3 to form modified portions 172"b-1 and 172' b-3. In some embodiments, the second metal element in dipole layer 274b is different from the first metal element in dipole layer 174 b.

Next, as shown in fig. 5G, the processes shown in fig. 3E-3H and previously described are performed to form the gate structure 168b of the semiconductor structure 100b, in accordance with some embodiments. In some embodiments, the gate structure 168b includes a portion 168b-1 wrapped around the channel structure 108'b-1, a portion 168b-2 wrapped around the channel structure 108' b-2, a portion 168b-3 wrapped around the channel structure 108'b-3, and a portion 168b-4 wrapped around the channel structure 108' b-4. Furthermore, according to some embodiments, all of the portions 168b-1, 168b-2, 168b-3, and 168b-4 include the same and a single work function metal layer 190.

In some embodiments, semiconductor structure 100b includes transistors Tb-1, tb-2, tb-3, and Tb-4 located in regions 10b, 20b, 30b, and 40b, respectively. As described above, according to some embodiments, the two treatment processes are performed, and thus the portion 172b-1 of the gate dielectric layer 172b in the region 10b is treated with the first metal element in the dipole layer 174b and the second metal element in the dipole layer 274 b. Furthermore, according to some embodiments, the portion 172b-2 of the gate dielectric layer 172b in the region 20b is treated with a first metal element in the dipole layer 174 b. According to some embodiments, the portion 172b-3 of the gate dielectric layer 172b in the region 30b is treated with the second metal element in the dipole layer 274b, and the portion 172a-4 of the gate dielectric layer 172 in the region 40b is not treated. That is, modified portion 172"b-1 includes a first metal element and a second metal element, modified portion 172'b-2 includes the first metal element but does not include the second metal element, modified portion 172' b-3 includes the second metal element but does not include the first metal element, and portion 172b-4 does not include the first metal element and the second metal element. In some embodiments, the threshold voltage of transistor Tb-1 is less than the threshold voltage of transistor Tb-2. In some embodiments, the threshold voltage of transistor Tb-3 is greater than the threshold voltage of transistor Tb-4.

The processes and materials used to form the channel structures 108'b-1, 108' b-2, 108'b3, and 108' b-4, the gate dielectric layer 172b, the dipole layers 174b and 274b, the photoresist layers 178b and 278b, the hard mask layer 276, and the gate structure 168b may be similar or identical to the processes and materials used to form the channel structures 108'-1 and 108' -2, the gate dielectric layer 172, the dipole layer 174, the photoresist layer 178, the hard mask layer 176, and the gate structure 168, and will not be repeated here. Furthermore, in some other embodiments, the cap layer 184 of the semiconductor structure 100b may be removed, similar to the semiconductor structure 100a previously described.

Fig. 6A-1 through 6J-1, 6A-2 through 6J-2, and 6A-3 through 6J-3 illustrate cross-sectional views of intermediate stages in the manufacture of a semiconductor structure 100c, in accordance with some embodiments. FIG. 6J-4 illustrates the block BK illustrated in FIG. 6J-2, according to some embodiments _6J An enlarged cross-sectional view of semiconductor structure 100 c. Fig. 6J-5 illustrate schematic top views of semiconductor structure 100c according to some embodiments. For clarity, fig. 6J-5 is simplified to better understand the inventive concepts of the present disclosure. More specifically, FIGS. 6A-1 through 6J-1, 6A-2 through 6J-2, and 6A-3 through 6J-3 illustrate the respective lines Y in FIG. 6J-5 according to some embodiments _SD6 -Y _SD6 ' i.e. in the Y direction, Y _MG6 -Y _MG6 ' i.e. in the Y direction, and X ₆ -X ₆ ' a cross-sectional view of an intermediate stage of fabricating the semiconductor structure 100c is shown (i.e., in the X-direction).

According to some embodiments, the semiconductor structure 100c may be similar to the semiconductor structure 100 described previously, except that a dielectric wall structure is formed. Some of the processes and materials used to form the semiconductor structure 100c may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here.

First, according to some embodiments, the processes shown in fig. 1A and 1B, previously described, are performed to form a semiconductor stack over the substrate 102, and the semiconductor stack is patterned with the mask structure 110 to form the fin structure 104c-1 in the first region 10c and the fin structure 104c-2 in the second region 20c, as shown in fig. 6A-1, 6A-2, and 6A-3.

After forming fin structures 104c-1 and 104c-2, a dielectric layer 620 is formed to cover fin structures 104c-1 and 104c-2, as shown in fig. 6B-1, 6B-2, and 6B-3, according to some embodiments. As shown in fig. 6B-1 and 6B-2, according to some embodiments, the lateral space between fin structures 104c-1 and 104c-2 is completely filled with dielectric layer 620. In some embodiments, dielectric layer 620 includes one or more dielectric materials, such as SiO ₂ 、SiN、SiCN、SiOC、SiOCN、HfO ₂ 、ZrO ₂ 、HfAlO _x 、HfSiO _x 、Al ₂ O ₃ Etc. The dielectric material may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or a combination thereof. In some embodiments, dielectric layer 620 includes a high-k shell layer and a low-k core layer formed over the high-k shell layer.

Next, according to some embodiments, as shown in fig. 6C-1, 6C-2, and 6C-3, an etching process is performed to form a dielectric wall structure 626, the dielectric wall structure 626 being interposed between the fin structures 104C-1 and 104C-2. In some embodiments, portions of dielectric layer 620 outside of the space between fin structures 104c-1 and 104c-2 are removed during the etching process. In some embodiments, the etching process is performed without using a mask structure. More specifically, since the space between fin structures 104c-1 and 104c-2 is completely filled with dielectric layer 620, the speed of dielectric layer 620 in removing the space may be much slower than elsewhere. That is, removing the dielectric layer 620 in other spaces is much easier and faster than removing the dielectric layer 620 in the space between the fin structures 104c-1 and 104c-2, because the top surface and sidewall surfaces of the dielectric layer 620 in other areas are mostly exposed. Thus, the dielectric layer 620 formed in the wider space may be completely removed, while the dielectric layer 620 formed in the space between the fin structures 104c-1 and 104c-2 is only partially removed during the etching process. In some embodiments, during the etching process, the mask structure 110 formed over the fin structures 104c-1 and 104c-2 is also partially etched.

According to some embodiments, after forming the dielectric wall structure 626, isolation structures 116 are formed around the fin structures 104c-1 and 104c-2, as shown in fig. 6D-1, 6D-2, and 6D-3. Thereafter, in accordance with some embodiments, as shown in FIGS. 6E-1, 6E-2, and 6E-3, a dummy gate structure 130 is formed across fin structures 104c-1 and 104c-2 and dielectric wall structure 626. According to some embodiments, after forming the dummy gate structure 130, a spacer layer 138 is formed to cover the top surfaces and sidewalls of the dummy gate structure 130 and the fin structures 104c-1 and 104c-2 and the top surfaces of the dielectric wall structures 626, as shown in fig. 6E-1, 6E-2, and 6E-3.

According to some embodiments, after forming spacer layer 138, an etching process is performed to form gate spacers 140 and fin spacers 142 with spacer layer 138, and source/drain recesses 144 are formed in fin structures 104c-1 and 104c-2, as shown in fig. 6F-1, 6F-2, and 6F-3. In some embodiments, the dielectric wall structure 626 at the source/drain regions is also slightly etched during the etching process used to form the source/drain recesses 144.

According to some embodiments, after forming the source/drain recesses 144, the inner spacers 148 are formed between the second semiconductor material layers 108, and source/drain structures 150c-1 and 150c-2 are formed in the source/drain recesses 144, as shown in fig. 6G-1, 6G-2, and 6G-3. The source/drain structures described herein may refer to the source or drain, individually or collectively, depending on the context.

In some embodiments, the source/drain structures 150c-1 and 150c-2 and the source/drain structures 150-1 and 150-2 have different shapes. More specifically, according to some embodiments, the source/drain structures 150c-1 and 150c-2 are sandwiched between one fin spacer 142 and a dielectric wall structure 626, wherein the dielectric wall structure 626 is higher than the fin spacer 142. Thus, according to some embodiments, the source/drain structures 150c-1 and 150c-2 have asymmetric shapes in the cross-sectional view in the Y-direction. According to some embodiments, the source/drain structure 150c-1 has a first side and a second side opposite the first side, and has substantially straight sidewalls at the second side. According to some embodiments, the substantially straight sidewalls of the source/drain structures 150c-1 are in direct contact with the first sidewalls of the dielectric wall structures 626. Meanwhile, according to some embodiments, the sidewalls of the source/drain structures 150c-1 on the first side extend laterally outside the sidewalls of the fin structures 104c-1 and further outside the sidewalls of the fin spacers 142.

Similarly, the source/drain structure 150c-2 has a first side and a second side opposite the first side. In some embodiments, the substantially straight sidewalls of the source/drain structures 150c-2 on the first side are in direct contact with the second sidewalls of the dielectric wall structures 626, according to some embodiments. Meanwhile, according to some embodiments, the sidewalls of the source/drain structures 150c-2 on the second side extend laterally outside the sidewalls of the fin structures 104c-2 and further outside the sidewalls of the fin spacers 142. In some embodiments, the top surface of dielectric wall structure 626 is higher than the topmost of source/drain structures 150c-1 and 150 c-2.

In some embodiments, the source/drain structures 150c-1 and 150c-2 are made of different types of source/drain materials. In some embodiments, source/drain structure 150c-1 is made of an n-type epitaxial material, and source/drain structure 150c-2 is made of a p-type epitaxial material.

According to some embodiments, after forming the source/drain structures 150c-1 and 150c-2, a Contact Etch Stop Layer (CESL) 160 is conformally formed to cover the source/drain structures 150c-1, 150c-2, and an interlayer dielectric (ILD) layer 162 is formed over the contact etch stop layer 160, as shown in FIGS. 6H-1, 6H-2, and 6H-3. In some embodiments, the contact etch stop layer 160 is in direct contact with the sidewalls of the dielectric wall structure 626. According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process such as a CMP or an etchback process is performed until the dummy gate electrode layer 134 is exposed.

Next, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form gate trenches 166c-1 and 166c-2, as shown in fig. 6I-1, 6I-2, and 6I-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'c-1 and 108' c-2 with the second semiconductor material layer 108 of the fin structures 104c-1 and 104 c-2. Although not explicitly shown in the figures, the channel structures 108'c-1 and 108' c-2 and the base fin structure 104B may have rounded corners.

As shown in fig. 6I-2, according to some embodiments, the top and bottom surfaces of each of the channel structures 108'c-1 and 108' c-2 are exposed by the gate trenches 166c-1 and 166c-2, but not all lateral sidewalls of the channel structures 108'c-1 and 108' c-2 are exposed by the gate trenches 166c-1 and 166 c-2. That is, according to some embodiments, one sidewall of each of the channel structures 108'c-1 and 108' c-2 is attached to the dielectric wall structure 626 and is not exposed by the gate trenches 166c-1 and 166c-2, and the other three lateral sidewalls in each of the channel structures 108'c-1 and 108' c-2 are exposed by the gate trenches 166c-1 and 166 c-2. According to some embodiments, in a cross-sectional view along the Y-direction, only one sidewall of each of the channel structures 108'c-1 and 108' c-2 is exposed by the gate trenches 166c-1 and 166 c-2.

Furthermore, according to some embodiments, the portion of the first sidewall of the dielectric wall structure 626 that is not attached to the channel structure 108'c-1 is exposed by the gate trench 166c-1, and the portion of the second sidewall of the dielectric wall structure 626 that is not attached to the channel structure 108' c-2 is exposed by the gate trench 166 c-2.

Next, gate structures 168c are formed in gate trenches 166c-1 and 166c-2, as shown in fig. 6J-1, 6J-2, 6J-3, 6J-4, and 6J-5, according to some embodiments. More specifically, the processes shown in fig. 3A-3H may be performed to form the gate structure 168c. In some embodiments, interface layer 170c is formed over channel structures 108'c-1 and 108' c-2 and the exposed portions of base fin structure 104B. Thereafter, according to some embodiments, a gate dielectric layer 172c is formed over interface layer 170c and over dielectric wall structure 262.

Furthermore, according to some embodiments, gate dielectric layer 172c includes a modified portion 172' c-1 surrounding channel structure 108' c-1 in first region 10c and a portion 172c-2 surrounding channel structure 108' c-2 in second region 20. In some embodiments, modified portion 172' c-1 of gate dielectric layer 172c covers and directly contacts the first side walls and top surfaces of dielectric wall structure 626. On the other hand, according to some embodiments, portion 172c-2 of gate dielectric layer 172c partially covers and directly contacts the second sidewalls and top surface of dielectric wall structure 626. As shown in fig. 6J-4, according to some embodiments, the boundary between modified portion 172' c-1 and portion 172c-2 is located above the top surface of dielectric wall structure 626. The modified portion 172' c-1 treated with the metal element may be formed by performing the processes shown in fig. 3A to 3D described previously, and will not be repeated here.

After forming the modified portion 172' c-1, the process illustrated in fig. 3E-3H may be performed to form the gate structure 168c. That is, according to some embodiments, the gate dielectric layer 182c, the cap layer 184c, the work function metal layer 190c, and the gate fill layer 192c are formed. Furthermore, according to some embodiments, each of the gate dielectric layer 182c, cap layer 184c, work function metal layer 190c, and gate fill layer 192c extends continuously from channel structure 108'c-1 to channel structure 108' c-2 and through the top surface of dielectric wall structure 626. In some embodiments, the semiconductor structure 100c includes a transistor Tc-1 and a transistor Tc-2, the transistor Tc-1 including a portion 168c-1 of the gate structure 168c formed around the channel structure 108'c-1, and the transistor Tc-2 including a portion 168c-2 of the gate structure 168c formed around the channel structure 108' c-2.

As shown in fig. 6J-2, in accordance with some embodiments, the dielectric wall structure 626 is interposed between the channel structures 108'c-1 and 180' c-2. Further, according to some embodiments, as shown in fig. 6J-5, the dielectric wall structure 626 is substantially parallel to the fin structures 104c-1 and 104c-2 and is longitudinally oriented along the X-direction.

The processes and materials used to form fin structures 104c-1 and 104c-2, source/drain structures 150c-1 and 150c-2, gate trenches 166c-1 and 166c-2, channel structures 108'c-1 and 108' c-2, gate structure 168c, interface layer 170c, gate dielectric layer 172c, gate dielectric layer 182c, cap layer 184c, work function metal layer 190c, and gate fill layer 192c may be similar or identical to those previously described for forming fin structures 104-1 and 104-2, source/drain structures 150-1 and 150-2, gate trenches 166-1 and 166-2, channel structures 108'-1 and 108' -2, gate structure 168, interface layer 170, gate dielectric layer 172, gate dielectric layer 182, cap layer 184, work function metal layer 190, and gate fill layer 192, and will not be repeated here.

Furthermore, in some other embodiments, the cap layer 184c of the semiconductor structure 100c may be removed, similar to the semiconductor structure 100a previously described. Further, according to some embodiments, the gate dielectric layer 172 may be processed according to the processes shown in fig. 5A-5G. For example, portion 172c-1 of gate dielectric layer 172 may be modified twice, similar to or the same as portion 172b "-1 of semiconductor structure 100 b. For example, portion 172c-2 of gate dielectric layer 172 may also be similar or identical to portion 172"b-1 or 172' b-3 of semiconductor structure 100 b.

Fig. 6J ' -1 and 6J ' -2 illustrate cross-sectional views of semiconductor structures 100c ' according to some embodiments. According to some embodiments, the semiconductor structure 100c ' may be similar to the semiconductor structure 100c described previously, except that the cap layer 184 between the channel structures 108' c-1 and 108' c-2 is incorporated. That is, according to some embodiments, the work function metal layer 190c does not extend between the channel structures 108'c-1 and 108' c-2. In some embodiments, the thickness of the cap layer 184c in the semiconductor structure 100c' is greater than about 3nm. The processes and materials used to form the semiconductor structure 100c' may be similar or identical to those previously described for forming the semiconductor structure 100c and are not repeated here.

Fig. 7A-1 through 7Q-1, fig. 7A-2 through 7Q-2, and fig. 7A-3 through 7Q-3 illustrate cross-sectional views of intermediate stages in the manufacture of a semiconductor structure 100d in accordance with some embodiments. FIG. 7Q-4 illustrates the block BK illustrated in FIG. 7Q-3, according to some embodiments _7Q An enlarged cross-sectional view of semiconductor structure 100 d. Fig. 7Q-5 showsA schematic top view of a semiconductor structure 100d according to some embodiments. Fig. 7Q-5 are simplified for clarity to better understand the inventive concepts of the present disclosure. More specifically, FIGS. 7A-1 through 7Q-1, 7A-2 through 7Q-2, and 7A-3 through 7Q-3 illustrate the respective lines Y in FIG. 7Q-5 according to some embodiments _SD7 -Y _SD7 ' i.e. in the Y direction, Y _MG7 -Y _MG7 ' i.e. in the Y direction, and X ₇ -X ₇ ' a cross-sectional view of an intermediate stage of fabricating the semiconductor structure 100d is shown (i.e., in the X-direction). Some of the processes and materials used to form the semiconductor structure 100d may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here.

First, according to some embodiments, a first semiconductor stack and a second semiconductor stack are formed in the first region 10d and the second region 20d over the substrate 102, and the first semiconductor stack, the second semiconductor stack, and the substrate 102 are patterned with a mask structure 110d to form a fin structure 104d, as shown in fig. 7A-1, 7A-2, and 7A-3. As shown in fig. 7A-1, the fin structure 104d includes a first portion 104d-1 including a first semiconductor stack formed in the first region 10d, a second portion 104d-2 including a second semiconductor stack formed in the second region 20d, and a base fin structure 104Bd, in accordance with some embodiments. Furthermore, according to some embodiments, the first portion 104d-1 of the fin structure 104d vertically overlaps the second portion 104d-2 of the fin structure 104.

In some embodiments, the first semiconductor stack and the second semiconductor stack each include alternating stacks of first semiconductor material layers 106 and second semiconductor material layers 108. Further, according to some embodiments, an intermediate layer 109 is formed over the first semiconductor stack, and a second semiconductor stack is formed over the intermediate layer 109. In some embodiments, the intermediate layer 109 is made of the same material as the first semiconductor material layer 106. In some embodiments, the intermediate layer 109 is made of SiGe.

After forming fin structure 104d, mask structure 110d is removed and isolation structures 116 are formed around fin structure 104d, as shown in fig. 7B-1, 7B-2, and 7B-3, according to some embodiments. Thereafter, in accordance with some embodiments, a dummy gate structure 130 is formed across the fin structure 104d, as shown in fig. 7C-1, 7C-2, and 7C-3. According to some embodiments, after forming the dummy gate structure 130, a spacer layer is formed and an etching process is performed to form the gate spacers 140 and the source/drain recesses 144D, as shown in fig. 7D-1, 7D-2, and 7D-3.

According to some embodiments, after forming the source/drain recesses 144d, the first semiconductor material layer 106 and the intermediate layer 109 in the first and second regions 10d and 20d are laterally etched to form recesses, as shown in fig. 7E-1, 7E-2, and 7E-3, and an inner spacer 148d is formed in the recess between the second semiconductor material layer 108 in the first and second regions 10d and 20d, and an intermediate spacer 149 is formed in the recess between the first and second regions 10d and 20 d. In some embodiments, intermediate spacer 149 and inner spacer 148d are made of the same material.

According to some embodiments, after forming the inner spacer 148d and the intermediate spacer 149, a source/drain structure 150d-1 is formed in the bottom region of the source/drain recess 144d, as shown in fig. 7E-1, 7E-2, and 7E-3. As shown in fig. 7E-3, the source/drain structure 150d-1 is attached to an opposite side of the second semiconductor material layer 108 in the first portion 104d-1 of the fin structure 104d in the first region 10d, according to some embodiments.

Next, a Contact Etch Stop Layer (CESL) 160d-1 and an interlayer dielectric (ILD) layer 162d-1 are formed over the source/drain structure 150d-1 in the middle portion of the source/drain recess 144d, as shown in fig. 7F-1, 7F-2, and 7F-3, according to some embodiments. In some embodiments, contact etch stop layer 160d-1 covers and is in direct contact with the sidewalls of intermediate spacer 149. In some embodiments, contact etch stop layer 160d-1 and interlayer dielectric layer 162-1 are laterally sandwiched between intermediate spacers 149.

According to some embodiments, after forming the contact etch stop layer 160d-1 and the interlayer dielectric layer 162d-1, a source/drain structure 150d-2 is formed in an upper portion of the source/drain recess 144d, as shown in fig. 7F-1, 7F-2, and 7F-3. As shown in fig. 7F-3, the source/drain structures 150d-2 are attached to opposite sides of the second semiconductor material layer 108 in the second portion 104d-2 of the fin structure 104d in the second region 20d, according to some embodiments. In some embodiments, source/drain structures 150d-1 and 150d-2 are different types of source/drain structures. In some embodiments, the source/drain structure 150d-1 is made of an n-type epitaxial material and the source/drain structure 150d-2 is made of a p-type epitaxial material.

Next, according to some embodiments, a contact etch stop layer 160d-2 and an interlayer dielectric layer 162d-2 are formed over the source/drain structure 150d-2 in the upper portion of the source/drain recess 144d, and a polishing process is performed until the dummy gate structure 130 is exposed, as shown in fig. 7G-1, 7G-2, and 7G-3.

Next, according to some embodiments, the dummy gate structure 130, the first semiconductor material layer 106 in the first region 10d and the second region 20d, and the intermediate layer 109 are removed to form a gate trench 166d including a first portion 166d-1 and a second portion 166d-2, as shown in fig. 7H-1, 7H-2, and 7H-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'd-1 and 108'd-2 with the second semiconductor material layer 108 of the first portion 104d-1 and the second portion 104d-2 of the fin structure 104 d. Although not explicitly shown in the figures, the channel structures 108'd-1 and 108'd-2 and the base fin structure 104Bd may have rounded corners.

As shown in FIGS. 7H-2 and 7H-3, the channel structure 108'd-2 vertically overlaps and aligns with the channel structure 108'd-1, according to some embodiments. In some embodiments, the vertical distance between the bottommost structure of channel structures 108'd-2 and the topmost structure of channel structures 108'd-1 is greater than the vertical distance between adjacent channel structures 108'd-1, and is also greater than the vertical distance between adjacent channel structures 108'd-2.

After forming the channel structures 108'd-1 and 108' -2, an interface layer 170d (including 170d-1 and 170 d-2), a gate dielectric layer 172d (including 172d-1 and 172 d-2), a dipole layer 174d (including 174d-1 and 174 d-2), and a hard mask layer 176d (including 176d-1 and 176 d-2) are formed, as shown in fig. 7I-1, 7I-2, and 7I-3, according to some embodiments. More specifically, according to some embodiments, interface layer 170d-1, gate dielectric layer 172d-1, dipole layer 174d-1, and hard mask layer 176d-1 are formed to surround channel structure 108'd-1 and cover base fin structure 104Bd, and hard mask layer 176d-2 is formed to surround channel structure 108'd-2.

In some embodiments, interface layers 170d-1 and 170d-2 are made of the same material using the same deposition process. In some embodiments, gate dielectric layers 172d-1 and 172d-2 are made of the same material using the same deposition process. In some embodiments, dipole layers 174d-1 and 174d-2 are made of the same material using the same deposition process.

Thereafter, according to some embodiments, as shown in fig. 7J-1, 7J-2, and 7J-3, a photoresist layer 178d is formed in the first region 10d to cover the hard mask layer 176d-1, and the hard mask layer 176d-2 and the dipole layer 174d-2 are removed. After removing the dipole layer 174d-2, the photoresist layer 178d and the hard mask layer 176d-1 in the first region 10d are also removed, and a treatment process 180 is performed to modify the gate dielectric layer 172d-1 in the first region 10d, as shown in fig. 7K-1, 7K-2, and 7K-3. More specifically, according to some embodiments, the metal elements in dipole layer 174d-1 are driven into gate dielectric layer 172d-1 to form modified gate dielectric layer 172'd-1.

According to some embodiments, after performing the treatment process 180, the dipole layer 174d-1 is removed, as shown in FIG. 7L-1, FIG. 7L-2, and FIG. 7L-3. Next, according to some embodiments, an additional hard mask layer 176d (including 276d-1 and 276 d-2) is formed over the modified gate dielectric layer 172'd-1 and the gate dielectric layer 172d-2, as shown in fig. 7M-1, 7M-2, and 7M-3. Thereafter, according to some embodiments, as shown in FIGS. 7N-1, 7N-2, and 7N-3, an additional photoresist layer 278d is formed in the first region 10d to cover the hard mask layer 276d-1 in the first region 10d, and the hard mask layer 276d-2 exposed by the photoresist layer 278d is removed.

According to some embodiments, after the hard mask layer 276d-2 is removed, a dipole layer 274d-1 is formed around the channel structure 108'd-1 in the first region 10d and a dipole layer 274d-2 is formed around the channel structure 108'd-1 in the second region 20d, as shown in FIGS. 7O-1, 7O-2, and 7O-3. In some embodiments, the dipole layers 274d-1 and 274d-2 are made of the same material using the same deposition process.

As shown in FIG. 7O-2, according to some embodiments, the dipole layer 274d-1 is separated from the gate dielectric layer 172'd-1 surrounding the channel structure 108'd-1 by the hard mask layer 276d-1, and the dipole layer 274d-2 is in direct contact with the gate dielectric layer 172d-2 surrounding the channel structure 108'd' -2.

According to some embodiments, after forming dipole layers 274d-1 and 274d-2, treatment process 180 is performed to modify gate dielectric layer 172d-2 in second region 20d to form modified gate dielectric layer 172'd-2, as shown in FIGS. 7O-1, 7O-2, and 7O-3. As previously described, during the process 180, the dipole layer 274d-1 is spaced apart from the modified gate dielectric layer 172'd-1. Thus, during the processing 180, the second metal element in the dipole layer 274d-2 is driven into the gate dielectric layer 172d-2 to form a modified gate dielectric layer 172'd-2, according to some embodiments. On the other hand, according to some embodiments, the second metal element in the dipole layer 274d-1 is not driven into the gate dielectric layer 172'd-1. In some embodiments, the second metal element in the dipole layer 274d-2 is driven into the hard mask layer 276d-1 during the processing process 180 shown in FIG. 7O-2.

Next, according to some embodiments, as shown in fig. 7P-1, 7P-2, and 7P-3, the dipole layers 274d-1 and 274d-2 and the hard mask layer 276d-1 are removed. Thereafter, according to some embodiments, the process shown in fig. 3E-3H is performed to form gate structure 168d, as shown in fig. 7Q-1, 7Q-2, 7Q-3, and 7Q-4. More specifically, according to some embodiments, a gate dielectric layer 182 (including 182-1 and 182-2), a cap layer 184 (including 184d-1 and 184 d-2), a work function metal layer 190d (including 190d-1 and 190 d-2), and a gate fill layer 192d are formed in the gate trenches 166d-1 and 166 d-2. In some embodiments, gate dielectric layers 182-1 and 182-2 are made of the same material using the same deposition process. In some embodiments, cap layers 184d-1 and 184d-2 are made of the same material using the same deposition process. In some embodiments, work function metal layers 190d-1 and 190d-2 are made of the same material using the same deposition process.

As shown in fig. 7Q-2, according to some embodiments, the semiconductor structure 100d includes a transistor Td-1 in the first region 10d and a transistor Td-2 in the second region 20 d. Further, according to some embodiments, transistor Td-2 vertically overlaps with transistor Td-1. In some embodiments, transistor Td-1 includes channel structure 108'd-1, source/drain structures 150d-1 attached to opposite sides of channel structure 108'd-1, and a portion 168d-1 of gate structure 168d wrapped around channel structure 108'd-1. Similarly, according to some embodiments, transistor Td-2 includes channel structure 108'd-2, source/drain structure 150d-2 attached to opposite sides of channel structure 108'd-2, and portion 168d-2 of gate structure 168d wrapped around channel structure 108'd-2.

In some embodiments, even though the work function metal layers 190d-1 and 190d-2 are made of the same material having the same thickness, the threshold voltage of the transistor Td-1 is different from the threshold voltage of the transistor Td-2. In some embodiments, the thickness of the work function metal layer 190d-1 over the topmost structure of the channel structure 108'd-1 (e.g., the distance between the top surface of the gate dielectric layer 182d-1 and the surface of the gate fill layer 192d, which is in contact with the work function metal layer 190d-1 over the topmost structure of the channel structure 108'd-1 in the direction Z) is substantially equal to the thickness of the work function metal layer 190d-2 over the topmost structure of the channel structure 108'd-2 (e.g., the distance between the top surface of the gate dielectric layer 182d-2 and the surface of the gate fill layer 192d, which is in contact with the work function metal layer 190d-2 over the topmost structure of the channel structure 108'd-1 in the direction Z). In some embodiments, the gate fill layer 192d is continuously formed around the channel structures 108'd-1 and 108'd-2, and a portion of the gate fill layer is vertically sandwiched between the topmost structure of the channel structure 108'd-1 and the bottommost structure of the channel structure 108'd-2.

In some embodiments, the modified gate dielectric layer 172'd-1 is doped with a first metal element and is free of a second metal element, while the modified gate dielectric layer 172'd-2 is doped with a second metal element and is free of the first metal element. Further, according to some embodiments, modified gate dielectric layer 172'd-2 vertically overlaps modified gate dielectric layer 172'd-1.

In some embodiments, modified gate dielectric layer 172'd-1 covers and is in direct contact with a lower portion of intermediate spacer layer 149 and modified gate dielectric layer 172'd-2 covers and is in direct contact with an upper portion of intermediate spacer 149, as shown in fig. 7Q-4. In some embodiments, portions of intermediate spacer 149 are sandwiched between contact etch stop layer 160d-1 and modified gate dielectric layer 172'd-1. In some embodiments, portions of intermediate spacer 149 are sandwiched between contact etch stop layer 160d-1 and modified gate dielectric layer 172'd-2. In some embodiments, portions of the intermediate spacer 149 are sandwiched between the source/drain structure 150d-2 and the modified gate dielectric layer 172'd-2.

For forming mask structure 110d, internal spacers 148d, source/drain structures 150d-1 and 150d-2, contact etch stop layers 160d-1 and 160d-2, interlayer dielectric layers 162d-1 and 162d-2, gate trench 166d, channel structures 108'd-1 and 108'd-2, interface layers 170d-1 and 170d-2, gate dielectric layers 172d-1 and 172d-2, dipole layers 174d-1, 174d-2, 274d-1 and 274d-2, hard mask layers 176d-1, 176d-2, 276d-1 and 276d-2, photoresist layers 178d and 278d, gate dielectric layers 182-1 and 182-2, cap layer 184d including cap layers 184d-1 and 184d-2 the process and materials of the work function metal layers 190d-1 and 190d-2 and the gate fill layer 192d may be similar or identical to the process and materials previously described for forming the mask structure 110, the inner spacer 148, the source/drain structures 150-1 and 150-2, the contact etch stop layer 160, the interlayer dielectric layer 162, the gate trench 166, the channel structures 108'-1 and 108' -2, the interface layer 170, the gate dielectric layer 172, the dipole layer 174, the hard mask layer 176, the photoresist layer 178, the gate dielectric layer 182, the cap layer 184, the work function metal layer 190 and the gate fill layer 192, and will not be repeated here.

Furthermore, in some other embodiments, the cap layers 184d-1 and 184d-2 of the semiconductor structure 100d may be removed, similar to the semiconductor structure 100a previously described. Furthermore, according to some embodiments, the gate dielectric layers 172d-1 and 172d-2 may be processed according to the processes shown in fig. 5A-5G. For example, gate dielectric layers 172d-1 and/or 172d-2 may be modified twice, similar to or identical to portions 172b "-1 of semiconductor structure 100 b.

Fig. 7Q ' -1 and 7Q ' -2 illustrate cross-sectional views of semiconductor structure 100d ' according to some embodiments. According to some embodiments, the semiconductor structure 100d ' may be similar to the previously described semiconductor structure 100d, except that the cap layer 184d between the channel structures 108'd-1 and 108'd-2 is incorporated. That is, according to some embodiments, the work function metal layer 190d does not extend between the channel structures 108'd-1 and 108'd-2. In some embodiments, the thickness of the cap layer 184d in the semiconductor structure 100d' is greater than about 3nm. The processes and materials used to form the semiconductor structure 100d may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here.

Fig. 8-1, 8-2, and 8-3 illustrate cross-sectional views of a semiconductor structure 100e according to some embodiments. 8-4 illustrate the block BK illustrated in FIGS. 8-3 according to some embodiments ₈ An enlarged cross-sectional view of semiconductor structure 100 e. According to some embodiments, the semiconductor structure 100e may be similar to the previously described semiconductor structure 100d, except that a gate fill layer is not formed. Some of the processes and materials used to form the semiconductor structure 100e may be similar or identical to those previously described for forming the semiconductor structure 100d and are not repeated here.

More specifically, the processes shown in fig. 7A-1 to 7P-1, 7A-2 to 7P-2, 7A-3 to 7P-3, and 3E to 3F may be performed. After formation of cap layers 184d-1 and 184d-2, gate trenches (e.g., gate trenches 166d-1 and 166 d-2) are completely filled with work function metal layer 190e to form semiconductor structure 100e, as shown in fig. 8-1, 8-2, and 8-3, according to some embodiments.

As shown in fig. 8-2, semiconductor structure 100e includes a transistor Te-1 and a transistor Te-2, according to some embodiments. Furthermore, according to some embodiments, transistor Te-2 vertically overlaps with transistor Te-1. In some embodiments, the transistor Te-1 includes a channel structure 108'd-1, source/drain structures 150d-1 attached to opposite sides of the channel structure 108'd-1, and a portion 168e-1 of the gate structure 168e surrounding the channel structure 108'd-1. Similarly, according to some embodiments, the transistor Te-2 includes a channel structure 108'd-2, source/drain structures 150d-2 attached to opposite sides of the channel structure 108'd-2, and a portion 168e-2 of the gate structure 168e surrounding the channel structure 108'd-2.

In some embodiments, the threshold voltage of transistor Te-1 is different than the threshold voltage of transistor Te-2. In some embodiments, the work function metal layer 190e is continuously formed around the channel structures 108'd-1 and 108'd-2, and a portion of the work function metal layer 190e is vertically sandwiched between the topmost structure of the channel structure 108'd-1 and the bottommost structure of the channel structure 108'd-2.

The process and materials used to form the work function metal layer 190e may be similar or identical to those previously described for forming the work function metal layer 190 and are not repeated here. Furthermore, in some other embodiments, the cap layers 184d-1 and 184d-2 of the semiconductor structure 100d may be removed, similar to the semiconductor structure 100a previously described.

Fig. 9-1, 9-2, and 9-3 illustrate cross-sectional views of a semiconductor structure 100f according to some embodiments. Fig. 9-4 illustrate schematic top views of semiconductor structures 100f according to some embodiments. Fig. 9-4 are simplified for clarity to better understand the inventive concepts of the present disclosure. More specifically, FIGS. 9-1, 9-2, and 9-3 illustrate a view along line Y in FIGS. 9-4, respectively, according to some embodiments _SD9 -Y _SD9 ' i.e. in the Y direction, Y _MG9 -Y _MG9 ' i.e. in the Y direction, and X ₉ -X ₉ ' a cross-sectional view of an intermediate stage of fabricating the semiconductor structure 100f is shown (i.e., in the X-direction).

According to some embodiments, the semiconductor structure 100f may be similar to the previously described semiconductor structure 100, except that the process is applied to a FinFET structure. Some of the processes and materials used to form the semiconductor structure 100f may be similar or identical to those previously described for forming the semiconductor structure 100 and are not repeated here.

More specifically, fin structures 104f-1 and 104f-2 are formed by patterning substrate 102. The fin structure may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning or multiple patterning processes) may be used to pattern the fin structure. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fin structure.

According to some embodiments, the processes shown in fig. 2A-1 through 2H-1, fig. 2A-2 through 2H-2, and fig. 2A-3 through 2H-3 may be performed after the fin structures 104f-1 and 104f-2 are formed. Next, the dummy gate structure (e.g., dummy gate structure 130) is removed and the process shown in fig. 3A-3H is performed to form gate structure 168f across fin structures 104f-1 and 104f-2, as shown in fig. 9-2 and 9-3.

As shown in fig. 9-2, semiconductor structure 100f includes a transistor Tf-1 and a transistor Tf-2, according to some embodiments. In some embodiments, transistor Tf-1 includes fin structure 104f-1, a portion 168f-1 of gate structure 168f formed across fin structure 104a-1, and source/drain structures 150-1 formed adjacent opposite sides of portion 168f-1 of gate structure 168 f-1. Similarly, according to some embodiments, the transistor Tf-2 includes a fin structure 104f-2, a portion 168f-2 of a gate structure 168f formed across the fin structure 104f-2, and source/drain structures 150-2 formed adjacent opposite sides of the portion 168f-2 of the gate structure 168 f. In some embodiments, gate structure 168f includes interface layer 170f, gate dielectric layer 172f having portions 172f-1 and 172f-2, gate dielectric layer 182f, cap layer 184f, work function metal layer 190f, and gate fill layer 192f. In some embodiments, portion 172' f-1 includes a first metal element, while portion 172f-2 does not include a first metal element, such that the threshold voltage of transistor Tf-1 is different than the threshold voltage of transistor Tf-2.

The processes and materials used to form interface layer 170f, gate dielectric layer 172f, gate dielectric layer 182f, cap layer 184f, work function metal layer 190f, and gate fill layer 192f may be similar or identical to those previously described for forming interface layer 170, gate dielectric layer 172, gate dielectric layer 182, cap layer 184, work function metal layer 190, and gate fill layer 192, and are not repeated here.

Furthermore, in some other embodiments, the cap layer 184f of the semiconductor structure 100f may be removed, similar to the semiconductor structure 100a previously described. Further, according to some embodiments, the gate dielectric layer 172f may be processed according to the processes shown in fig. 5A-5G.

In general, multiple work function metal layers may be formed in a gate structure so that the resulting transistors may have different threshold voltages. For example, in a gate structure, more than one work function metal layer may be formed. However, as the size of semiconductor devices continues to shrink, the space for forming the gate structure may be mainly occupied by the work function metal layer. That is, there may not be enough space for forming the gate filling layer.

Furthermore, during the patterning process for forming different work function metal layers in different regions, multiple etching processes may need to be performed, and it may be challenging to completely remove the metal layers without damaging the elements exposed during the etching process. On the other hand, different types of work function metal layers may be formed in a single metal gate structure. For example, a p-type transistor may include n-type and p-type work function metal layers. Therefore, a threshold voltage difference between the p-type transistor and the n-type transistor may decrease, and reliability may also decrease. Furthermore, the metal element in one type of work function metal layer may diffuse into another type of work function metal layer. That is, at the interface between the two types of work function metal layers, the metal in the p-type work function metal layer may diffuse into the n-type work function metal layer, and the metal in the n-type work function metal layer may diffuse into the p-type work function metal layer, and thus the threshold voltage may not be as designed, and the performance of the resulting transistor may be destroyed.

Thus, in the above-described embodiments, at least a portion of the gate dielectric layer (e.g., gate dielectric layer 172) is doped with a metal element in the dipole layer (e.g., dipole layer 174), so that the threshold voltage of the transistor can be adjusted. That is, although only a single type of work function metal layer (e.g., work function metal layer 190) is used, the transistor may still have a different threshold voltage according to some embodiments. In addition, there may still be sufficient space for forming a gate fill layer (e.g., gate fill layer 192) in the gate trench. Thus, the reliability and performance of the resulting transistor can be improved.

In some embodiments, the gate dielectric layer at the n-type transistor (e.g., transistor T-1) is treated with a metal element, so that both the n-type transistor and the adjacent p-type transistor (e.g., transistor T-2) include a p-type work function metal layer, but do not include an n-type work function metal layer. Since the n-type work function metal layer is not formed, the threshold voltage of the p-type transistor will not be affected by the n-type work function metal layer that will be formed generally, and thus may have a lower threshold voltage. In addition, the gate dielectric layer on which the n-type work function metal layer (e.g., al-containing layer) is not formed may have improved reliability.

Furthermore, there is no interface between the two types of work function metal layers. At the same time, the metal element is doped in the gate dielectric layer (e.g., oxide layer), and diffusion of the metal element in the oxide layer may be relatively slow. Therefore, a boundary effect due to diffusion of metal elements will not occur between the different types of work function metal layers. Thus, performance can be improved.

Further, according to some embodiments, a cap layer (e.g., cap layer 184) is formed over the gate dielectric layer and an anneal process (e.g., post-deposition anneal process 186) is performed to densify the gate dielectric layer (e.g., gate dielectric layers 172 and 182), such that the quality of the gate dielectric layer may be improved. In addition, the cap layer may remain in the gate structure, so that the gate dielectric layer is not damaged by removing the cap layer.

It should be understood that the elements shown in semiconductor structures 100, 100a, 100b, 100c, 100d, 100e, and 100f may be combined and/or interchanged. For example, the semiconductor structure may include at least one of the modified portions 172"b-1, 172'b-2, 172' b3, and 172 b-4. Further, it should be noted that the same elements in fig. 1A through 9-3 may be denoted by the same reference numerals, and may include the same or similar materials, and may be formed by the same or similar processes; therefore, these redundant details are omitted for the sake of brevity. Furthermore, although fig. 1A to 9-3 are described with respect to the method, it should be understood that the structures disclosed in fig. 1A to 9-3 are not limited to the method, but may be used alone as a structure independent of the method. Similarly, the methods shown in fig. 1A-9-3 are not limited to the disclosed structures, but may exist independently of the structures. Furthermore, according to some embodiments, the channel structures (e.g., nanostructures) described above may include nanowires, nanoplatelets, or other applicable nanostructures.

Moreover, while the disclosed methods are illustrated and described hereinafter as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events may be changed in some other embodiments. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described above. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments of the description above. Furthermore, one or more of the acts described above may be performed as one or more separate acts and/or phases.

Furthermore, the terms "approximate," "substantially," and "about" as used above explain minor variations and may vary in different techniques and are within the scope of deviation as understood by those skilled in the art. For example, when used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely, and also to instances where the event or circumstance occurs approximately.

Embodiments for forming a semiconductor structure may be provided. The semiconductor structure may include forming a gate dielectric layer in the first region and the second region, and the gate dielectric layer modified with the first metal element in the first region but not in the second region. Thereafter, a capping layer may be formed on the modified gate dielectric layer to densify the gate dielectric layer, so that the quality of the gate dielectric layer may be improved. Next, a work function metal layer may be formed in the first region and the second region. Since the gate dielectric layer in the first region is doped with the first metal element, threshold voltages of the first transistor and the second transistor may be different.

In some embodiments, a method for fabricating a semiconductor structure is provided. The method for manufacturing the semiconductor structure comprises the following steps: a first channel structure is formed in the first region and a second channel structure is formed in the second region, and a first type of source/drain structure attached to opposite sides of the first channel structure and a second type of source/drain structure attached to opposite sides of the second channel structure are formed. The method for fabricating the semiconductor structure further comprises: a first gate dielectric layer is formed having a first portion overlying the first channel structure and a second portion overlying the second channel structure, and a first metal element is driven into the first portion of the first gate dielectric layer. The method for fabricating the semiconductor structure further comprises: after driving the first metal element into the first portion of the first gate dielectric layer, a capping layer is formed over the first portion and the second portion of the first gate dielectric layer, and an annealing process is performed on the first gate dielectric layer under the capping layer. The method of fabricating a semiconductor structure further includes: a work function metal layer is formed that extends continuously from the first region to the second region and covers the first channel structure and the second channel structure.

In some embodiments, the method for fabricating a semiconductor structure further comprises: after driving the first metal element into the first portion of the first gate dielectric layer, a second gate dielectric layer is formed over the first portion and the second portion of the first gate dielectric layer.

In some embodiments, the second gate dielectric layer is thinner than the first gate dielectric layer.

In some embodiments, the second gate dielectric layer and the first gate dielectric layer are made of the same material.

In some embodiments, the first channel structure and the second channel structure are suspended above the substrate and are spaced apart from each other.

In some embodiments, the method for fabricating a semiconductor structure further comprises: a second metal element is driven into a second portion of the first gate dielectric layer in the second region, wherein the first metal element is different from the second metal element.

In some embodiments, the first region vertically overlaps the second region.

In some embodiments, the work function metal layer is made of p-type work function metal.

In some embodiments, a method for fabricating a semiconductor structure is provided. The method for manufacturing the semiconductor structure comprises the following steps: forming a first type of source/drain structure and a second type of source/drain structure over the substrate, and forming a first channel structure suspended vertically over the substrate and sandwiched between the first type of source/drain structures. The method for fabricating the semiconductor structure further comprises: forming a second channel structure suspended vertically above the substrate and sandwiched between source/drain structures of a second type, and forming a first gate dielectric layer having a first portion wrapped around the first channel structure and a second portion wrapped around the second channel structure. The method for fabricating the semiconductor structure further comprises: a first dipole layer is formed in physical contact with a first portion of the first gate dielectric layer and spaced apart from a second portion of the first gate dielectric layer, and a second gate dielectric layer is formed over the first gate dielectric layer. Wherein the first gate dielectric layer and the second gate dielectric layer are made of the same dielectric material. The method for fabricating the semiconductor structure further comprises: a cap layer is formed that wraps around the first and second channel structures over the second gate dielectric layer, and after the cap layer is formed, the first and second gate dielectric layers are annealed.

In some embodiments, the method for fabricating a semiconductor structure further comprises: forming a work function metal layer in direct contact with the top surface of the cap layer; and forming a gate fill layer in direct contact with a top surface of the work function metal layer, wherein a first portion of the work function metal layer vertically formed over a topmost structure of the first channel structure has a first thickness and a second portion of the work function metal layer vertically formed over a topmost structure of the second channel structure has a second thickness substantially equal to the first thickness.

In some embodiments, the method for fabricating a semiconductor structure further comprises: driving a first element metal of a first dipole layer into a first portion of a first gate dielectric layer; and removing the first dipole layer prior to forming the second gate dielectric layer.

In some embodiments, the method for fabricating a semiconductor structure further comprises: forming a second dipole layer in physical contact with a second portion of the first gate dielectric layer; and driving the second metal element of the second dipole layer into the second portion of the first gate dielectric layer.

In some embodiments, the method for fabricating a semiconductor structure further comprises: a dielectric wall structure is formed that is laterally interposed between the first channel structure and the second channel structure, wherein a first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure and a second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure opposite the first sidewall.

In some embodiments, the method for fabricating a semiconductor structure further comprises: forming a first semiconductor stack over a substrate and forming a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack includes alternately stacked layers of a first semiconductor material and layers of a second semiconductor material; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; removing the first semiconductor material layer of the first semiconductor stack to form a first channel structure using the second semiconductor material layer of the first semiconductor stack; and removing the first semiconductor material layer of the second semiconductor stack to form a second channel structure using the second semiconductor material layer of the second semiconductor stack, wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a first type of source/drain structure formed in a first region over the substrate and a second type of source/drain structure formed in a second region over the substrate; first channel structures separated from each other along a first direction and interposed with source/drain structures of a first type along a second direction different from the first direction; the second channel structure, separate each other along the first direction, and insert the source/drain structure of the second type along the second direction; a gate dielectric layer having a first portion wrapped around the first channel structure in a first region and a second portion wrapped around the second channel structure in a second region. Further, the first portion of the gate dielectric layer is doped with a first metal element, and a concentration of the first metal element in a lower portion of the first portion of the gate dielectric layer is greater than a concentration of the first metal element in an upper portion of the first portion of the gate dielectric layer. The semiconductor structure further includes a work function metal layer formed over the first portion and the second portion of the gate dielectric layer.

In some embodiments, the semiconductor structure further comprises: and a gate fill layer continuously extending from the first region to the second region and oriented longitudinally along a third direction different from the first direction and the second direction, wherein a distance between the gate fill layer in the first direction and a top surface of a topmost structure of the first channel structure is substantially equal to a distance between top surfaces of topmost structures of the second channel structure in the first direction.

In some embodiments, the second portion of the gate dielectric layer is doped with a second metal element, the second portion of the gate dielectric layer is free of the first metal element, and the first portion of the gate dielectric layer is free of the second metal element.

In some embodiments, the semiconductor structure further comprises: a dielectric wall structure sandwiched between the first channel structure and the second channel structure and oriented longitudinally in the second direction, wherein the first and second portions of the gate dielectric layer each partially cover a top surface of the dielectric wall structure.

In some embodiments, the portion of the work function metal layer is vertically sandwiched between a topmost structure of the first channel structure and a bottommost structure of the second channel structure.

In some embodiments, the semiconductor structure further comprises: and a gate filling layer surrounding the first channel structure and the second channel structure, wherein a portion of the gate filling layer is vertically sandwiched between a topmost structure of the first channel structure and a bottommost structure of the second channel structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a first channel structure in the first region and forming a second channel structure in the second region;

forming a first type of source/drain structure attached to opposite sides of the first channel structure and a second type of source/drain structure attached to opposite sides of the second channel structure;

forming a first gate dielectric layer having a first portion overlying the first channel structure and a second portion overlying the second channel structure;

Driving a first metal element into the first portion of the first gate dielectric layer;

forming a cap layer over the first portion and the second portion of the first gate dielectric layer after driving the first metal element into the first portion of the first gate dielectric layer;

performing an annealing process on the first gate dielectric layer under the cap layer; and

a work function metal layer is formed that extends continuously from the first region to the second region and covers the first channel structure and the second channel structure.

2. The method for fabricating a semiconductor structure of claim 1, further comprising:

a second gate dielectric layer is formed over the first portion and the second portion of the first gate dielectric layer after driving the first metallic element into the first portion of the first gate dielectric layer.

3. The method for fabricating a semiconductor structure of claim 1, further comprising:

a second metallic element is driven into a second portion of the first gate dielectric layer in the second region, wherein the first metallic element is different from the second metallic element.

4. A method for fabricating a semiconductor structure, comprising:

forming a first type of source/drain structure and a second type of source/drain structure over a substrate;

forming a first channel structure vertically suspended above the substrate and sandwiched between source/drain structures of the first type;

forming a second channel structure vertically suspended above the substrate and sandwiched between source/drain structures of the second type;

forming a first gate dielectric layer having a first portion wrapped around the first channel structure and a second portion wrapped around the second channel structure;

forming a first dipole layer in physical contact with the first portion of the first gate dielectric layer and spaced apart from the second portion of the first gate dielectric layer;

forming a second gate dielectric layer over the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of the same dielectric material;

forming a cap layer surrounding the first channel structure and the second channel structure over the second gate dielectric layer; and

After forming the cap layer, the first gate dielectric layer and the second gate dielectric layer are annealed.

5. The method for fabricating a semiconductor structure of claim 4, further comprising:

forming a work function metal layer in direct contact with a top surface of the cap layer; and

forming a gate fill layer in direct contact with a top surface of the work function metal layer,

wherein a first portion of the work function metal layer vertically formed over a topmost structure of the first channel structure has a first thickness and a second portion of the work function metal layer vertically formed over a topmost structure of the second channel structure has a second thickness equal to the first thickness.

6. The method for fabricating a semiconductor structure of claim 4, further comprising:

driving a first metal element of the first dipole layer into the first portion of the first gate dielectric layer; and

the first dipole layer is removed prior to forming the second gate dielectric layer.

7. The method for fabricating a semiconductor structure of claim 4, further comprising:

forming a dielectric wall structure laterally interposed between the first channel structure and the second channel structure,

Wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure opposite the first sidewall.

8. The method for fabricating a semiconductor structure of claim 4, further comprising:

forming a first semiconductor stack over the substrate and forming a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack comprises alternately stacked layers of a first semiconductor material and layers of a second semiconductor material;

patterning the first semiconductor stack and the second semiconductor stack to form a fin structure;

removing the first semiconductor material layer of the first semiconductor stack to form the first channel structure with the second semiconductor material layer of the first semiconductor stack; and

removing the first semiconductor material layer of the second semiconductor stack to form the second channel structure with the second semiconductor material layer of the second semiconductor stack,

Wherein the first portion of the first gate dielectric layer vertically overlaps the second portion of the first gate dielectric layer.

9. A semiconductor structure, comprising:

a first type of source/drain structure formed in a first region over a substrate and a second type of source/drain structure formed in a second region over the substrate;

first channel structures separated from each other along a first direction and interposed in the first type of source/drain structures along a second direction different from the first direction;

second channel structures separated from each other along the first direction and interposed with the second type of source/drain structures along the second direction;

a gate dielectric layer having a first portion wrapped around the first channel structure in the first region and a second portion wrapped around the second channel structure in the second region, wherein the first portion of the gate dielectric layer is doped with a first metal element and a concentration of the first metal element in a lower portion of the first portion of the gate dielectric layer is greater than a concentration of the first metal element in an upper portion of the first portion of the gate dielectric layer; and

A work function metal layer formed over the first portion and the second portion of the gate dielectric layer.

10. The semiconductor structure of claim 9, further comprising:

a gate fill layer extending continuously from the first region to the second region and oriented longitudinally along a third direction different from the first direction and the second direction,

wherein a distance between the gate fill layer and a top surface of a topmost structure of the first channel structure in the first direction is equal to a distance between top surfaces of topmost structures of the second channel structure in the first direction.