CN117877976A - Method for manufacturing semiconductor device with improved overlay measurement accuracy - Google Patents

Method for manufacturing semiconductor device with improved overlay measurement accuracy Download PDF

Info

Publication number
CN117877976A
CN117877976A CN202311302591.3A CN202311302591A CN117877976A CN 117877976 A CN117877976 A CN 117877976A CN 202311302591 A CN202311302591 A CN 202311302591A CN 117877976 A CN117877976 A CN 117877976A
Authority
CN
China
Prior art keywords
layer
mask layer
forming
molding
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311302591.3A
Other languages
Chinese (zh)
Inventor
李昭荣
金允熙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020230046764A external-priority patent/KR20240050248A/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN117877976A publication Critical patent/CN117877976A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a semiconductor device comprising: forming a step bond on a substrate; forming a molding layer covering the step key on the step key; forming a first mask layer on the molding layer; forming a transparent layer overlapping the step key in the first mask layer; forming a second mask layer on the first mask layer and the transparent layer; the molding layer is etched using a second mask layer, wherein the first mask layer comprises a metallic material.

Description

Method for manufacturing semiconductor device with improved overlay measurement accuracy
Cross Reference to Related Applications
Korean patent application No. 10-2022-0129804, filed on 10-11 in 2022, and korean patent application No.10-2023-0046764, filed on 4-4 in 2023, are incorporated herein by reference in their entirety.
Technical Field
A method for manufacturing a semiconductor device having improved overlay measurement accuracy is disclosed.
Background
With the high integration of semiconductor devices, the line width of patterns included in semiconductor devices becomes finer and finer, and complex processes and novel materials are applied to the manufacturing process, so that the difficulty of the measurement process is also increasing.
Disclosure of Invention
Embodiments relate to a method for manufacturing a semiconductor device, the method including: forming a step bond on a substrate; forming a molding layer covering the step key on the step key; forming a first mask layer on the molding layer; forming a transparent layer overlapping the step key in the first mask layer; forming a second mask layer on the first mask layer and the transparent layer; the molding layer is etched using a second mask layer, wherein the first mask layer comprises a metallic material.
Embodiments relate to a method for manufacturing a semiconductor device, the method including: forming a substrate including a chip region and an off-chip region; forming a step bond on an off-chip region of the substrate; forming a molding layer covering the step key on the substrate; forming a first mask layer on the molding layer; forming a key hole overlapping the step key in the first mask layer; forming a transparent layer in the key hole; forming a second mask layer on the first mask layer and the transparent layer while aligning the second mask layer using the step key; etching the molding layer using the second mask layer to form a pattern hole; and filling the pattern holes with a pattern material to form the pillar structures.
Embodiments relate to a method for manufacturing a semiconductor device, the method including: forming a substrate including a chip region and an off-chip region; forming bit lines on the substrate in the chip region extending across the substrate; forming buried contacts between the bit lines and connected to the chip region of the substrate; forming a landing pad on the buried contact; forming a step bond on the substrate in an off-chip region; forming a molding layer covering the bonding pad and the step bond on the chip region and the off-chip region; forming a first mask layer on the molding layer, wherein the first mask layer comprises a metallic material; forming a key hole overlapping the step key in the first mask layer; forming a transparent layer in the key hole; forming a second mask layer on the first mask layer and the transparent layer while aligning the second mask layer using the step key; etching the molding layer in the chip region using the second mask layer to form a pattern hole; forming a lower electrode filling the pattern hole; and forming a dielectric film and an upper electrode on the lower electrode, the transparent layer having a light transmittance greater than that of the first mask layer, and a first vertical height of an upper surface of the lower electrode extending farther in a vertical direction with respect to a bottom surface of the substrate than a second vertical height of an upper surface of the molding layer.
Drawings
Features will become apparent to those skilled in the art from the detailed description of an exemplary embodiment with reference to the accompanying drawings, in which:
fig. 1 to 12 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 13 to 15 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 16 to 18 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 19 to 26 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 27 to 29 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 30 to 32 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 33 is a diagram showing stages in a method for manufacturing a semiconductor device according to an example embodiment.
Fig. 34 to 39 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 40 to 45 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 46 to 54 are diagrams showing stages in a method for manufacturing a semiconductor device according to an exemplary embodiment.
Fig. 55 to 64 are diagrams illustrating a semiconductor device manufactured using a method for manufacturing a semiconductor device according to example embodiments.
Fig. 65 to 70 are diagrams illustrating a semiconductor device manufactured using a method for manufacturing a semiconductor device according to example embodiments.
Detailed Description
Hereinafter, embodiments according to the technical ideas of the present disclosure will be described with reference to the drawings.
Fig. 1 to 12 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. Referring to fig. 1, a first step key (step key) K1 and a first molding layer MD1 may be on a substrate 100.
The first step key K1 may include a groove recessed toward the lower surface of the substrate 100. In an implementation, the first step key K1 may have a step from the upper surface of the substrate 100 toward the lower surface of the substrate 100.
The first molding layer MD1 may be on the substrate 100. The first molding layer MD1 may be on the first step key K1 including the groove. The first molding layer MD1 may cover the first step key K1. The first molding layer MD1 is shown as a single layer. In an implementation, the first molding layer MD1 may include a multilayer film.
The first molding layer MD1 may have a curved upper surface in a region overlapping with the first step key K1. In an implementation, the first molding layer MD1 may have grooves GR that overlap the first step key K1. Since the first step key K1 has a groove recessed toward the lower surface of the substrate 100, the upper surface of the first molding layer MD1 may be recessed toward the substrate 100 in a region overlapping with the first step key K1.
Referring to fig. 2, a first pre-mask layer 210P may be on the first molding layer MD1. The first pre-mask layer 210P may extend along an upper surface of the first molding layer MD1. The first pre-mask layer 210P may cover the first molding layer MD1.
The first pre-mask layer 210P may include a metal material. In an implementation, the first pre-mask layer 210P may include a material doped with a metal. In some embodiments, the first pre-mask layer 210P may include aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), or lanthanum (La), or an alloy of the above materials. The first pre-mask layer 210P may be opaque. As used herein, the term "or" is not an exclusive term, e.g., "a or B" would include A, B, or a and B.
The first pre-mask layer 210P may have a higher etching selectivity with respect to the first molding layer MD1. When the first molding layer MD1 is etched into a pattern having a high aspect ratio, the first pre-mask layer 210P having a higher etching selectivity with respect to the first molding layer MD1 may be used to stably etch the first molding layer MD1. The light transmittance of the first pre-mask layer 210P may be lower than that of the first molding layer MD1. Referring to fig. 3, a key hole H1 may be in the first mask layer 210.
The keyhole H1 may extend through the first mask layer 210. The key hole H1 may overlap the first step key K1. The keyhole H1 may expose an upper surface of the first molding layer MD1. The keyhole H1 may expose a curved surface of the first molding layer MD1. The keyhole H1 may expose a groove (GR in fig. 1) of the upper surface of the first molding layer MD1. Referring to fig. 4, a pre-transparent layer 220P may be on the first mask layer 210.
The pre-transparent layer 220P may cover the first mask layer 210. The pre-transparent layer 220P may fill the key hole H1 in fig. 3. The upper surface of the pre-transparent layer 220P may be located at a height higher than that of the upper surface of the first mask layer 210.
The pre-transparent layer 220P may include hafnium oxide (HfO 2 ) Titanium oxide (TiO) 2 ) Tantalum oxide (TaO) 2 ) Silicon oxide (SiO) 2 ) Or silicon nitride (Si) 3 N 4 ). The light transmittance of the pre-transparent layer 220P may be greater than the light transmittance of the first mask layer 210. The extinction coefficient and refractive index of the pre-transparent layer 220P may be lower than those of the first mask layer 210, respectively. By CVD (chemical vapor deposition), PVD (physical gas)Phase deposition) or ALD (atomic layer deposition) to form the pre-transparent layer 220P.
Referring to fig. 5, a transparent layer 220 may be in the first mask layer 210. The upper surface of the first mask layer 210 may be exposed by removing the pre-transparent layer 220P covering the upper surface of the first mask layer 210 in fig. 4. The upper surface of the transparent layer 220 may be coplanar with the upper surface of the first mask layer 210. The transparent layer 220 may fill the key holes (H1 in fig. 3) in the first mask layer 210. The transparent layer 220 may overlap the first step key K1. The transparent layer 220 may be surrounded by the first mask layer 210. The sidewalls of the transparent layer 220 may be covered with the first mask layer 210. The width of the transparent layer 220 may be greater than or equal to the width of the first step key K1. The portion of the pre-transparent layer (220P in fig. 4) located on top of the upper surface of the first mask layer 210 may be removed by CMP (chemical mechanical polishing).
Referring to fig. 6, a second mask layer 230 may be on the first mask layer 210 and the transparent layer 220. The second mask layer 230 may extend along upper surfaces of the first mask layer 210 and the transparent layer 220. The second mask layer 230 may cover the first mask layer 210 and the transparent layer 220.
The second mask layer 230 may include silicon oxide or silicon nitride. The second mask layer 230 is shown as a single layer. In an implementation, the second mask layer 230 may include a multi-layer film. Referring to fig. 7, a third mask layer 240 may be on the second mask layer 230.
The third mask layer 240 may cover the second mask layer 230. The third mask layer 240 may include photoresist. The third mask layer 240 may include a pattern for etching the first molding layer MD 1. The third mask layer 240 may have a pattern exposing a portion of the upper surface of the second mask layer 230. The third mask layer 240 may have a pattern so as not to cover the portion of the upper surface of the second mask layer 230.
The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered at a target position.
In an implementation, to determine whether the third mask layer 240 is properly aligned, light may be irradiated onto the first step key K1. Whether the third mask layer 240 is properly aligned may be determined based on the result of detecting the polarization state and diffraction of light that impinges on the first step key K1.
The first mask layer 210 including a metal material may have low light transmittance. Accordingly, the first mask layer 210 may be on the first step key K1. Therefore, even if light is irradiated to determine whether the third mask layer 240 is properly aligned, it may not be easy to detect the polarization state and diffraction of light using the first step key K1. Alternatively, the transparent layer 220 may overlap the first step key K1. In this case, since the light transmittance of the transparent layer 220 is higher than that of the first mask layer 210, it is possible to easily determine whether the third mask layer 240 is properly aligned based on the result of detecting the polarization state and diffraction of light irradiated toward the first step key K1.
Referring to fig. 8, the first molding layer MD1 may be etched using the third mask layer 240. Using the pattern of the third mask layer 240, pattern holes H2 may be formed in the first molding layer MD1, the first mask layer 210, and the second mask layer 230. The pattern hole H2 may extend through the first molding layer MD1 and the first mask layer 210. Using the first step key K1, the pattern hole H2 may be formed at a target position on the substrate 100.
Referring to fig. 9, the second mask layer 230 and the third mask layer 240 may be removed. The first mask layer 210 and the transparent layer 220 may be exposed. The pattern holes H2 may be in the first molding layer MD1 and the first mask layer 210.
Referring to fig. 10, a pillar structure 250 may be formed. The pillar structures 250 may be in a pattern hole (H2 in fig. 9). The pillar structures 250 may fill the pattern holes (H2 in fig. 9). The pattern material may fill the pattern holes (H2 in fig. 9). The upper surfaces of the pillar structures 250 may be coplanar with the upper surface of the first mask layer 210. The upper surface of the pillar structures 250 may be located at a height higher than that of the upper surface of the first molding layer MD1 based on the lower surface of the substrate 100.
In an implementation, the pillar structure 250 may include a lower electrode of a DRAM capacitor. In another example, pillar structures 250 may include channel structures of non-volatile memory such as NAND. In yet another example, the post structures 250 may include vias.
Referring to fig. 11, the first mask layer 210 and the transparent layer 220 may be removed. The upper surface of the first molding layer MD1 may be exposed. When the first mask layer 210 has been removed, a portion of the sidewalls of the pillar structures 250 may be exposed. The pillar structures 250 may protrude upward beyond the upper surface of the first molding layer MD 1.
Referring to fig. 12, a second molding layer MD2 and a protective film 260 may be on the first molding layer MD 1. The second molding layer MD2 may surround the exposed portions of the sidewalls of the pillar structures 250. The second molding layer MD2 may extend along an upper surface of the first molding layer MD 1. The protective film 260 may extend along an upper surface of the second molding layer MD 2. The protective film 260 may cover the upper surface of the pillar structures 250.
In an implementation, the second molding layer MD2 may include silicon oxide. The protective film 260 may include silicon nitride. In fig. 12, each of the second molding layer MD2 and the protective film 260 is shown as a single-layer film. In an implementation, each of the second molding layer MD2 and the protective film 260 may include a multi-layer film.
Fig. 13 to 15 are diagrams showing intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment.
For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. For reference, fig. 13 is a diagram showing steps subsequent to fig. 8.
Referring to fig. 8 and 13, after the pattern hole H2 is formed, the first, transparent, second, and third mask layers 210, 220, 230, and 240 may be removed. The pattern holes H2 may extend only through the first molding layer MD1. The first, transparent, second and third mask layers 210, 220, 230 and 240 may be removed so that the upper surface of the first molding layer MD1 may be exposed.
Referring to fig. 14, a pillar structure 250 may be formed. The pillar structures 250 may be in the pattern holes (H2 of fig. 13). The pillar structures 250 may fill the pattern holes (H2 in fig. 13). The upper surface of the pillar structures 250 may be coplanar with the upper surface of the first molding layer MD1. The entire sidewall of the pillar structures 250 may be surrounded by the first molding layer MD1.
Referring to fig. 14, the vertical dimension of the pillar structure (250 in fig. 14) may be smaller than the vertical dimension of the pillar structure (250 in fig. 10) as compared to fig. 10.
Referring to fig. 15, a protective film 260 may be formed. The protective film 260 may be on the first molding layer MD1 and the pillar structures 250. The protective film 260 may extend along an upper surface of the first molding layer MD 1. The protective film 260 may cover the upper surface of the pillar structures 250.
Fig. 16 to 18 are diagrams showing intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment.
For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. For reference, fig. 16 is a diagram showing steps subsequent to fig. 10. Referring to fig. 10 and 16, after forming the pillar structures 250, the first mask layer 210 may be removed.
When the first mask layer 210 is removed, sidewalls of the transparent layer 220 may be exposed. The pillar structures 250 may protrude upward beyond the upper surface of the first molding layer MD 1. The transparent layer 220 may be on the first molding layer MD 1. The upper surface of the pillar structures 250 and the upper surface of the transparent layer 220 may be coplanar with each other. In an implementation, the upper surface of the pillar structures 250 and the upper surface of the transparent layer 220 may have the same vertical height based on the lower surface of the substrate 100.
Referring to fig. 17, a second molding layer MD2 may be formed. The second molding layer MD2 may fill the space between adjacent ones of the portions of the pillar structures 250 protruding upward beyond the upper surface of the first molding layer MD 1. The second molding layer MD2 may be between the pillar structures 250.
Referring to fig. 18, a protective film 260 may be formed. The protective film 260 may be on the transparent layer 220, the first molding layer MD1, the pillar structures 250, and the second molding layer MD2. The protective film 260 may extend along the contours of the transparent layer 220, the first molding layer MD1, the pillar structures 250, and the second molding layer MD2.
The protective film 260 may surround the transparent layer 220. The protective film 260 may cover the upper surface and the sidewalls of the transparent layer 220. The protective film 260 may cover the upper surface of the pillar structures 250 and the upper surface of the second molding layer MD2.
Fig. 19 to 26 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment.
For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. For reference, fig. 19 is a diagram showing steps subsequent to fig. 2. Fig. 20 is an enlarged view of a portion P of fig. 19.
Referring to fig. 2, 19 and 20, a key hole H1 may be on the first mask layer 210. The keyhole H1 may extend through only a portion of the first mask layer 210. The key hole H1 may expose the first mask layer 210. The inner sidewall and bottom surface of the keyhole H1 may be defined by the first mask layer 210. The key hole H1 may overlap the first step key K1.
The first mask layer 210 may include a first portion 211 and a second portion 212. The first portion 211 may be on one side of the key hole H1. The first portion 211 may define an inner sidewall of the keyhole H1. The first portion 211 may not overlap the first step key K1.
The second portion 212 may be below the keyhole H1. The second portion 212 may define a bottom surface of the keyhole H1. The second portion 212 may overlap the first step key K1.
The thickness of the second portion 212 may be less than the depth of the keyhole H1. In an implementation, the thickness TH212 of the second portion may be less than a distance from an upper surface of the second portion 212 to an upper surface of the first portion 211. The thickness TH211 of the first portion may be greater than the thickness TH212 of the second portion based on the lower surface of the substrate 100.
The thickness of the second portion 212 may be within a range that light can be transmitted through the first mask layer 210. In an implementation, when the first mask layer 210 includes tungsten silicide (WSi), the second portion 212 may have a thickness of 100 to 200 angstromsWithin a range of (2).
Referring to fig. 21, a transparent layer 220 may be on the first mask layer 210. The transparent layer 220 may be in the keyhole (H1 of fig. 19). The transparent layer 220 may fill the key hole (H1 in fig. 19). The lower surface and the side surfaces of the transparent layer 220 may be surrounded by the first mask layer 210. The transparent layer 220 may not contact the first molding layer MD1. The lower surface of the transparent layer 220 may be spaced apart from the upper surface of the first molding layer MD1. The upper surface of the transparent layer 220 may be coplanar with the upper surface of the first mask layer 210.
Referring to fig. 22, a second mask layer 230 and a third mask layer 240 may be on the transparent layer 220 and the first mask layer 210. The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
To determine whether the third mask layer 240 is properly aligned, light may be irradiated onto the first step key K1. The light transmittance of the first mask layer 210 may be less than the light transmittance of the transparent layer 220. However, the thickness of the first mask layer 210 under the transparent layer 220 may be small, so that light may be stably irradiated to the first step key K1. In implementations, the thickness of the second portion of the first mask layer 210 (TH 212 of fig. 20) under the transparent layer 220 can be 200 angstroms or less.
Whether the third mask layer 240 is properly aligned may be determined based on the result of detecting the polarization state and diffraction of light irradiated to the first step key K1 through the transparent layer 220 and the first mask layer 210.
Referring to fig. 23, a pattern hole H2 may be formed using a third mask layer 240. Using the pattern of the third mask layer 240, the first molding layer MD1, the first mask layer 210, and the second mask layer 230 may be etched.
Referring to fig. 24, the second mask layer 230 and the third mask layer 240 may be removed. Referring to fig. 25, a pillar structure 250 may be formed. Referring to fig. 26, a protective film 260 may be formed. The protective film 260 may cover the pillar structures 250, the first mask layer 210, and the transparent layer 220.
Fig. 27 to 29 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 19 to 26 will be mainly described. For reference, fig. 27 is a diagram showing steps subsequent to fig. 25.
Referring to fig. 25 and 27, a portion of the first mask layer 210 may be removed. In the region where the pillar structures 250 are located, the first mask layer 210 may be removed. The remaining portion of the first mask layer 210 may surround the transparent layer 220. The first mask layer 210 may surround side surfaces and a lower surface of the transparent layer 220.
The pillar structures 250 may not be surrounded by the first mask layer 210. The pillar structures 250 may protrude upward beyond the top surface of the first molding layer MD 1. The pillar structures 250 may not be in contact with the first mask layer 210.
Referring to fig. 28, a second molding layer MD2 may be formed. The second molding layer MD2 may be between the pillar structures 250. The second molding layer MD2 may be spaced apart from the first mask layer 210. The second molding layer MD2 may not contact the first mask layer 210.
Referring to fig. 29, a protective film 260 may be formed. The protective film 260 may be on the transparent layer 220, the first molding layer MD1, the first mask layer 210, the pillar structures 250, and the second molding layer MD 2. The transparent layer 220 may be surrounded by the first mask layer 210 and the protective film 260.
Fig. 30 to 32 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 19 to 26 will be mainly described. For reference, fig. 30 is a diagram showing steps subsequent to fig. 25.
Referring to fig. 25 and 30, a portion of the first mask layer 210 may be removed. Portions of the first mask layer 210 that do not overlap the transparent layer 220 may be removed. The remaining portion of the first mask layer 210 may be under the transparent layer 220. The remaining portion of the first mask layer 210 may be between the transparent layer 220 and the first molding layer MD 1. The remaining portion of the first mask layer 210 may overlap the first step key K1. The sidewalls of the remaining portion of the first mask layer 210 may be coplanar with the sidewalls of the transparent layer 220. The width of each of the transparent layer 220 and the remaining portion of the first mask layer 210 may be greater than the width of the first step key K1.
Referring to fig. 31, a second molding layer MD2 may be formed. The second molding layer MD2 may be between the pillar structures 250. The second molding layer MD2 may be spaced apart from the first mask layer 210 and the transparent layer 220. The second molding layer MD2 may not overlap the first step key K1.
Referring to fig. 32, a protective film 260 may be formed. The protective film 260 may be on the transparent layer 220, the first molding layer MD1, the first mask layer 210, the pillar structures 250, and the second molding layer MD2. The protective film 260 may cover sidewalls of each of the first mask layer 210 and the transparent layer 220.
Fig. 33 is a diagram showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. For reference, fig. 33 is a diagram showing steps subsequent to fig. 10.
Referring to fig. 10 and 33, a protective film 260 may be on the first mask layer 210. Referring to fig. 33, in comparison with fig. 11, when the first mask layer 210 and the transparent layer 220 are not removed, a protective film 260 may be formed. The protective film 260 may be on the transparent layer 220, the first mask layer 210, and the pillar structures 250.
The upper surface of the pillar structures 250 may be covered with a protective film 260. A portion of the side surface of the pillar structures 250 may be surrounded by the first mask layer 210. The first mask layer 210 and the pillar structures 250 may be in direct contact with each other.
The material of the first mask layer 210 and the material of the pillar structures 250 may be different from each other. In an implementation, the first mask layer 210 may include a silicon alloy, and the pillar structures 250 may include titanium nitride (TiN). Even though the first mask layer 210 and the pillar structures 250 may be in direct contact with each other, the first mask layer 210 may not affect the electrical operation of the pillar structures 250.
Fig. 34 to 39 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. For reference, fig. 34 is a diagram showing steps subsequent to fig. 3.
Referring to fig. 34, the transparent layer 220 may be in the key hole H1. The transparent layer 220 may be formed in an ASD (area selective deposition) manner. The transparent layer 220 may be only on the surface of the first molding layer MD 1. The transparent layer 220 may not be on the first mask layer 210. The transparent layer 220 may not contact the first mask layer 210. The upper surface of the transparent layer 220 in the key hole H1 may be below the upper surface of the first mask layer 210.
Fig. 34 shows that the sidewalls of the transparent layer 220 are in contact with the sidewalls of the first mask layer 210. The sidewalls of the transparent layer 220 may not contact the sidewalls of the first mask layer 210.
Referring to fig. 35, a filler film 280 may be on the transparent layer 220. The filling film 280 may fill the key holes (H1 of fig. 34). The filling film 280 may cover the transparent layer 220. The filler film 280 may overlap with the transparent layer 220. The upper surface of the fill film 280 may be coplanar with the upper surface of the first mask layer 210. The side surface of each of the transparent layer 220 and the filling film 280 may be surrounded by the first mask layer 210.
The light transmittance of the filling film 280 may be greater than the light transmittance of the first mask layer 210. The light transmittance of the filling film 280 may be lower than that of the transparent layer 220. In an implementation, the fill film 280 may include silicon oxide.
Referring to fig. 36, a second mask layer 230 and a third mask layer 240 may be on the first mask layer 210 and the filling film 280. The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
To determine whether the third mask layer 240 is properly aligned, light may be irradiated to the first step key K1. The light irradiated to the first step key K1 may pass through the filling film 280 and the transparent layer 220, and then may reach the first step key K1.
Referring to fig. 37, the first molding layer MD1 may be etched using the third mask layer 240. Using the pattern of the third mask layer 240, pattern holes H2 may be formed in the first molding layer MD1, the first mask layer 210, and the second mask layer 230. The pattern hole H2 may extend through the first molding layer MD1 and the first mask layer 210. Using the first step key K1, the pattern hole H2 may be at a target position on the substrate 100.
Referring to fig. 38, the second mask layer 230 and the third mask layer 240 may be removed. The first mask layer 210 and the filling film 280 may be exposed. The pattern holes H2 may be in the first molding layer MD1 and the first mask layer 210.
Referring to fig. 39, a pillar structure 250 may be formed. The pillar structures 250 may be in the pattern holes (H2 in fig. 38). The pillar structures 250 may fill the pattern holes (H2 in fig. 38). The pattern material may fill the pattern holes (H2 in fig. 38). The upper surface of the pillar structures 250 may be coplanar with the upper surface of each of the first mask layer 210 and the fill film 280.
The upper surface of the pillar structures 250 may be located at a height higher than that of the upper surface of the first molding layer MD1 based on the lower surface of the substrate 100. The upper surface of the pillar structures 250 may be located at a height higher than that of the upper surface of the transparent layer 220 based on the lower surface of the substrate 100.
The steps following fig. 39 are substantially the same as those described with reference to fig. 11 and 12, and thus are briefly described. Subsequently, referring to fig. 39, 11, and 12, the first mask layer 210, the filling film 280, and the transparent layer 220 may be removed.
Since the first mask layer 210, the filling film 280, and the transparent layer 220 have been removed, the upper surface of the first molding layer MD1 may be exposed. The pillar structures 250 may protrude upward beyond the upper surface of the first molding layer MD 1.
Subsequently, the second molding layer MD2 and the protective film 260 may be on the first molding layer MD 1. The second molding layer MD2 may surround the exposed portions of the sidewalls of the pillar structures 250. The protective film 260 may extend along an upper surface of the second molding layer MD 2. The protective film 260 may cover the upper surface of the pillar structures 250.
Fig. 40 to 45 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 34 to 39 will be mainly described. For reference, fig. 40 is a diagram showing steps subsequent to fig. 3.
Referring to fig. 40, the transparent layer 220 may be in the key hole H1. The transparent layer 220 may be formed in an ASD (area selective deposition) manner. The transparent layer 220 may be only on the surface of the first molding layer MD 1. The transparent layer 220 may not be on the first mask layer 210. The transparent layer 220 may not contact the first mask layer 210. The upper surface of the transparent layer 220 in the key hole H1 may be below the upper surface of the first mask layer 210.
Referring to fig. 40, the thickness of the transparent layer 220 in fig. 40 may be greater than that of the transparent layer 220 in fig. 34, as compared to fig. 34. The step between the upper surface of the transparent layer 220 and the upper surface of the first mask layer 210 in fig. 40 may be smaller than the step between the upper surface of the transparent layer 220 and the upper surface of the first mask layer 210 in fig. 23.
Fig. 40 shows that the sidewalls of the transparent layer 220 contact the sidewalls of the first mask layer 210. The sidewalls of the transparent layer 220 may not contact the sidewalls of the first mask layer 210.
Referring to fig. 41, a second mask layer 230 may be on the first mask layer 210 and the transparent layer 220. The second mask layer 230 may fill the key hole (H1 in fig. 40). The second mask layer 230 may be on the transparent layer 220 in the key hole (H1 in fig. 40). The second mask layer 230 may cover the first mask layer 210 and the transparent layer 220. The second mask layer 230 may have a curved surface in a region overlapping the first step key K1.
Referring to fig. 42, a third mask layer 240 may be on the second mask layer 230. The third mask layer 240 may cover the second mask layer 230. The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
Referring to fig. 43, the first molding layer MD1 may be etched using the third mask layer 240. Using the pattern of the third mask layer 240, pattern holes H2 may be formed in the first molding layer MD1, the first mask layer 210, and the second mask layer 230. The pattern hole H2 may extend through the first molding layer MD1 and the first mask layer 210. Using the first step key K1, the pattern hole H2 may be at a target position on the substrate 100.
Referring to fig. 44, the second mask layer 230 and the third mask layer 240 may be removed. The first mask layer 210 and the transparent layer 220 may be exposed. The upper surface of the transparent layer 220 may be below the upper surface of the first mask layer 210 based on the lower surface of the substrate 100. The pattern holes H2 may be in the first molding layer MD1 and the first mask layer 210.
The transparent layer 220 may have an etching selectivity with respect to each of the second mask layer 230 and the third mask layer 240. Accordingly, the second mask layer 230 and the third mask layer 240 may be removed, and the transparent layer 220 may not be removed.
Referring to fig. 45, a pillar structure 250 may be formed. The pillar structures 250 may be in the pattern holes (H2 in fig. 38). The pillar structures 250 may fill the pattern holes (H2 in fig. 38). The upper surfaces of the pillar structures 250 may be coplanar with the upper surface of the first mask layer 210. The upper surface of the pillar structures 250 may be located at a height higher than that of the upper surface of the transparent layer 220 based on the lower surface of the substrate 100.
The steps following fig. 45 are substantially the same as those described with reference to fig. 11 and 12, and thus are briefly described. Subsequently, referring to fig. 45, 11 and 12, the first mask layer 210 and the transparent layer 220 may be removed. Subsequently, the second molding layer MD2 and the protective film 260 may be on the first molding layer MD 1. The second molding layer MD2 may surround a portion of the sidewall of the pillar structure 250 that is exposed when the first mask layer 210 is removed. The protective film 260 may extend along an upper surface of the second molding layer MD 2. The protective film 260 may cover the upper surface of the pillar structures 250.
Fig. 46 to 54 are diagrams showing intermediate structures respectively corresponding to intermediate steps of a method for manufacturing a semiconductor device according to an example embodiment. For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described.
Referring to fig. 46, a second step key K2 and a first molding layer MD1 may be on the substrate 100. The second step key K2 may include a convex protrusion toward the first molding layer MD 1. In an implementation, the second step key K2 may have a step protruding upward from the upper surface of the substrate 100.
The first molding layer MD1 may be on the substrate 100. The first molding layer MD1 may be on the second step key K2 including the protrusion. The first molding layer MD1 may cover the second step key K2. The first molding layer MD1 is shown as a single layer. In an implementation, the first molding layer MD1 may include a multilayer film.
The first molding layer MD1 may have a curved surface in a region overlapping with the second step key K2. In an implementation, the first molding layer MD1 may have a protrusion PR overlapping the second step key K2. Since the second step key K2 has a convex step toward the first molding layer MD1, the upper surface of the first molding layer MD1 may protrude in a direction opposite to the direction toward the substrate 100 in a region overlapping with the second step key K2.
Referring to fig. 47, a first pre-mask layer 210P may be on the first molding layer MD 1. The first pre-mask layer 210P may include a metal material. In an implementation, the first pre-mask layer 210P may include a material doped with a metal. The first pre-mask layer 210P may be opaque. The light transmittance of the first pre-mask layer 210P may be lower than that of the first molding layer MD 1.
Referring to fig. 48, a key hole H1 may be in the first mask layer 210. The keyhole H1 may extend through the first mask layer 210. The key hole H1 may overlap the second step key K2. The keyhole H1 may expose an upper surface of the first molding layer MD 1. The keyhole H1 may expose a curved surface of the first molding layer MD 1. The keyhole H1 may expose a protrusion (PR in fig. 46) of the first molding layer MD 1.
Referring to fig. 49, a pre-transparent layer 220P may be on the first mask layer 210. The light transmittance of the pre-transparent layer 220P may be greater than the light transmittance of the first mask layer 210. The extinction coefficient and refractive index of the pre-transparent layer 220P may be lower than those of the first mask layer 210, respectively.
Referring to fig. 50, a transparent layer 220 may be in the first mask layer 210. Referring to fig. 51, a second mask layer 230 and a third mask layer 240 may be on the first mask layer 210 and the transparent layer 220.
The third mask layer 240 may include photoresist. The third mask layer 240 may include a pattern for etching the first molding layer MD1. The third mask layer 240 may be aligned using the second step key K2. The second step key K2 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
Referring to fig. 52, the first molding layer MD1 may be etched using the third mask layer 240. The pattern holes H2 may be in the first mask layer 210, the first molding layer MD1, the second mask layer 230, and the third mask layer 240.
Referring to fig. 53, the second mask layer 230 and the third mask layer 240 may be removed. Referring to fig. 54, a pillar structure 250 may be formed.
The upper surfaces of the pillar structures 250 may be coplanar with the upper surface of the first mask layer 210. The upper surface of the pillar structures 250 may be located at a height higher than that of the upper surface of the first molding layer MD1 based on the lower surface of the substrate 100.
In an implementation, the pillar structure 250 may include a lower electrode of a DRAM capacitor. In another example, pillar structures 250 may include channel structures of non-volatile memory such as NAND. In yet another example, the pillar structures 250 may include vias of a semiconductor device.
Fig. 55 to 64 are diagrams illustrating a semiconductor device manufactured using a method for manufacturing a semiconductor device according to example embodiments. For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described.
Referring to fig. 55, a substrate 100 including a chip area CA and an off-chip area OCA may be formed. A plurality of bit line structures 340ST, buried contacts 320, landing pads 360, and etch stop film 130 may be on substrate 100 and in chip area CA.
The off-chip wire 440, the interlayer insulating film 480, and the off-chip etching stopper film 430 may be on the substrate 100 and in the off-chip region OCA. The etch stop film 130 and the off-chip etch stop film 430 may be at the same height.
The first step key K1 may be on the substrate 100 and in the off-chip area OCA. The first step key K1 may include a groove recessed toward the lower surface of the substrate 100. In an implementation, the first step key K1 may have a step down toward the upper surface of the substrate 100.
The first molding layer MD1 may span the chip area CA and the off-chip area OCA. Subsequently, the first mask layer 210, the transparent layer 220, and the second mask layer 230 may be on the first molding layer MD1.
The first molding layer MD1 may include a first molding film 111, a first pre-support film 141P, a second molding film 112, a second pre-support film 142P, a third molding film 113, and a third pre-support film 143P. The first molding layer MD1 may correspond to the first molding layer MD1 of fig. 1 to 54.
In an implementation, each of the first, second, and third molding films 111, 112, and 113 may include silicon oxide. Each of the first, second, and third pre-support films 141P, 142P, and 143P may include silicon nitride. Each of the first, second, and third pre-support films 141P, 142P, and 143P may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN).
In the off-chip region OCA, the first molding layer MD1 may be on the first step key K1. The first molding layer MD1 may cover the first step key K1. The first molding layer MD1 may have a curved surface in a region overlapping with the first step key K1.
The first mask layer 210 may surround the transparent layer 220. The upper surface of the first mask layer 210 may be coplanar with the upper surface of the transparent layer 220.
The first mask layer 210 may include a metal material. In an implementation, the first mask layer 210 may include a material doped with a metal. In some embodiments, the first mask layer 210 may include aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), lanthanum (La), or alloys of the above materials. The first mask layer 210 may be opaque.
The first mask layer 210 may have a higher etching selectivity with respect to the first molding layer MD 1. The transparent layer 220 may overlap the first step key K1. The width of the transparent layer 220 may be greater than the width of the first step key K1. The transparent layer 220 may be in the first mask layer 210.
The transparent layer 220 may include hafnium oxide (HfO 2 ) Titanium oxide (TiO) 2 ) Tantalum oxide (TaO) 2 ) Silicon oxide (SiO) 2 ) Or silicon nitride (Si) 3 N 4 ). The light transmittance of the transparent layer 220 may be greater than that of the first mask layer 210Light transmittance. The extinction coefficient and refractive index of the transparent layer 220 may be smaller than those of the first mask layer 210, respectively.
The second mask layer 230 may extend along the first mask layer 210 and the transparent layer 220 across the chip area CA and the off-chip area OCA. The second mask layer 230 may cover the first mask layer 210 and the transparent layer 220.
The element isolation film 305 may be in the substrate 100. The element isolation film 305 may have an STI (shallow trench isolation) structure having excellent element isolation characteristics. The element isolation film 305 may define an active region on the substrate 100.
The active region defined by the element isolation film 305 may have an elongated island shape including a short axis and a long axis. The active region may have an inclined shape to have an angle of less than 90 degrees with respect to the word line in the element isolation film 305.
Each of the element isolation films 305 may include, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Each element isolation film 305 is shown as embodied as one insulating film. Each element isolation film 305 may be composed of one insulating film or a plurality of insulating films depending on the width of the element isolation film 305.
In addition, the active region may have a diagonal shape to have an angle of less than 90 degrees with respect to the bit line on the element isolation film 305. The bit line structure 340ST may include a cell conductive line 340 and a cell line capping film 344. The cell wire 340 may be on a region of the substrate 100 in which a gate structure may be formed and on the element isolation film 305. The cell wire 340 may intersect the element isolation film 305 and the active region. The cell conductive line 340 may intersect the gate structure. In this regard, the cell conductive line 340 may correspond to a bit line.
The cell wire 340 may be composed of a stack of multi-layered films. The cell wire 340 may include, for example, a first cell conductive film 341, a second cell conductive film 342, and a third cell conductive film 343. The first to third unit conductive films 341, 342, and 343 may be sequentially stacked on the substrate 100 and the element isolation film 305. The cell wire 340 is shown as being embodied as a stack of three layers of film.
Each of the first to third unit conductive films 341, 342, and 343 may include, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a metal, or a metal alloy. In an implementation, the first cell conductive film 341 may include a doped semiconductor material, the second cell conductive film 342 may include a conductive silicide compound or a conductive metal nitride, and the third cell conductive film 343 may include a metal or a metal alloy.
Bit line contact 346 may be between cell wire 340 and substrate 100. In an implementation, the cell wire 340 may be on the bit line contact 346. In an implementation, the bit line contact 346 may be at a point where the cell wire 340 intersects a central portion of the active region having an elongated island shape.
The bit line contact 346 may electrically connect the cell wire 340 and the substrate 100 to each other. The bit line contact 346 may include, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.
In a region overlapping with the upper surface of the bit line contact 346, the cell wire 340 may include a second cell conductive film 342 and a third cell conductive film 343. In a region not overlapping with the upper surface of the bit line contact 346, the cell wire 340 may include first to third cell conductive films 341, 342, and 343.
A cell line capping film 344 may be on the cell wire 340. The cell line capping film 344 may extend along an upper surface of the cell wire 340. In this regard, the cell line capping film 344 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride oxide. In the semiconductor memory device according to some embodiments, the cell line capping film 344 may include, for example, a silicon nitride film. The cell line capping film 344 is shown as a single layer film. The cell line capping film 344 may be composed of a stack of multilayer films. However, when the films constituting the stack of the multilayer films are made of the same material, the cell line cover film 344 may be interpreted as being composed of a single layer film.
The unit insulating film 330 may be on the substrate 100 and the element isolation film 305. More specifically, the cell insulating film 330 may be on the region of the substrate 100 in which the bit line contact 346 is not formed and on the element isolation film 305. The unit insulating film 330 may be between the substrate 100 and the unit wire 340 and between the element isolation film 305 and the unit wire 340.
The unit insulating film 330 may be a single-layer film. However, as shown, the unit insulating film 330 may be composed of a stack of multi-layered films including the first unit insulating film 331 and the second unit insulating film 332. In an implementation, the first unit insulating film 331 may include a silicon oxide film, and the second unit insulating film 332 may include a silicon nitride film.
The cell line spacers 350 may be on sidewalls of each of the cell line 340 and the cell line capping film 344. The cell line spacer 350 may be located on the element isolation film 305 in a region of the substrate 100 in which the bit line contact 346 is formed. Cell line spacers 350 may be on sidewalls of each of the cell conductive lines 340, the cell line capping film 344, and the bit line contacts 346.
However, in a region of the substrate 100 in which the bit line contact 346 is not formed, the cell line spacer 350 may be on the cell insulating film 330. The cell line spacers 350 may be on sidewalls of each of the cell line 340 and the cell line capping film 344.
The cell line spacers 350 may be a single layer film. However, as shown, the cell line spacers 350 may be embodied as a stack of multi-layered films including the first to fourth cell line spacers 351, 352, 353 and 354. In an implementation, each of the first to fourth cell line spacers 351, 352, 353 and 354 may include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN) or air.
In an implementation, the second cell line spacer 352 may not be on the cell insulating film 330, but may be on a sidewall of the bit line contact 346. The fourth cell line spacer 354 may extend along sidewalls of the cell conductive line 340 adjacent thereto and an upper surface of the gate capping pattern while on an upper surface of the gate structure. In an implementation, the second cell line spacer 352 may not be on the cell insulating film 330, but may be on a sidewall of the bit line contact 346.
Buried contacts 320 may be between adjacent bit lines. In an implementation, the buried contact 320 may be between the unit wires 340 adjacent to each other in the first direction DR 1. The buried contact 320 may overlap with the element isolation film 305 at a region of the substrate 100 between adjacent cell wires 340. The buried contact 320 may be connected to the active region.
The buried contact 320 may include, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.
The landing pad 360 may then be on the buried contact 320. The landing pad 360 may then be electrically connected to the buried contact 320. The bond pads 360 may then be connected to the cell active area.
The landing pad 360 may then overlap a portion of the upper surface of the bit line structure 340 ST. The landing pad 360 may comprise, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.
A pad isolation insulating pattern 380 may be on the landing pad 360 and the bit line structure 340 ST. In an implementation, the pad isolation insulating pattern 380 may be on the cell line capping film 344. The pad isolation insulating pattern 380 may define the landing pad 360 as each of a plurality of isolation regions.
The pad isolation insulating pattern 380 may include an insulating material. The pad isolation insulating pattern 380 may electrically insulate the plurality of landing pads 360 from each other. In an implementation, the pad isolation insulating pattern 380 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbonitride film, or a silicon carbonitride film.
The off-chip wire 440 may be located at the same height as the unit wire 340. As used herein, "at the same height" means formed in the same manufacturing process. In an implementation, the stacked structure of the off-chip wires 440 may be the same as that of the unit wires 340.
In an implementation, the off-chip wire 440 may include a first electrode 441, a second electrode 442, a third electrode 443, and an off-chip wire capping film 444. The first electrode 441, the second electrode 442, the third electrode 443, and the chip external line cover film 444 may be sequentially stacked in the second direction DR 2. The first electrode 441 may be located at the same height as the first cell conductive film 341. The second electrode 442 may be located at the same height as the second unit conductive film 342. The third electrode 443 may be located at the same height as the third unit conductive film 343. The chip outside line capping film 444 may be located at the same height as the unit line capping film 344.
The vertical height of the first electrode 441 in the second direction DR2 may be the same as the vertical height of the first unit conductive film 341 in the second direction DR 2. The vertical height of the second electrode 442 in the second direction DR2 may be the same as the vertical height of the second unit conductive film 342 in the second direction D2. The vertical height of the third electrode 443 in the second direction DR2 may be the same as the vertical height of the third unit conductive film 343 in the second direction DR 2. The vertical height of the chip external line cover film 444 in the second direction DR2 may be the same as the vertical height of the unit line cover film 344 in the second direction DR 2.
The interlayer insulating film 480 may be located at the same height as the pad isolation insulating pattern 380. Referring to fig. 56, a third mask layer 240 may be placed across the chip area CA and the off-chip area OCA.
The third mask layer 240 may cover the second mask layer 230. The third mask layer 240 may include photoresist. The third mask layer 240 may include a pattern for etching the first molding layer MD1 in the chip area CA. The pattern of the third mask layer 240 may expose a portion of the upper surface of the second mask layer 230 in the chip area CA.
The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
Whether the third mask layer 240 is properly aligned may be determined based on a result of detecting a polarization state and diffraction of light irradiated to the first step key K1 through the transparent layer 220 overlapped with the first step key K1. In an implementation, the first step key K1 may be used to determine whether a hole formed by etching the first molding layer MD1 using the third mask layer 240 is connected to the landing pad 360.
Referring to fig. 57, the first molding layer MD1 may be etched using the third mask layer 240. Using the pattern of the third mask layer 240, the lower electrode hole H150 may be formed in the first molding layer MD1, the first mask layer 210, and the second mask layer 230. The lower electrode hole H150 may extend through the first molding layer MD1 and the etch stop film 130. The lower electrode hole H150 may expose the bonding pad 360.
Referring to fig. 58, the second mask layer 230 and the third mask layer 240 may be removed, and the lower electrode 150 may be formed. The lower electrode 150 may be in a lower electrode hole (H150 in fig. 57). The lower electrode 150 may fill the lower electrode hole (H150 in fig. 57). The upper surface of the lower electrode 150 may be coplanar with the upper surface of the first mask layer 210. The lower electrode 150 may be connected to the landing pad 360. The lower electrode 150 may contact the bonding pad 360.
The lower electrode 150 may include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (such as iridium oxide or niobium oxide). In the semiconductor device according to some embodiments, the lower electrode 150 may include titanium nitride (TiN). Further, in the semiconductor device according to some embodiments, the lower electrode 150 may include niobium nitride (NbN).
Referring to fig. 59, the first mask layer 210 may be removed. In the chip area CA and the off-chip area OCA, the first molding layer MD1 may be exposed. A portion of each of the third pre-support film 143P and the lower electrode 150 may be exposed in the chip area CA. A portion of the sidewall of the lower electrode 150 surrounded by the first mask layer 210 may be exposed. In the off-chip area OCA, the third pre-support film 143P and the transparent layer 220 may be exposed. The transparent layer 220 may protrude from the top surface of the first molding layer MD1 in the off-chip area OCA.
Referring to fig. 60, a second molding layer MD2 and a protective film 260 may be formed. The second molding layer MD2 may be between the lower electrodes 150 in the chip area CA. The protective film 260 may span the chip area CA and the off-chip area OCA. The protective film 260 may extend along the outline of the second molding layer MD2, the lower electrode 150, and the transparent layer 220.
Referring to fig. 61, the first molding layer MD1 may be patterned. The first molding layer MD1 may be patterned in the chip area CA to form the first, second and third support films 141, 142 and 143. The first mold film 111, the first pre-support film (141P of fig. 60), the second mold film 112, the second pre-support film (142P of fig. 60), the third mold film 113, and the third pre-support film (143P of fig. 60) may be partially removed. The first, second and third support films 141, 142 and 143 may connect adjacent lower electrodes 150 to each other. Each of the first, second and third support films 141, 142 and 143 may contact a portion of a sidewall of the lower electrode 150.
Referring to fig. 62, the first mold film 111, the second mold film 112, the third mold film 113, and the second mold layer MD2 may be removed. The first, second, third and second molding films 111, 112, 113 and MD2 may be removed by regions in which each of the first, second and third support films 141, 142 and 143 is not in contact with the lower electrode 150.
The transparent layer 220 may have an etching selectivity with respect to each of the first mold film 111, the second mold film 112, the third mold film 113, and the second mold layer MD 2. In an implementation, when each of the first, second, third and second molding films 111, 112, 113 and MD2 includes silicon oxide, the transparent layer 220 may include hafnium oxide (HfO 2 ) Titanium oxide (TiO) 2 ) Or tantalum oxide (TaO) 2 ). Therefore, even when the first mold film 111, the second mold film 112, the third mold film 113, and the second mold layer MD2 are removed, the transparent layer 220 may not be removed.
Referring to fig. 63, a capacitor dielectric film 170 may be formed. The capacitor dielectric film 170 may extend along the etch stop film 130, the first support film 141, the second support film 142, the third support film 143, and the protective film 260. The capacitor dielectric film 170 may extend along sidewalls of the lower electrode 150. The capacitor dielectric film 170 may cover the protective film 260.
The capacitor dielectric film 170 may include, for example, one selected from silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.
The capacitor dielectric film 170 is shown as a single layer film. In the semiconductor device according to some embodiments, the capacitor dielectric film 170 may have a stacked structure of ferroelectric material films and paraelectric material films.
The ferroelectric material film may have ferroelectric characteristics. The thickness of the ferroelectric material film may be designed to have ferroelectric characteristics. The thickness range of the ferroelectric material film having ferroelectric characteristics may vary according to the type of ferroelectric material.
In an implementation, the ferroelectric material film may include a single metal oxide. The ferroelectric material film may include a single metal oxide film. In this regard, the single metal oxide may be a binary compound composed of one metal and oxygen. The ferroelectric material film including the single metal oxide may have an orthorhombic crystal system.
In one example, the metal included in the single metal oxide film may be hafnium (Hf). The single metal oxide film may be a hafnium oxide film (HfO). In this regard, the hafnium oxide may have a chemical formula that satisfies the stoichiometry, or may have a chemical formula that does not satisfy the stoichiometry.
In another example, the metal included in the single metal oxide film may be one of rare earth metals belonging to the lanthanoid series. The single metal oxide film may be made of an oxide of a rare earth metal belonging to the lanthanoid series. In this regard, the oxide of the rare earth metal belonging to the lanthanoid may have a chemical formula that satisfies the stoichiometry, or may have a chemical formula that does not satisfy the stoichiometry.
The ferroelectric material film may further contain a dopant doped in the single metal oxide film. The doping concentration may vary depending on the type of dopant, and the doping concentration of the dopant contained in the ferroelectric material film may be 10% or less.
In one example, when the single metal oxide film is a hafnium oxide film, the dopant may include at least one selected from gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), strontium (Sr), or niobium (Nb). In another example, when the single metal oxide film is made of an oxide of a rare earth metal belonging to the lanthanoid series, the dopant may include silicon (Si), aluminum (Al), hafnium (Hf), zirconium (Zr), or niobium (Nb).
In another example, the ferroelectric material film may not contain a dopant doped in the single metal oxide film. When the ferroelectric material film includes a single metal oxide film, the ferroelectric material film may have a thickness in the range of 1nm to 10nm, for example.
In an implementation, the ferroelectric material film may include a bimetal oxide. The ferroelectric material film may include a bimetal oxide film. In this regard, the bimetallic oxide may be a ternary compound composed of two metals and oxygen. The ferroelectric material film including the bimetal oxide may have an orthorhombic crystal system.
The metal included in the bimetal oxide film may be, for example, hafnium (Hf) and zirconium (Zr). The bimetal oxide film may be a hafnium zirconium oxide film (Hf x Zr (1-x) O). In the bi-metal oxide film, x may be in the range of 0.2 to 0.8, including 0.2 and 0.8. In this regard, hafnium zirconium oxide film (Hf x Zr (1-x) O) may have a chemical formula that satisfies the stoichiometry, or may have a chemical formula that does not satisfy the stoichiometry.
In one example, the ferroelectric material film may further include a dopant doped into the bimetal oxide film. The dopant may include gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), or strontium (Sr). In another example, the ferroelectric material film may not include a dopant doped in the bimetal oxide film. When the ferroelectric material film includes a bimetal oxide film, the ferroelectric material film 132 may have a thickness in the range of 1nm to 20nm (including 1nm and 20 nm), for example.
In an implementation, the paraelectric material film may be a dielectric film including zirconium (Zr) or a stacked film including zirconium (Zr). When the chemical formula of the dielectric material is not changed, the dielectric material may exhibit ferroelectric or paraelectric properties depending on the crystal structure of the dielectric material.
Within a certain range, paraelectric materials may have a positive dielectric constant, while ferroelectric materials may have a negative dielectric constant. That is, the paraelectric material may have a positive capacitance, while the ferroelectric material may have a negative capacitance.
In general, when two or more capacitors having positive capacitance are connected in series with each other, the total capacitance thereof decreases. However, when a negative capacitor having a negative capacitance and a positive capacitor having a positive capacitance are connected in series with each other, the total capacitance thereof increases.
In fig. 63, the capacitor dielectric film 170 is shown on the protective film 260. In an implementation, the protective film 260 may be removed before forming the capacitor dielectric film 170, and the capacitor dielectric film 170 may be on the lower electrode 150. In this case, the capacitor dielectric film 170 may extend along the upper surface and the sidewalls of the lower electrode 150.
Referring to fig. 64, an upper electrode 190 may be formed. The upper electrode 190 may be on the lower electrode 150 and the capacitor dielectric film 170. The upper electrode 190 may cover the capacitor dielectric film 170. The upper electrode 190 may cover the transparent layer 220 in the off-chip region OCA.
The upper electrode 190 may be made of, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, or tantalum), a conductive metal oxide (such as iridium oxide, or niobium oxide). In a semiconductor device according to some embodiments, the upper electrode 190 may include titanium nitride (TiN). Alternatively, in a semiconductor device according to some embodiments, the upper electrode 190 may include niobium nitride (NbN).
A semiconductor device according to some embodiments may include a gate structure. The gate structure may be in the substrate 100 and the element isolation film 305. The gate structure may extend through the element isolation film 305 and the active region defined by the element isolation film 305. The gate structure may include a gate trench, a gate insulating film, a gate electrode, a gate capping pattern, and a gate capping conductive film in the substrate 100 and the element isolation film 305. In this regard, the gate electrode may correspond to a word line. Unlike what is shown, the gate structure may not include a gate capping conductive film.
The gate insulating film may extend along sidewalls and bottom surfaces of the gate trench. The gate insulating film may extend along a contour of at least a portion of the gate trench.
The gate insulating film may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.
The gate electrode may be on the gate insulating film. The gate electrode may fill a portion of the gate trench. The gate capping conductive film may extend along an upper surface of the gate electrode.
The gate electrode may comprise a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride or a conductive metal oxide. The gate electrode may comprise, for example, tiN, taC, taN, tiSiN, taSiN, taTiN, tiAlN, taAlN, WN, ru, tiAl, tiAlC-N, tiAlC, tiC, taCN, W, al, cu, co, ti, ta, ni, pt, ni-Pt, nb, nbN, nbC, mo, moN, moC, WC, rh, pd, ir, ag, au, zn, V, ruTiN, tiSi, taSi, niSi, coSi, irOx or RuOx. The gate capping conductive film may comprise, for example, polysilicon or polysilicon germanium.
The gate capping pattern may be on the gate electrode and the gate capping conductive film. The gate capping pattern may fill a portion of the gate trench remaining after the gate electrode and the gate capping conductive film fill a portion of the gate trench. The gate insulating film is shown as extending along sidewalls of the gate capping pattern. The gate capping pattern may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO) 2 ) Silicon carbonitride (SiCN) or silicon oxynitride (SiOCN). The impurity doped region may be on at least one side of the gate structure. The impurity doped region may be a transistorSource/drain regions of (a).
Fig. 65 to 70 are diagrams illustrating a semiconductor device manufactured using a method for manufacturing a semiconductor device according to example embodiments. For convenience of description, differences from the description made with reference to fig. 1 to 12 will be mainly described. Referring to fig. 65, a substrate 100 including a chip area CA and an off-chip area OCA may be formed.
The first molding layer MD1 and the first pre-mask layer 210P may be formed across the chip area CA and the off-chip area OCA. The first molding layer MD1 may include the first molding sacrificial film 112 and the first molding insulating film 110 alternately stacked on top of each other. Each of the first molding sacrificial film 112 and the first molding insulating film 110 in the chip area CA may be located at the same height as each of the first molding sacrificial film 112 and the first molding insulating film 110 in the off-chip area OCA. The first molding layer MD1 may correspond to the first molding layer MD1 of fig. 1 to 54.
The first pre-mask layer 210P may include a metal material. In an implementation, the first pre-mask layer 210P may include a material doped with a metal. In some embodiments, the first pre-mask layer 210P may include aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), lanthanum (La), or alloys thereof. The first pre-mask layer 210P may be opaque. The first pre-mask layer 210P may have a higher etching selectivity with respect to the first molding layer MD1.
In the chip area CA, the first molding layer MD1 may have a stepped structure. The first interlayer insulating film 115 may be on the first molding layer MD1 having a stepped structure in the chip area CA.
The first molding sacrificial film 112 may include a material having etching selectivity with respect to the first molding insulating film 110. In an implementation, the first molding insulating film 110 may include silicon oxide, and the first molding sacrificial film 112 may include silicon nitride.
In some embodiments, the source sacrificial films 102p and 103 and the second source layer 104 may be on the substrate 100 before stacking the first molding sacrificial film 112 and the first molding insulating film 110. The source sacrificial films 102p and 103 may include a material having etching selectivity with respect to the first mold insulating film 110. In an implementation, the first molding insulating film 110 may include silicon oxide, and the source sacrificial films 102p and 103 may include silicon nitride. The second source layer 104 may include polysilicon doped with impurities or polysilicon free of impurities.
In some embodiments, the substrate 100 may be stacked on the peripheral circuit board 120. In an implementation, the peripheral circuit element PT, the second wiring structure 160, and the second inter-wiring insulating film 140 may be on the peripheral circuit board 120. The substrate 100 may be stacked on the second inter-wiring insulating film 140.
The first step key K1 may be in the off-chip area OCA on the substrate 100 and the peripheral circuit board 120. The first step key K1 may include a groove recessed toward the lower surface of the peripheral circuit board 120. In an implementation, the first step key K1 may have a step downward from the upper surface of the substrate 100.
In the chip area CA, the first pre-mask layer 210P may be on the first molding layer MD1 and the first interlayer insulating film 115. In the off-chip region OCA, the first pre-mask layer 210P may be on the first molding layer MD 1.
Referring to fig. 66, a key hole H1 may be in the first mask layer 210. The keyhole H1 may extend through the first mask layer 210. The key hole H1 may overlap the first step key K1. The keyhole H1 may expose an upper surface of the first molding layer MD 1. The keyhole H1 may expose a curved surface of the first molding layer MD 1.
Referring to fig. 67, a transparent layer 220 may be in the first mask layer 210. The upper surface of the transparent layer 220 may be coplanar with the upper surface of the first mask layer 210. The transparent layer 220 may fill the key holes (H1 of fig. 3) in the first mask layer 210. The transparent layer 220 may overlap the first step key K1.
The transparent layer 220 may be surrounded by the first mask layer 210. The sidewalls of the transparent layer 220 may be covered with the first mask layer 210. The first width of the transparent layer 220 may be greater than or equal to the second width of the first step key K1.
In fig. 67, an upper surface of the transparent layer 220 may be coplanar with an upper surface of the first mask layer 210. In an implementation, the upper surface of the transparent layer 220 may be below the upper surface of the first mask layer 210.
Referring to fig. 68, the second mask layer 230 and the third mask layer 240 may span the chip area CA and the off-chip area OCA. The third mask layer 240 may cover the second mask layer 230. The third mask layer 240 may include photoresist. The third mask layer 240 may include a pattern for etching the first molding layer MD1 in the chip area CA. The pattern of the third mask layer 240 may expose a portion of the upper surface of the second mask layer 230 in the chip area CA.
The third mask layer 240 may be aligned using the first step key K1. The first step key K1 may be used to determine whether a pattern of the third mask layer 240 for etching the first molding layer MD1 is covered on the target position.
Whether the third mask layer 240 is properly aligned may be determined based on a result of detecting a polarization state and diffraction of light irradiated to the first step key K1 through the transparent layer 220 overlapped with the first step key K1. In an implementation, the first step key K1 may be used to determine whether a channel hole formed by etching the first molding layer MD1 using the third mask layer 240 is disposed at an appropriate position.
Referring to fig. 69, the first molding layer MD1 may be etched using the third mask layer 240. Using the pattern of the third mask layer 240, channel holes H450 and contact holes H550 may be formed in the first molding layer MD1, the first mask layer 210 and the second mask layer 230.
The channel hole H450 may extend through the first molding layer MD1, the source sacrificial film 102p, and the second source layer 104. The contact hole H550 may extend through the first interlayer insulating film 115, the source sacrificial film 103, and the second source layer 104.
Referring to fig. 70, the second mask layer 230 and the third mask layer 240 may be removed, and a channel structure 450 and a cell contact 550 may be formed. The channel structure 450 may be in a channel hole (H450 in fig. 69). The channel structure 450 may fill the channel hole (H450 in fig. 69). The channel structure 450 may extend through the first molding layer MD1.
Channel structure 450 is shown in fig. 70 as being embodied as a single layer film. In an implementation, the channel structure 450 may be composed of a stack of multi-layered films including a semiconductor pattern and an information storage film.
The semiconductor pattern of the channel structure 450 may extend through the first molding layer MD1 in the third direction Z. The semiconductor pattern of the channel structure 450 may have each of various shapes such as a cylinder shape, a square column shape, and a solid column shape. The semiconductor pattern of channel structure 450 may include a semiconductor material such as monocrystalline silicon, polycrystalline silicon, an organic semiconductor, or a carbon nanostructure.
An information storage film of the channel structure 450 may be between the semiconductor pattern and each gate electrode. In an implementation, the information storage film of the channel structure 450 may extend along an outer side surface of the semiconductor pattern. The information storage film of channel structure 450 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, hafnium lanthanum oxide, lanthanum aluminum oxide, or dysprosium scandium oxide.
In some embodiments, the information storage film of the channel structure 450 may be composed of a stack of multi-layered films. In an implementation, the information storage film of the channel structure 450 may include a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially stacked on an outer side surface of the semiconductor pattern of the channel structure 450.
The tunnel insulating film of the channel structure 450 may include, for example, silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include aluminum oxide (Al 2 O 3 ) Or hafnium oxide (HfO) 2 ). The charge storage layer of channel structure 450 may comprise, for example, silicon nitride. The blocking insulating film of the channel structure 450 may include, for example, silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include aluminum oxide (Al 2 O 3 ) Or hafnium oxide (HfO) 2 )。
In some embodiments, the channel structure 450 may further include a fill pattern. The filling pattern of the channel structure 450 may fill an inner space defined in the cup-shaped semiconductor pattern. The fill pattern of the channel structure 450 may include an insulating material, such as silicon oxide.
The unit contact 550 may be in a contact hole (H550 in fig. 69). The unit contact 550 may fill the contact hole (H550 in fig. 69). The unit contact 550 may extend through the first interlayer insulating film 115.
The cell contact 550 may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon.
After the step shown in fig. 70, the mold sacrificial film 112 may be removed, and a plurality of gate electrodes may be formed. Subsequently, the source sacrificial film 102p may be selectively removed, and a source layer filling a space remaining by removing a portion of the source sacrificial film 102p may be formed.
The gate electrode may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon. The source layer may include a conductive material, such as polysilicon or metal doped with impurities.
By summarizing and reviewing, it becomes increasingly difficult to identify bond patterns for overlay measurements due to the introduction of new materials or complex manufacturing processes. Technical object of the present disclosure is to provide a method for manufacturing a semiconductor device having improved overlay measurement accuracy.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some cases, as will be recognized by one of ordinary skill in the pertinent art after submitting the present application, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in other embodiments, unless explicitly stated otherwise. Thus, it will be understood by those skilled in the art that various changes in form and details may be made.

Claims (20)

1. A method for manufacturing a semiconductor device, the method comprising:
forming a step bond on a substrate;
forming a molding layer covering the step key on the step key;
forming a first mask layer on the molding layer;
forming a transparent layer overlapping the step key in the first mask layer;
Forming a second mask layer on the first mask layer and the transparent layer; and
the second mask layer is used to etch the molding layer,
wherein the first mask layer comprises a metallic material.
2. The method of claim 1, wherein the first mask layer comprises:
a first portion surrounding a side surface of the transparent layer; and
a second portion below the transparent layer.
3. The method of claim 2, wherein the second portion has a second thickness from the upper surface of the molding layer that is less than the first thickness of the transparent layer.
4. The method of claim 2, wherein a first thickness of the first portion from an upper surface of the molding layer is greater than a second thickness of the second portion from the upper surface of the molding layer.
5. The method of claim 1, wherein forming the transparent layer comprises:
forming a keyhole extending through the first mask layer and overlapping the step key; and
the transparent layer is formed in the keyhole.
6. The method of claim 5, wherein the first width of the keyhole is greater than the second width of the step key.
7. The method according to claim 5, wherein:
forming the transparent layer in the keyhole includes forming the transparent layer using chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and
the upper surface of the transparent layer and the upper surface of the first mask layer are coplanar with each other.
8. The method according to claim 5, wherein:
forming the transparent layer in the keyhole includes forming the transparent layer in the keyhole on the molding layer by way of area-selective deposition, and
the transparent layer is not on the surface of the first mask layer, and
an upper surface of the transparent layer is located below an upper surface of the first mask layer based on a lower surface of the substrate.
9. The method of claim 1, wherein the molding layer comprises:
a flat surface area that does not overlap the step key; and
and the curved surface area is overlapped with the step key.
10. The method of claim 1, wherein the molding layer comprises:
a first molding layer comprising silicon nitride; and
and a second molding layer comprising silicon oxide.
11. The method of claim 1, further comprising:
removing the first mask layer after etching the molding layer; and
Forming a protective film covering the transparent layer.
12. The method of claim 1, wherein the transparent layer has a light transmittance that is greater than a light transmittance of the first mask layer.
13. The method of claim 1, wherein the transparent layer comprises hafnium oxide, titanium oxide, tantalum oxide, silicon oxide, or silicon nitride.
14. A method for manufacturing a semiconductor device, the method comprising:
forming a substrate including a chip region and an off-chip region;
forming a step bond on the off-chip region of the substrate;
forming a molding layer covering the step key on the substrate;
forming a first mask layer on the molding layer;
forming a key hole overlapping the step key in the first mask layer;
forming a transparent layer in the key hole;
forming a second mask layer on the first mask layer and the transparent layer while aligning the second mask layer using the step key;
etching the molding layer using the second mask layer to form a pattern hole; and
the pattern holes are filled with a pattern material to form pillar structures.
15. The method of claim 14, wherein the first mask layer comprises a metallic material.
16. The method according to claim 14, wherein:
the keyhole extends through the first mask layer and
the lower surface of the transparent layer is in contact with the molding layer.
17. The method according to claim 14, wherein:
the lower surface of the transparent layer is in contact with the first mask layer, and
the first mask layer includes:
a first portion surrounding a side surface of the transparent layer; and
a second portion below the transparent layer.
18. The method of claim 17, wherein a first thickness of the first portion from an upper surface of the molding layer is greater than a second thickness of the second portion from the upper surface of the molding layer.
19. The method according to claim 14, wherein:
forming the pattern hole includes etching the first mask layer and the molding layer;
forming the pillar structures includes removing the second mask layer and forming the pillar structures in the pattern holes; and is also provided with
The upper surface of the pillar structure is located at a vertical height higher than a vertical height of the lower surface of the first mask layer based on the lower surface of the substrate.
20. A method for manufacturing a semiconductor device, the method comprising:
Forming a substrate including a chip region and an off-chip region;
forming bit lines on the substrate in the chip region extending across the substrate;
forming buried contacts between the bit lines and connected to the chip region of the substrate;
forming a landing pad on the buried contact;
forming a step bond on the substrate in the off-chip region;
forming a molding layer covering the landing pad and the step bond on the chip region and the off-chip region;
forming a first mask layer on the molding layer, wherein the first mask layer comprises a metal material;
forming a key hole overlapping the step key in the first mask layer;
forming a transparent layer in the key hole;
forming a second mask layer on the first mask layer and the transparent layer while aligning the second mask layer using the step key;
etching the molding layer in the chip region using the second mask layer to form a pattern hole;
forming a lower electrode filling the pattern hole; and
a dielectric film and an upper electrode are formed on the lower electrode,
wherein:
The light transmittance of the transparent layer is greater than that of the first mask layer, and
the first vertical height of the upper surface of the lower electrode extends farther in a vertical direction relative to the bottom surface of the substrate than the second vertical height of the upper surface of the molding layer.
CN202311302591.3A 2022-10-11 2023-10-09 Method for manufacturing semiconductor device with improved overlay measurement accuracy Pending CN117877976A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2022-0129820 2022-10-11
KR1020230046764A KR20240050248A (en) 2022-10-11 2023-04-10 Semiconductor device fabricating method
KR10-2023-0046764 2023-04-10

Publications (1)

Publication Number Publication Date
CN117877976A true CN117877976A (en) 2024-04-12

Family

ID=90576093

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311302591.3A Pending CN117877976A (en) 2022-10-11 2023-10-09 Method for manufacturing semiconductor device with improved overlay measurement accuracy

Country Status (1)

Country Link
CN (1) CN117877976A (en)

Similar Documents

Publication Publication Date Title
EP3639300B1 (en) Three-dimensional memory device having a buried source line extending to scribe line and method of making thereof
US10158073B2 (en) Manufacturing method of semiconductor structure
CN109560194B (en) Semiconductor device and method for manufacturing the same
CN108123034B (en) Embedded memory device with composite top electrode
US11482668B2 (en) RRAM structure
CN111785722A (en) Method of manufacturing F-RAM
KR102436169B1 (en) Top electrode via with low contact resistance
TWI788106B (en) Semiconductor device
US11296147B2 (en) Method for manufacturing memory device having spacer
US10978473B2 (en) Flash memory structure and method of forming the same
KR20220059695A (en) Semiconductor memory device and method for fabricating the same
US20090239351A1 (en) Method For Fabricating Capacitor Structures Using The First Contact Metal
CN115602702A (en) Semiconductor memory device with a plurality of memory cells
US11854979B2 (en) Semiconductor device
US20240120199A1 (en) Method for manufacturing semiconductor device
CN117877976A (en) Method for manufacturing semiconductor device with improved overlay measurement accuracy
KR20240050248A (en) Semiconductor device fabricating method
CN114725070A (en) Semiconductor device and method for manufacturing the same
US20230402503A1 (en) Semiconductor device
US20240107751A1 (en) Semiconductor memory device
US20220359823A1 (en) Top electrode via with low contact resistance
US20230017264A1 (en) Semiconductor device and method of forming the same
US20240032294A1 (en) Electronic devices comprising an oxide fill region, and related electronic systems and methods
KR20050079433A (en) Semiconductor devices having a planar metal-insulator-metal capacitor and methods of fabricating the same
TW202320066A (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication