CN117877557A - ZQ calibration circuit, method of operating ZQ calibration circuit, and semiconductor memory device - Google Patents

Abstract

A ZQ calibration circuit, a semiconductor memory device, and a method of operating the ZQ calibration circuit are provided. The ZQ calibration circuit included in the semiconductor memory device includes: a reference voltage selector configured to output a reference voltage selected from a first reference voltage and a second reference voltage generated based on the first power supply voltage and the second power supply voltage in response to a selection signal; a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage; and a loop selector configured to output a selection signal according to whether each of the pull-up code and the pull-down code is switched. The levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

Description

ZQ calibration circuit, method of operating ZQ calibration circuit, and semiconductor memory device

Cross Reference to Related Applications

The present application is based on and claims priority of korean patent application No.10-2022-0130870 filed on 10 month 12 of 2022 and korean patent application No.10-2023-0005528 filed on 13 month 1 of 2023, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a ZQ calibration circuit that performs ZQ calibration using different reference voltages for each cycle, an operating method of the ZQ calibration circuit, and a semiconductor memory device.

Background

Semiconductor memories are widely used to store data in various electronic devices such as computers, wireless communication devices, and the like. In order to access data stored in the semiconductor memory, at least one memory state of the semiconductor memory may be read or detected. To store data, components in the device may write or program the state of the semiconductor memory.

In most cases, the semiconductor memory receives various signals from the outside through an input pad and transmits internal signals to the outside through an output pad. In order to minimize delay time required for signal transmission due to an increased operation speed of the electronic device, a swing width of signals transmitted and received between semiconductor memories has been gradually reduced. However, as the swing width of the signal decreases, the influence of external noise increases, and reflection of the signal by impedance mismatch becomes serious in the interface. When impedance mismatch occurs, it is difficult to transfer data at high speed, and data output from the semiconductor memory may be distorted.

A semiconductor memory requiring high-speed operation employs an impedance matching circuit called an on-chip termination circuit in the vicinity of a pad inside a chip. The impedance matching circuit may match the impedance by performing ZQ calibration. ZQ calibration is a process that produces pull-up and pull-down codes that change as process, voltage, and temperature (PVT) conditions change. The resistance value of the on-chip termination device is adjusted by a code generated as a result of ZQ calibration. Typically, ZQ calibration is performed based on one reference voltage during one cycle. However, in pulse modulation methods such as Pulse Amplitude Modulation (PAM) -3 and PAM-4, there are cases where the impedance of the data driver of the semiconductor memory changes with a change in signal level or voltage. Therefore, it is important to generate pull-up and pull-down codes for accurate matching of impedances.

Disclosure of Invention

The disclosure of the inventive concept provides a ZQ calibration circuit including an additional pull-down circuit compensating for a change in impedance according to a change in a level of a drain-source voltage (e.g., vds) of a transistor, an operating method of the ZQ calibration circuit, and a semiconductor memory device.

According to an aspect of the inventive concept, there is provided a ZQ calibration circuit included in a semiconductor memory device, the ZQ calibration circuit including: a reference voltage selector configured to output a reference voltage selected from a first reference voltage and a second reference voltage generated based on the first power supply voltage and the second power supply voltage in response to a selection signal; a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage; and a loop selector configured to output a selection signal according to whether each of the pull-up code and the pull-down code is switched. The levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

According to another aspect of the inventive concept, there is provided a semiconductor memory device including: a ZQ bonding pad; DQ pads; a ZQ calibration circuit configured to perform a ZQ calibration operation by using a ZQ resistor connected to a ZQ pad and generate a ZQ code; and a DQ driver configured to determine a termination resistance value of the DQ pad based on the ZQ code. The ZQ calibration circuit includes: a reference voltage selector configured to output a reference voltage selected from a first reference voltage and a second reference voltage generated based on the first power supply voltage and the second power supply voltage in response to a selection signal; a ZQ engine configured to generate a pull-up code of a ZQ code and a pull-down code of the ZQ code based on the selected reference voltage; and a loop selector configured to output a selection signal according to whether each of the pull-up code and the pull-down code is switched. The levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

According to another aspect of the inventive concept, there is provided a method of operating a ZQ calibration circuit, the method of operating a ZQ calibration circuit comprising: generating a first reference voltage and a second reference voltage based on the first power supply voltage and the second power supply voltage; selecting a reference voltage from the first reference voltage and the second reference voltage according to the selection signal; generating a pull-up code and a pull-down code based on the selected reference voltage; and generating a selection signal according to whether each of the pull-up code and the pull-down code is switched. The levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

Drawings

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which

In the accompanying drawings:

fig. 1 is a diagram illustrating a semiconductor memory device according to some embodiments;

FIG. 2 is a diagram illustrating a ZQ calibration circuit according to some embodiments;

FIG. 3 is a circuit diagram illustrating a ZQ engine according to some embodiments;

FIG. 4 is a diagram illustrating DQ drivers according to some embodiments;

FIGS. 5A and 5B are diagrams illustrating a ZQ engine and DQ driver, respectively, supplied with a first reference voltage of the inventive concepts, according to some embodiments;

FIGS. 6A and 6B are diagrams illustrating a ZQ engine and DQ driver, respectively, supplied with a second reference voltage of the inventive concepts, according to some embodiments;

FIG. 7 is a flow chart illustrating a method of operation of a ZQ calibration circuit according to some embodiments;

and

Fig. 8 is a block diagram illustrating an electronic system according to some embodiments.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 is a diagram illustrating a semiconductor memory device according to some embodiments.

The semiconductor memory device 100 may be implemented as a volatile memory device. Volatile memory devices may include, for example, dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), mobile DRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, rambus Dynamic Random Access Memory (RDRAM), and the like. However, the semiconductor memory device 100 is not limited thereto, and may be implemented as a nonvolatile memory device in some embodiments.

Semiconductor memory device 100 may include ZQ pad 101 and DQ pad 102.ZQ pad 101 may be a pad for adjusting impedance. The ZQ pad 101 may be connected to a ZQ resistor RZQ existing outside. The power supply voltage VSS may be connected to one end of the ZQ resistor RZQ. DQ pad 102 may be a pad for inputting/outputting data. DQ pad 102 may be connected to a DQ resistor RDQ that exists externally. Supply voltage VDDQ may be connected to one end of DQ resistor RDQ. The level of the power supply voltage VDDQ may be higher than the level of the power supply voltage VSS. In the inventive concept, the power supply voltage VDDQ may be referred to as a first power supply voltage, and the power supply voltage VSS may be referred to as a second power supply voltage. According to an embodiment, the second power supply voltage VSS may be designed to be ground.

Although not shown, the semiconductor memory device 100 may further include command pads and address pads. In the present inventive concept, the term "pad" may refer broadly to an electrical interconnect with an integrated circuit. For example, the term "pad" may include a pin or other electrical contact on an integrated circuit.

Semiconductor memory device 100 may include ZQ calibration circuit 110 and DQ driver 120.

The ZQ calibration circuit 110 may perform a ZQ calibration operation by using the ZQ resistor RZQ connected to the ZQ pad 101 and generate the ZQ code zqode. Specifically, for example, the ZQ calibration circuit 110 may repeatedly perform a calibration operation by using the ZQ resistor RZQ and generate a ZQ code zqode converging n bits, n may be an integer greater than or equal to 1. ZQ calibration circuit 110 may provide ZQ code zqode to DQ driver 120.

DQ driver 120 may determine the termination resistance value of DQ pad 102 based on the ZQ code ZQCODE.

Fig. 2 is a diagram illustrating a ZQ calibration circuit in accordance with some embodiments.

Referring to fig. 2, the zq calibration circuit 200 may be a circuit that compensates for a change in impedance according to voltage levels in Pulse Amplitude Modulation (PAM) -3 and PAM-4. The ZQ calibration circuit 200 may include a reference voltage selector 210, a ZQ engine 220, and a loop selector 230.

The reference voltage selector 210 may output a reference voltage selected from the first and second reference voltages VREFZQ1 and VREFZQ2 generated from the first and second power voltages VDDQ and VSS according to the selection signal SEL. The reference voltage selector 210 may generate the first reference voltage VREFZQ1 and/or the second reference voltage VREFZQ2 based on the first power supply voltage VDDQ and the second power supply voltage VSS. In addition, the reference voltage selector 210 may output the first reference voltage VREFZQ1 or the second reference voltage VREFZQ2 according to the selection signal SEL (e.g., a logic level of the selection signal SEL). For example, the reference voltage selector 210 may output the first reference voltage VREFZQ1 when the selection signal SEL from the cyclic selector 230 has a first logic level, and output the second reference voltage VREFZQ2 when the selection signal SEL from the cyclic selector 230 has a second logic level different from the first logic level.

The ZQ calibration circuit 200 may perform ZQ calibration operations during a first cycle and during a second cycle after the first cycle. In some embodiments, the reference voltage selector 210 may provide the first reference voltage VREFZQ1 among the first reference voltage VREFZQ1 and the second reference voltage VREFZQ2 to the ZQ engine 220 during the first cycle. Further, the reference voltage selector 210 may provide the second reference voltage VREFZQ2 among the first reference voltage VREFZQ1 and the second reference voltage VREFZQ2 to the ZQ engine 220 during the second cycle.

In a first cycle, a first reference voltage VREFZQ1 may be applied to the ZQ engine 220 to perform ZQ calibration. During the first cycle, the termination resistance value of the DQ pad 102 of fig. 1 may be determined as a first resistance value, and the level of the voltage generated on the DQ pad 102 may be a first level. In a second cycle, a second reference voltage VREFZQ2 may be applied to the ZQ engine 220 to perform ZQ calibration. During the second cycle, the termination resistance value of the DQ pad 102 of fig. 1 may be determined as a second resistance value, and the level of the voltage generated on the DQ pad 102 may be a second level.

In some embodiments, the level of the first reference voltage VREFZQ1 may be higher than the level of the second reference voltage VREFZQ2 and lower than the level of the first power supply voltage VDDQ. The level of the second reference voltage VREFZQ2 may be higher than the level of the second power supply voltage VSS. Specifically, for example, when ZQ calibration circuit 200 is included in GDDR7, which may be driven with PAM-3, the voltage of PAM-3 in GDDR7 may be 3/4VDDQ and/or 1/2VDDQ. Thus, the first reference voltage VREFZQ1 may be 3/4VDDQ and the second reference voltage VREFZQ2 may be 1/2VDDQ. However, the embodiment is not limited thereto.

The ZQ engine 220 may receive the first power supply voltage VDDQ and the second power supply voltage VSS. The ZQ engine 220 may be connected between a line to which the first power voltage VDDQ is applied and the ZQ pad 201. The ZQ pad 201 may be connected to a ZQ resistor RZQ. One end of the ZQ resistor RZQ may be connected to a line to which the second power supply voltage VSS is applied.

The ZQ engine 220 may output a ZQ code (e.g., ZQ code zqode of fig. 1) based on the selected reference voltage. Specifically, ZQ engine 220 may perform ZQ calibration based on a selected reference voltage (e.g., first reference voltage VREFZQ1 or second reference voltage VREFZQ 2) to generate a pull-up code PUCODE < 0 for the ZQ code: n > and the pull-down code PDCODE < 0: n >. The pull-up code PUCODE < 0 generated as a result of performing ZQ calibration: n > and the pull-down code PDCODE < 0: n > is provided to a DQ driver (e.g., DQ driver 120 of FIG. 1) and determines the termination resistance value of DQ pad 102. Furthermore, the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: n > may be provided to the loop selector 230.

The loop selector 230 may be configured to select the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: each of N > switches to output the selection signal SEL. In some embodiments, when the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: when two of N > are switched, the cycle selector 230 may output a select signal SEL informing the end of the cycle in the ZQ engine 220. When the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: when none of N > is switched, the loop selector 230 may not output the selection signal SEL. In some embodiments, when the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: when two of N > are switched, a selection signal SEL having a first logic level may be output. For example, when the pull-up code PUCODE < 0: one bit in N > and the pull-down code PDCODE < 0: when one bit of N > is switched, the loop selector 230 may output the selection signal SEL having a logic high level "H". When the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: when any one of N > is not switched, a selection signal SEL having a second logic level different from the first logic level may be output. For example, when the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: when any one bit of each of N > is not switched, the loop selector 230 may output the selection signal SEL having a logic low level "L".

As described above, in pulse amplitude modulation methods such as PAM-3 and PAM-4, the level separation mismatch Ratio (RLM) can be improved.

Fig. 3 is a circuit diagram illustrating a ZQ engine in accordance with some embodiments.

Referring to fig. 3, the zq engine 300 may configure a structure of a loop corresponding to each level of signals in methods such as PAM-3 and PAM-4. The ZQ engine 300 may include a first pull-up circuit 310, a second pull-up circuit 320, a first pull-down circuit 330, a second pull-down circuit 340, a first comparator (COMP 1) 350, a first counter (CNT 1) 360, a second comparator (COMP 2) 370, a second counter (CNT 2) 380, and a third counter (CNT 3) 390.

The first pull-up circuit 310 may be connected between the first node N1 and the second node N2. For example, the terms "connected" and/or "coupled" may mean that two or more elements are in direct physical or electrical contact with each other. The terms "connected" and/or "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The first pull-up circuit 310 may be referred to as a first pull-up replica.

The first power supply voltage VDDQ may be applied or supplied to the first node N1.ZQ pad 301 may be connected to a second node N2. The first pull-up circuit 310 may be connected to the ZQ pad 301 through the second node N2.

The first pull-up circuit 310 may receive a pull-up code PUCODE < 0: n > to adjust the resistance of the first pull-up circuit 310. In some embodiments, the first pull-up circuit 310 includes one or more first transistors TR1 and one or more first resistors R1 connected in series between the first node N1 and the second node N2.

The first transistor TR1 may include a first electrode connected to the first node N1, a second electrode connected to the first resistor R1, and a reception pull-up code PUCODE < 0: n > gate electrode. The first transistor TR1 may be implemented as a p-type transistor (or PMOS transistor). A gate of the first transistor TR1 may be connected to the seventh node N7. The pull-up code PUCODE < 0: a specific bit in N > may be input to the gate of the first transistor TR1 corresponding thereto. The first transistor TR1 may be according to the pull-up code PUCODE < 0: the bit value of N > is turned on or off.

The first resistor R1 may be connected between the second electrode of the first transistor TR1 and the second node N2.

The number of each of the first transistor TR1 and the first resistor R1 may be equal to the pull-up code PUCODE < 0: the number of N > digits (bit digit) corresponds to the number of bits. In some embodiments, code PUCODE < 0 may be according to phase Guan Shangla: the binary weight of N > differently sets the size ratio of the first transistor TR1 and/or the resistance value ratio of the first resistor R1.

The second pull-up circuit 320 may be connected between the third node N3 and the fourth node N4. The first power supply voltage VDDQ may be supplied to the third node N3. Herein, the first node N1 and the third node N3 may be connected to each other. An input terminal of the second comparator 370 may be connected to the fourth node N4. The second pull-up circuit 320 may be referred to as a second pull-up replica.

The second pull-up circuit 320 may receive the pull-up code PUCODE < 0: n > to adjust the resistance of the second pull-up circuit 320. In some embodiments, the second pull-up circuit 320 may include one or more second transistors TR2 and one or more second resistors R2 connected in series between the third node N3 and the fourth node N4. The second transistor TR2 may be implemented as a p-type transistor (or PMOS transistor).

The second transistor TR2 may include a first electrode connected to the third node N3, a second electrode connected to the second resistor R2, and a reception pull-up code PUCODE < 0: n > gate electrode. A gate of the second transistor TR2 may be connected to the seventh node N7. Each second transistor TR2 may be controlled according to a pull-up code PUCODE < 0 corresponding thereto: the bit value of N > is turned on or off. The second transistor TR2 may be implemented as a p-type transistor (or PMOS transistor).

The second resistor R2 may be connected between the second electrode of the second transistor TR2 and the fourth node N4.

The number of each of the second transistors TR2 and the second resistors R2 may be equal to the pull-up code PUCODE < 0: the number of digits of N > corresponds to the number of digits of N.

The first pull-down circuit 330 may be connected between the fourth node N4 and the fifth node N5. The second power supply voltage VSS may be supplied to the fifth node N5. The first pull-down circuit 330 may be referred to as a first pull-down replica.

The first pull-down circuit 330 may receive a first pull-down code PDCODE1 < 0: n > to adjust the resistance of the first pull-down circuit 330. In some embodiments, the first pull-down circuit 330 may include one or more third resistors R3 and one or more third transistors TR3 connected in series between the fourth node N4 and the fifth node N5.

The third resistor R3 may be connected to the fourth node N4 and the first electrode of the third transistor TR3.

The third transistor TR3 may include a first electrode connected to the third resistor R3, a second electrode connected to the fifth node N5, and receive the first pull-down code PDCODE1 < 0: n > gate electrode. Each third transistor TR3 may be according to the first pull-down code PDCODE1 < 0 corresponding thereto: the bit value of N > is turned on or off. The third transistor TR3 may be implemented as an n-type transistor (or an NMOS transistor).

The number of each of the third resistor R3 and the third transistor TR3 may be equal to the first pull-down code PDCODE1 < 0: the number of digits of N > corresponds to the number of digits of N.

The second pull-down circuit 340 may be connected between the fourth node N4 and the sixth node N6. The second power supply voltage VSS may be supplied to the sixth node N6. The second pull-down circuit 340 may be referred to as a second pull-down replica.

The second pull-down circuit 340 may receive the second pull-down code PDCODE2 < 0: n > to adjust the resistance of the second pull-down circuit 340. In some embodiments, the second pull-down circuit 340 may include one or more fourth resistors R4 and one or more fourth transistors TR4 connected in series between the fourth node N4 and the sixth node N6.

The fourth resistor R4 may be connected to the fourth node N4 and the first electrode of the fourth transistor TR4.

The fourth transistor TR4 may include a first electrode connected to the fourth resistor R4, a second electrode connected to the sixth node N6, and receive the second pull-down code PDCODE2 < 0: n > gate electrode. Each fourth transistor TR4 may be according to the second pull-down code PDCODE2 < 0 corresponding thereto: the bit value of N > is turned on or off. The fourth transistor TR4 may be implemented as an n-type transistor (or an NMOS transistor).

The number of each of the fourth resistor R4 and the fourth transistor TR4 may be equal to the second pull-down code PDCODE2 < 0: the number of digits of N > corresponds to the number of digits of N.

The first comparator 350 may include a first input terminal connected to the ZQ pad 301, a second input terminal to which the reference voltage VREFZQ is input, and an output terminal to which the first comparison output signal CMPO1 is output. The first comparator 350 may output a first comparison output signal CMPO1 based on the voltage generated on the ZQ pad 301 and the reference voltage VREFZQ. For example, the first comparator 350 may compare the level of the voltage generated on the ZQ pad 301 with the level of the reference voltage VREFZQ to output the first comparison output signal CMPO1 of a logic high level or a logic low level (or up/down).

The first counter 360 may receive the first comparison output signal CMPO1 and generate a pull-up code PUCODE < 0: n >. The pull-up code PUCODE < 0: n > may be output to the seventh node N7. The pull-up code PUCODE < 0: n > may be a signal for turning on or off a transistor connected in parallel in each of the first pull-up circuit 310 and the second pull-up circuit 320. The pull-up code PUCODE < 0: n > is provided to the first pull-up circuit 310 and the second pull-up circuit 320, and thus, each of the first pull-up circuit 310 and the second pull-up circuit 320 may adjust its resistance value. The resistance value of the first pull-up circuit 310 affects the voltage of the ZQ pad 301, and the above operation is repeated.

The second comparator 370 may include a first input terminal to which the reference voltage VREFZQ is input, a second input terminal connected to the fourth node N4, and an output terminal outputting the second comparison output signal CMPO2. The second comparator 370 may compare the level of the voltage generated on the fourth node N4 with the level of the reference voltage VREFZQ to output the second comparison output signal CMPO2 of a logic high level or a logic low level.

The second counter 380 may receive the second comparison output signal CMPO2 and generate a first pull-down code PDCODE1 < 0: n >. The first pull-down code PDCODE1 < 0: n > may be a signal for turning on or off each transistor connected in parallel in the first pull-down circuit 330. The first pull-down code PDCODE1 < 0: n > is provided to the first pull-down circuit 330, and thus, the first pull-down circuit 330 may adjust its resistance value.

The third counter 390 may receive the second comparison output signal CMPO2 and generate a second pull-down code PDCODE2 < 0: n >. The second pull-down code PDCODE2 < 0: n > may be a signal for turning on or off each transistor connected in parallel in the second pull-down circuit 340.

As described above, an additional pull-down circuit is designed to compensate for the variation of the impedance according to the level variation of the drain-source voltage (e.g., vds) of the transistor, and thus, RLM can be improved in pulse amplitude modulation methods such as PAM-3 and PAM-4.

As described above, the final ZQ code compensating for a part of the impedance variation of the ZQ engine 300 is converted, and thus, impedance matching according to the level of PAM-3 is achieved, thereby improving the characteristics of RLM.

Fig. 4 is a diagram illustrating DQ drivers according to some embodiments.

Referring to fig. 3 and 4, dq driver 400 may include a pull-up circuit 410, a first pull-down circuit 420, and a second pull-down circuit 430.

The pull-up circuit 410 may be connected between a line supplied with the first power supply voltage VDDQ and the node N. The pull-up circuit 410 may receive the pull-up code PUCODE < 0: n > to adjust the resistance of pull-up circuit 410. The pull-up circuit 410 may include the first pull-up circuit 310 and/or the second pull-up circuit 320. Pull-up circuit 410 may be referred to as a DQ pull-up circuit.

The first pull-down circuit 420 may be connected between the node N and a line supplied with the second power supply voltage VSS. The first pull-down circuit 420 may receive a first pull-down code PDCODE1 < 0: n > to adjust the resistance of the first pull-down circuit 420. The first pull-down circuit 420 may be referred to as a first DQ pull-down circuit.

The second pull-down circuit 430 may be connected between the node N and a line supplied with the second power supply voltage VSS, and receives the second pull-down code PDCODE2 < 0: n > to adjust the resistance of the second pull-down circuit 430. The second pulldown circuit 430 may be referred to as a second DQ pulldown circuit.

DQ pad 402 may be connected to node N. DQ resistor RDQ may be connected to DQ pad 402. The first power supply voltage VDDQ may be supplied to one end of the DQ resistor RDQ.

Fig. 5A and 5B are diagrams illustrating a ZQ engine and DQ driver supplied with a first reference voltage of the inventive concept according to some embodiments. Specifically, fig. 5A and 5B are diagrams showing the termination resistance value of DQ pad 502 by ZQ calibration performed during the first cycle.

Referring again to fig. 2, the reference voltage selector 210 may provide the first reference voltage VREFZQ1 among the first and second reference voltages VREFZQ1 and VREFZQ2 to the first and second comparators 550a and 570a during the first cycle. In some embodiments, the first reference voltage VREFZQ1 may correspond to 3/4 of the first supply voltage VDDQ in PAM-3.

Referring to fig. 5A, a first reference voltage 3/4VDDQ may be input to the first comparator 550a and the second comparator 570a of the ZQ engine 500 a.

The first comparator 550a may compare the level of the voltage generated on the ZQ pad 501 with the level of the first reference voltage 3/4VDDQ and output the first comparison output signal CMPO1. The first counter 560a may output a pull-up code PUCODE < 0 based on the first comparison output signal CMPO 1: n >. Each of the first pull-up circuit 510a and the second pull-up circuit 520a may be according to the pull-up code PUCODE < 0: n > to adjust its resistance.

The second comparator 570a may compare the level of the voltage generated on the fourth node N4 with the level of the first reference voltage 3/4VDDQ and output the second comparison output signal CMPO2. The second counter 580a may output the first pull-down code PDCODE1 < 0 based on the second comparison output signal CMPO 2: n >. Although not shown, the second counter 580a may receive a selection signal SEL from the loop selector 230 of fig. 2. For example, when the selection signal SEL has a logic low level "L", the second counter 580a may generate the first pull-down code PDCODE1 < 0: n >. The third counter 590a may output the second pull-down code PDCODE2 < 0 based on the second comparison output signal CMPO 2: n >. Although not shown, the third counter 590a may receive a selection signal SEL from the loop selector 230 of fig. 2. For example, when the selection signal SEL has a logic low level "L", the third counter 590a may provide the second pull-down code PDCODE2 < 0: n > to turn off the second pull-down circuit 540a. The first pull-down circuit 530a may receive the first pull-down code PDCODE1 < 0 during the first cycle: n > and set a first resistance value. The second pull-down circuit 540a may receive the second pull-down code PDCODE2 < 0 during the first cycle: n > and is turned off.

In some embodiments, the resistance value of the ZQ resistor RZQ may be 120Ω. At this time, when the first reference voltage 3/4VDDQ is input to the ZQ engine 500a in the first cycle, the resistance value of the first pull-up circuit 510a may be 40Ω, the resistance value of the second pull-up circuit 520a may be 80/3Ω, and the first resistance value of the first pull-down circuit 530a may be 80Ω.

Referring to fig. 5B, a pull-up circuit 510B included in DQ driver 500B may be according to a pull-up code PUCODE < 0 input during the first cycle: n > sets the first resistance value. The first pull-down circuit 520b may be configured to output a first pull-down code PDCODE1 < 0 according to the first pull-down code input during the first cycle: n > sets the first resistance value. The second pull-down circuit 530b may be configured to output a second pull-down code PDCODE2 < 0 according to the second pull-down code PDCODE input during the first cycle: n > is turned off.

In some embodiments, the resistance value of ZQ resistor RZQ may be 120Ω and the resistance value of DQ resistor RDQ may be 40Ω. In this regard, when the first reference voltage 3/4VDDQ is input to the ZQ engine 500a in the first cycle, the first resistance value of each of the pull-up circuit 510b and the first pull-down circuit 520b may be 80 Ω. A voltage having the same level as the level of the first reference voltage 3/4VDDQ may be generated on the DQ pad 502.

As described above, by directly compensating for the impedance variation of the first and second pull-down circuits 530a and 540a within the ZQ engine 500a, an impedance matching code is finally generated, and thus, the characteristics of the RLM can be improved.

Fig. 6A and 6B are diagrams illustrating a ZQ engine and DQ driver supplied with a second reference voltage of the inventive concept according to some embodiments. Specifically, fig. 6A and 6B are diagrams showing the termination resistance value of the DQ pad 502 by ZQ calibration performed during the second cycle.

Referring again to fig. 2, the reference voltage selector 210 may provide the second reference voltage VREFZQ2 among the first and second reference voltages VREFZQ1 and VREFZQ2 to the first and second comparators 650a and 670a during a second cycle after the first cycle. In some embodiments, the first reference voltage VREFZQ1 may correspond to half (1/2) of the first supply voltage VDDQ in PAM-3.

Referring to fig. 6A, the second reference voltage 1/2VDDQ may be input to the first comparator 650a and the second comparator 670a of the ZQ engine 600 a.

The first comparator 650a may compare the level of the voltage generated on the ZQ pad 601 with the level of the second reference voltage 1/2VDDQ and output the first comparison output signal CMPO1. The first counter 660a may output a pull-up code PUCODE < 0 based on the first comparison output signal CMPO 1: n >. Each of the first pull-up circuit 610a and the second pull-up circuit 620a may be according to a pull-up code PUCODE < 0: n > adjusts its resistance value.

The second comparator 670a may compare the level of the voltage generated at the fourth node N4 with the level of the second reference voltage 1/2VDDQ and output the second comparison output signal CMPO2. The second counter 680a may output the first pull-down code PDCODE1 < 0 based on the second comparison output signal CMPO 2: n >. Although not shown, the second counter 680a may receive a selection signal SEL from the loop selector 230 of fig. 2. For example, when the selection signal SEL has a logic high level "H", the second counter 680a may output the first pull-down code PDCODE1 < 0 generated during the first cycle: n > the same first pull-down code PDCODE1 < 0: n >. The third counter 690a may output the second pull-down code PDCODE2 < 0 based on the second comparison output signal CMPO 2: n >. Although not output, the third counter 690a may receive the selection signal SEL from the loop selector 230 of fig. 2. For example, when the selection signal SEL has a logic high level "H", the third counter 690a may output the second pull-down code PDCODE2 < 0 generated during the second cycle: n >. The first pull-down circuit 630a may receive the first pull-down code PDCODE1 < 0 during the second cycle: n > and the second resistance value is set smaller than the first resistance value. In detail, the resistance value of the first pull-down circuit 630a may be affected by process variations that may occur during the fabrication of the semiconductor memory device. The second pull-down circuit 640a may receive the second pull-down code PDCODE2 < 0 during the second cycle: n > and the third resistance value is set to be larger than the first resistance value. In this regard, in an embodiment, the equivalent resistance value of the second resistance value and the third resistance value may be equal to the first resistance value.

In some embodiments, the resistance value of the ZQ resistor RZQ may be 120Ω. In this regard, when the second reference voltage 1/2VDDQ is input to the ZQ engine 600a in the second cycle, the resistance value of the first pull-up circuit 610a may be 120Ω, the resistance value of the second pull-up circuit 620a may be 40Ω, the first resistance value may be 80Ω, the second resistance value of the first pull-down circuit 630a may be 80- αΩ, and the third resistance value of the second pull-down circuit 640a may be 80+αΩ. In this regard, α may be a positive number. Since the first pull-down circuit 630a and the second pull-down circuit 640a are connected in parallel, the resistance value of the equivalent resistance of the first pull-down circuit 630a and the second pull-down circuit 640a may be 40Ω.

Referring to fig. 6B, a pull-up circuit 610B included in DQ driver 600B may be configured to output a pull-up code PUCODE < 0 according to the pull-up code input during the second cycle: n > is turned off. In this case, the pull-up code PUCODE input to the pull-up circuit 610b is < 0: n > may be the pull-up code PUCODE < 0 generated during the first cycle: n >. Although not shown, the logic circuit may receive the pull-up code PUCODE < 0: n >, and provides a pull-up code PUCODE < 0: n > to turn off the pull-up circuit 610b during the second cycle. The first pull-down circuit 620b may be based on the first pull-down code PDCODE1 < 0 input during the second cycle: n > the second resistance value is set smaller than the first resistance value. The second pull-down circuit 630b may be configured to output a second pull-down code PDCODE2 < 0 according to the second pull-down code PDCODE input during the second cycle: n > the third resistance value is set to be larger than the first resistance value. In this regard, in an embodiment, the equivalent resistance value of the second resistance value and the third resistance value may be equal to the first resistance value.

In some embodiments, the resistance value of ZQ resistor RZQ may be 120Ω and the resistance value of DQ resistor RDQ may be 40Ω. In this regard, when the second reference voltage 1/2VDDQ is input to the ZQ engine 600a in the second cycle, the first resistance value may be 80 Ω, the second resistance value of the first pull-down circuit 620b may be 80- αΩ, and the third resistance value of the second pull-down circuit 630b may be 80+αΩ. Since the first pull-down circuit 620b and the second pull-down circuit 630b are connected in parallel, the resistance value of the equivalent resistance of the first pull-down circuit 620b and the second pull-down circuit 630b may be 40Ω. A voltage having the same level as the level of the second reference voltage 1/2VDDQ may be generated on the DQ pad 602.

Referring to fig. 5A and 6A, each of the first pull-up circuits 510a and 610a, each of the second pull-up circuits 520a and 620a, each of the first pull-down circuits 530a and 630a, each of the second pull-down circuits 540a and 640a, each of the first comparators 550a and 650a, each of the second comparators 570a and 670a, each of the first counters 560a and 660a, each of the second counters 580a and 680a, and each of the third counters 590a and 690a may correspond to each of the first pull-up circuit 310, the second pull-up circuit 320, the first pull-down circuit 330, the second pull-down circuit 340, the first comparator 350, the second comparator 370, the first counter 360, the second counter 380, and the third counter 390 of fig. 3, respectively.

Referring to fig. 5B and 6B, each of the pull-up circuits 510B and 610B, each of the first pull-down circuits 520B and 620B, and each of the second pull-down circuits 530B and 630B may correspond to the pull-up circuit 410, the first pull-down circuit 420, and the second pull-down circuit 430 of fig. 4, respectively.

Fig. 7 is a flow chart illustrating a method of operation of a ZQ calibration circuit in accordance with some embodiments.

Referring to fig. 2 and 7, the reference voltage selector 210 selects a reference voltage from among a first reference voltage VREFZQ1 and a second reference voltage VREFZQ2 different from each other according to a selection signal SEL in operation S100. The first reference voltage VREFZQ1 and the second reference voltage VREFZQ2 may be generated based on the first power supply voltage VDDQ and the second power supply voltage VSS. For example, the levels of the first reference voltage VREFZQ1 and the second reference voltage VREFZQ2 may be smaller than the level of the first power supply voltage VDDQ and larger than the level of the second power supply voltage VSS.

In operation S200, the ZQ engine 220 generates a pull-up code PUCODE < 0 based on the selected reference voltage (e.g., the first reference voltage VREFZQ1 or the second reference voltage VREFZQ 2): n > and the pull-down code PDCODE < 0: n >. The pull-down code PDCODE < 0: n > may include the first pulldown code PDCODE1 < 0 of FIG. 3: n > and a second pull-down code PDCODE2 < 0: n >.

In operation S300, the loop selector 230 selects the pull-up code PUCODE < 0: n > and the pull-down code PDCODE < 0: each of N > switches to output the selection signal SEL.

Fig. 8 is a block diagram illustrating an electronic system according to some embodiments.

Referring to fig. 8, the electronic system 1000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a wearable device, a medical device, or an IoT device. Further, the electronic system 1000 may be implemented as a server or a PC.

Electronic system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, volatile memories 1500a and 1500b, flash memories 1600a and 1600b, I/O devices 1700a and 1700b, and an Application Processor (AP) 1800.

The camera 1100 may capture a still image or a moving image under the control of a user.

The audio processor 1300 may process audio data or web content included in the flash memories 1600a and 1600 b.

The modem 1400 may modulate and transmit a signal for transmission/reception of wired/wireless data and may demodulate the signal to restore an original signal at a receiving side.

I/O devices 1700a and 1700b may include devices that provide digital input and/or output functionality.

The AP 1800 may control the overall operation of the electronic system 1000. AP 1800 may control display 1200 to display portions of the content. When receiving user input through the I/O devices 1700a and 1700b, the AP 1800 may perform control operations corresponding to the user input. The AP 1800 may include an accelerator 1820 for dedicated circuitry for computing Artificial Intelligence (AI) data. The volatile memory 1500b may additionally be mounted on the accelerator 1820. The accelerator 1820 may be a functional block dedicated to performing a particular function of the AP 1800. The accelerator 1820 may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and a Data Processing Unit (DPU). The GPU may be a block dedicated to graphics data processing. The NPU may be a functional block dedicated to AI computation and reasoning. The DPU may be a functional block dedicated to data transmission.

The AP 1800 may control the volatile memories 1500a and 1500b by command and Mode Register Set (MRS) conforming to Joint Electron Device Engineering Council (JEDEC) standard. In addition, the AP 1800 may set up a DRAM interface protocol to use company specific functions such as low voltage/high speed/reliability and Cyclic Redundancy Check (CRC)/Error Correction Code (ECC) functions.

The controller 1810 included in the AP 1800 may correspond to the ZQ calibration circuit 110 described above with reference to fig. 1.

Volatile memories 1500a and 1500b have relatively smaller latency and bandwidth than I/O devices 1700a and 1700b or flash memories 1600a and 1600 b. Volatile memories 1500a and 1500b may be initialized upon power-up of electronic system 1000, loaded with operating system and application data, and used as temporary storage for operating system and application data or as execution space for various software codes.

Within the volatile memories 1500a and 1500b, an addition/subtraction/multiplication/division operation, a vector operation, an address operation, or a Fast Fourier Transform (FFT) operation may be performed. In addition, the functions for performing reasoning can be performed in the volatile memories 1500a and 1500 b.

Each of the volatile memories 1500a and 1500b may correspond to the semiconductor memory device 100 of fig. 1. Thus, each of the volatile memories 1500a and 1500b may include ZQ pads and DQ pads, and may include ZQ calibration circuitry and DQ drivers.

Flash memories 1600a and 1600b may store photographs taken by camera 1100 or data transmitted through a data network. Flash memories 1600a and 1600b may have a larger capacity than volatile memories 1500a and 1500 b.

While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A ZQ calibration circuit included in a semiconductor memory device, the ZQ calibration circuit comprising:

a reference voltage selector configured to output a reference voltage selected from a first reference voltage and a second reference voltage generated based on the first power supply voltage and the second power supply voltage in response to a selection signal;

a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage; and

a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is switched,

wherein the levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

2. The ZQ calibration circuit of claim 1, wherein the ZQ calibration circuit is configured to perform ZQ calibration operations during a first cycle and during a second cycle subsequent to the first cycle, and

Wherein the reference voltage selector is further configured to:

providing the first reference voltage to the ZQ engine as the selected reference voltage during the first cycle, an

During the second cycle, the second reference voltage is provided to the ZQ engine as the selected reference voltage.

3. The ZQ calibration circuit of claim 1, wherein the ZQ engine comprises:

a first comparator connected to a ZQ pad of the semiconductor memory device and configured to output a first comparison output signal based on a voltage generated on the ZQ pad and the selected reference voltage;

a first counter configured to output the pull-up code based on the first comparison output signal;

a first pull-up circuit connected between a first node supplied with the first power supply voltage and a second node connected to the ZQ pad, and configured to adjust a resistance value of the first pull-up circuit in response to the pull-up code;

a second pull-up circuit connected between a third node and a fourth node to which the first power supply voltage is supplied, and configured to adjust a resistance value of the second pull-up circuit in response to the pull-up code;

A second comparator configured to output a second comparison output signal based on the voltage generated on the fourth node and the selected reference voltage;

a second counter configured to output a first pull-down code based on the second comparison output signal;

a first pull-down circuit connected between the fourth node and a fifth node supplied with the second power supply voltage and configured to adjust a resistance value of the first pull-down circuit in response to the first pull-down code;

a third counter configured to output a second pull-down code based on the second comparison output signal; and

and a second pull-down circuit connected between the fourth node and a sixth node supplied with the second power supply voltage, and configured to adjust a resistance value of the second pull-down circuit in response to the second pull-down code.

4. The ZQ calibration circuit of claim 3, wherein the first pull-up circuit comprises:

at least one p-type transistor including a first electrode connected to the first node, a second electrode, and a gate electrode configured to receive the pull-up code; and

at least one resistor connected between the respective second electrode and the second node.

5. The ZQ calibration circuit of claim 3, wherein the second pull-up circuit comprises:

at least one p-type transistor including a first electrode connected to the third node, a second electrode, and a gate electrode configured to receive the pull-up code; and

at least one resistor connected between the respective second electrode and the fourth node.

6. The ZQ calibration circuit of claim 3, wherein the first pull-down circuit comprises:

at least one resistor comprising a first terminal and a second terminal connected to the fourth node; and

at least one n-type transistor including a first electrode connected to the respective second terminal, a second electrode connected to the fifth node, and a gate electrode configured to receive the first pull-down code.

7. The ZQ calibration circuit of claim 3, wherein the second pull-down circuit comprises:

at least one resistor comprising a first terminal and a second terminal connected to the fourth node; and

at least one n-type transistor including a first electrode connected to the respective second terminal, a second electrode connected to the sixth node, and a gate electrode configured to receive the second pull-down code.

8. The ZQ calibration circuit of claim 3, wherein:

the ZQ calibration circuit is configured to perform ZQ calibration operations during a first cycle and during a second cycle subsequent to the first cycle,

the second comparator is further configured to:

outputting the second comparison output signal in response to the first reference voltage during the first cycle, an

Outputting the second comparison output signal in response to the second reference voltage during the second cycle,

the first pull-down circuit is further configured to:

setting a first resistance value in response to the first pull-down code during the first cycle, an

Setting a second resistance value to be smaller than the first resistance value in response to the first pull-down code during the second cycle, and

the second pull-down circuit is further configured to:

is turned off during the first cycle in response to the second pull-down code, and

a third resistance value is set to be greater than the first resistance value in response to the second pull-down code during the second cycle.

9. The ZQ calibration circuit of claim 1, wherein:

the first supply voltage is greater than the second supply voltage,

The first reference voltage is greater than the second reference voltage and less than the first power supply voltage, and

the second reference voltage is greater than the second supply voltage.

10. A semiconductor memory device, comprising:

a ZQ bonding pad;

DQ pads;

a ZQ calibration circuit configured to perform a ZQ calibration operation by using a ZQ resistor connected to the ZQ pad and generate a ZQ code; and

a DQ driver configured to determine a termination resistance value of the DQ pad based on the ZQ code,

wherein the ZQ calibration circuit includes:

a reference voltage selector configured to output a reference voltage selected from a first reference voltage and a second reference voltage generated based on the first power supply voltage and the second power supply voltage in response to a selection signal;

a ZQ engine configured to generate a pull-up code of the ZQ code and a pull-down code of the ZQ code based on the selected reference voltage; and

a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is switched,

wherein the levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.

11. The semiconductor memory device according to claim 10, wherein the ZQ calibration circuit is configured to perform a ZQ calibration operation during a first cycle and during a second cycle after the first cycle, and

wherein the reference voltage selector is further configured to:

providing the first reference voltage to the ZQ engine as the selected reference voltage during the first cycle, an

During the second cycle, a second reference voltage from among the first reference voltage and the second reference voltage is provided to the ZQ engine as the reference voltage of choice.

12. The semiconductor memory device according to claim 10, wherein the ZQ engine comprises:

a first comparator connected to the ZQ pad and configured to output a first comparison output signal based on a voltage generated on the ZQ pad and the selected reference voltage;

a first counter configured to output the pull-up code based on the first comparison output signal;

a first pull-up circuit connected between a first node supplied with the first power supply voltage and a second node connected to the ZQ pad, and configured to adjust a resistance value of the first pull-up circuit in response to the pull-up code;

A second pull-up circuit connected between a third node and a fourth node to which the first power supply voltage is supplied, and configured to adjust a resistance value of the second pull-up circuit in response to the pull-up code;

a second comparator configured to output a second comparison output signal based on the voltage generated on the fourth node and the selected reference voltage;

a second counter configured to output a first pull-down code based on the second comparison output signal;

a first pull-down circuit connected between the fourth node and a fifth node supplied with the second power supply voltage and configured to adjust a resistance value of the first pull-down circuit in response to the first pull-down code;

a third counter configured to output a second pull-down code based on the second comparison output signal; and

and a second pull-down circuit connected between the fourth node and a sixth node supplied with the second power supply voltage, and configured to adjust a resistance value of the second pull-down circuit in response to the second pull-down code.

13. The semiconductor memory device according to claim 12, wherein the first pull-up circuit comprises:

At least one p-type transistor including a first electrode connected to the first node, a second electrode, and a gate electrode configured to receive the pull-up code; and

at least one resistor connected between the respective second electrode and the second node.

14. The semiconductor memory device according to claim 12, wherein the second pull-up circuit comprises

At least one p-type transistor including a first electrode connected to the third node, a second electrode, and a gate electrode configured to receive the pull-up code; and

at least one resistor connected between the respective second electrode and the fourth node.

15. The semiconductor memory device according to claim 12, wherein the first pull-down circuit comprises

At least one resistor comprising a first terminal and a second terminal connected to the fourth node; and

at least one n-type transistor including a first electrode connected to the respective second terminal, a second electrode connected to the fifth node, and a gate electrode configured to receive the first pull-down code.

16. The semiconductor memory device according to claim 12, wherein the second pull-down circuit comprises

At least one resistor comprising a first terminal and a second terminal connected to the fourth node; and

at least one n-type transistor including a first electrode connected to the respective second terminal, a second electrode connected to the sixth node, and a gate electrode configured to receive the second pull-down code.

17. The semiconductor memory device of claim 12, wherein the DQ driver comprises:

a DQ pull-up circuit connected between a line supplied with the first power supply voltage and an output node, and configured to adjust a resistance value of the DQ pull-up circuit in response to the pull-up code;

a first DQ pull-down circuit connected between the output node and a line supplied with the second power supply voltage, and configured to adjust a resistance value of the first DQ pull-down circuit in response to the first pull-down code; and

a second DQ pull-down circuit connected between the output node and a line supplied with the second power supply voltage, and configured to adjust a resistance value of the second DQ pull-down circuit in response to the second pull-down code.

18. The semiconductor memory device according to claim 17, wherein:

The ZQ calibration circuit is configured to perform ZQ calibration operations during a first cycle and during a second cycle subsequent to the first cycle,

the second comparator is further configured to:

outputting the second comparison output signal in response to the first reference voltage during the first cycle, an

Outputting the second comparison output signal in response to the second reference voltage during the second cycle,

the first pull-down circuit is further configured to:

setting a first resistance value in response to the first pull-down code during the first cycle, an

Setting a second resistance value to be smaller than the first resistance value in response to the first pull-down code during the second cycle, and

the second pull-down circuit is further configured to:

is turned off during the first cycle in response to the second pull-down code, and

a third resistance value is set to be greater than the first resistance value in response to the second pull-down code during the second cycle.

19. The semiconductor memory device according to claim 18, wherein:

the DQ pull-up circuit is further configured to:

setting the first resistance value in response to the pull-up code during the first cycle, an

Is turned off during the second cycle in response to the pull-up code,

the first DQ pulldown circuit is further configured to:

setting the first resistance value in response to the first pull-down code during the first cycle, an

Setting the second resistance value in response to the first pull-down code during the second cycle, and

the second DQ pulldown circuit is further configured to:

is turned off during the first cycle in response to the second pull-down code, and

the third resistance value is set in response to the second pull-down code during the second cycle.

20. A method of operation of a ZQ calibration circuit, the method of operation comprising:

generating a first reference voltage and a second reference voltage based on the first power supply voltage and the second power supply voltage;

selecting a reference voltage from the first reference voltage and the second reference voltage according to a selection signal;

generating a pull-up code and a pull-down code based on the selected reference voltage; and

the selection signal is generated according to whether each of the pull-up code and the pull-down code is switched,

wherein the levels of the first reference voltage and the second reference voltage are different from each other, are smaller than the level of the first power supply voltage, and are larger than the level of the second power supply voltage.