CN117873903A

CN117873903A - Code testing method, device, electronic equipment and storage medium

Info

Publication number: CN117873903A
Application number: CN202410239000.0A
Authority: CN
Inventors: 付安琪
Original assignee: Kunlun Core Beijing Technology Co ltd
Current assignee: Kunlun Core Beijing Technology Co ltd
Priority date: 2024-03-01
Filing date: 2024-03-01
Publication date: 2024-04-12

Abstract

The disclosure provides a code testing method, relates to the technical field of artificial intelligence, and particularly relates to the technical field of chips and the technical field of code testing. The specific implementation scheme is as follows: acquiring a target to-be-executed instruction set corresponding to a target to-be-executed code segment, wherein the target to-be-executed code segment is from a plurality of to-be-executed code segments of a target code, and a plurality of instructions corresponding to the target code comprise N to-be-detected index acquisition instruction sets and M to-be-executed instruction sets; in response to determining that the target to-be-executed instruction set is executed by a target processor core in a plurality of processor cores of the chip to be tested, executing the to-be-tested index corresponding to the target to-be-executed instruction set by the target processor core to obtain an intermediate test result of the target to-be-executed instruction set, and storing the intermediate test result of the target to-be-executed instruction set in a target storage space corresponding to the target processor core. The disclosure also provides a code testing device, an electronic device and a storage medium.

Description

Code testing method, device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of manual technology, and in particular, to the field of chip technology and the field of code testing technology. More particularly, the present disclosure provides a code testing method, apparatus, electronic device, and storage medium.

Background

With the development of artificial intelligence technology, heterogeneous systems may perform a variety of artificial intelligence tasks. The heterogeneous system may include a host (host) side and a device (device) side.

Disclosure of Invention

The disclosure provides a code testing method, a code testing device, code testing equipment and a storage medium.

According to an aspect of the present disclosure, there is provided a code testing method, the method including: acquiring a target to-be-executed instruction set corresponding to a target to-be-executed code segment, wherein the target to-be-executed code segment is from a plurality of to-be-executed code segments of target codes, the plurality of instructions corresponding to the target codes comprise N to-be-tested index acquisition instruction sets and M to-be-executed instruction sets, the to-be-executed instruction sets correspond to at least one to-be-executed code segment, the N to-be-tested index acquisition instruction sets correspond to N target to-be-executed instruction sets in the M to-be-executed instruction sets, N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1; in response to determining that the target to-be-executed instruction set is executed by a target processor core in a plurality of processor cores of the chip to be tested, executing the to-be-tested index corresponding to the target to-be-executed instruction set by the target processor core to obtain an intermediate test result of the target to-be-executed instruction set, wherein the plurality of processor cores should correspond to at least one storage space, and the intermediate test result of the target to-be-executed instruction set is stored in the target storage space corresponding to the target processor core.

According to another aspect of the present disclosure, there is provided a code testing method, the method comprising: in response to determining that the plurality of instructions corresponding to the target code have been executed by the chip under test, obtaining at least one intermediate test result of a target set of instructions to be executed in the plurality of instructions from at least one memory space corresponding to a plurality of processor cores of the chip under test, wherein the at least one intermediate test result corresponds to the at least one processor core; determining a target test result of a target code segment to be executed in target codes corresponding to the target instruction set to be executed according to at least one intermediate test result of the target instruction set to be executed; and determining the target test data of the target code segment to be executed according to the initial test data of the target code segment to be executed and the target test result of the target code segment to be executed.

According to another aspect of the present disclosure, there is provided a code testing apparatus, the apparatus comprising: a first storage unit including at least one storage space; a processor core configured to: acquiring a target to-be-executed instruction set corresponding to a target to-be-executed code segment, wherein the target to-be-executed code segment is from a plurality of to-be-executed code segments of target codes, the plurality of instructions corresponding to the target codes comprise N to-be-tested index acquisition instruction sets and M to-be-executed instruction sets, the to-be-executed instruction sets correspond to at least one to-be-executed code segment, the N to-be-tested index acquisition instruction sets correspond to N target to-be-executed instruction sets in the M to-be-executed instruction sets, N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1; after the target to-be-executed instruction set is executed, executing the index to be detected corresponding to the target to-be-executed instruction set to obtain an intermediate test result of the target to-be-executed instruction set, wherein the intermediate test result of the target to-be-executed instruction set is stored in a target storage space corresponding to the processor core.

According to another aspect of the present disclosure, there is provided a code testing apparatus, the apparatus comprising: a second storage unit; a processor configured to: in response to determining that the plurality of instructions corresponding to the target code have been executed by the chip under test, obtaining at least one intermediate test result of a target set of instructions to be executed in the plurality of instructions from at least one memory space corresponding to a plurality of processor cores of the chip under test, wherein the at least one intermediate test result corresponds to the at least one processor core; determining a target test result of a target code segment to be executed in target codes corresponding to the target instruction set to be executed according to at least one intermediate test result of the target instruction set to be executed; determining target test data of the target code segment to be executed according to the initial test data of the target code segment to be executed and the target test result of the target code segment to be executed; and writing the target test data into the second storage unit.

According to another aspect of the present disclosure, there is provided an electronic device including: the present disclosure provides a code testing apparatus and another code testing apparatus provided by the present disclosure.

According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method provided in accordance with the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a method provided according to the present disclosure.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method provided according to the present disclosure.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of an exemplary system architecture to which code testing methods and apparatus may be applied, according to one embodiment of the present disclosure;

FIG. 2 is a flow chart of a code testing method according to one embodiment of the present disclosure;

FIG. 3 is a flow chart of a code testing method according to one embodiment of the present disclosure;

FIG. 4 is a flow chart of a code testing method according to one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a heterogeneous system according to one embodiment of the present disclosure;

FIG. 6 is a block diagram of a code testing apparatus according to one embodiment of the present disclosure;

FIG. 7 is a block diagram of a code testing apparatus according to one embodiment of the present disclosure;

FIG. 8 is a block diagram of a heterogeneous electronic device according to one embodiment of the present disclosure; and

fig. 9 is a block diagram of an electronic device to which a code testing method may be applied according to one embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

FIG. 1 is a schematic diagram of an exemplary system architecture to which code testing methods and apparatus may be applied, according to one embodiment of the present disclosure. It should be noted that fig. 1 is only an example of a system architecture to which embodiments of the present disclosure may be applied to assist those skilled in the art in understanding the technical content of the present disclosure, but does not mean that embodiments of the present disclosure may not be used in other devices, systems, environments, or scenarios.

As shown in fig. 1, a system architecture a100 according to this embodiment may include a host side 100 and a device side 110. The host side 100 may include a central processing unit. The user may set artificial intelligence tasks or other various tasks based on input devices associated with the host side 100. The host 100 may send some or all of the tasks to the device 110, or may perform some or all of the tasks. The host side 100 may also configure the device side 110.

The device side 110 may include an artificial intelligence chip or various simulators corresponding to various artificial intelligence chips. The artificial intelligence chip may be a Graphics Processing Unit (GPU), tensor Processing Unit (TPU), or the like. Different artificial intelligence chips correspond to one or more device end operator libraries. For example, the graphics processing unit corresponds to a unified computing device architecture deep neural network library (CUDA deep neural network library, CUDNN library). The large amount of content in the operator library is aimed at various scenes such as deep learning or mathematical calculation. These include the definition of the kernel (kernel) function of the operator running on the device side.

The user may control the system architecture a100 to perform artificial intelligence tasks based on various programming modes. The various programming modes may include a hybrid programming mode and a split programming mode. For example, based on the hybrid programming mode, the user may define the code at the host side and the code at the device side in one file. For another example, a split programming model may be implemented based on the unified computing device architecture deep neural network library described above. The unified computing device architecture deep neural network library includes operator kernel functions that can run on the device side, as well as encapsulation (wrapper) code that can run on the host side for user invocation.

Taking the example that the device side is a graphic processing unit, compiling and adapting can be performed on relevant codes of the host side based on an open source compiler. The code at the host may also be tested based on various schemes. For example, code coverage of relevant code may be tested for the host side using various schemes based on an open source compiler. Code coverage may indicate: in a program or logic system design, whether code, functions, or branches are executed, and the number of times that execution is performed. Based on code coverage, a comprehensive test of the program or logic system design may be achieved. For codes requiring a large number of operators running on the device side, the code quality can also be evaluated based on code coverage.

However, for code at the device end, it is difficult to test code coverage of relevant code based on an open source compiler. It is appreciated that the open source compiler may be an underlying virtual machine (1ow level virtual machine,llvm) compiler.

Based on this, in order to test various indexes such as code coverage of the device-side code, the present disclosure provides a code test method that can be applied to a host side and a device side, respectively, as will be described below.

Fig. 2 is a flow chart of a code testing method according to one embodiment of the present disclosure.

As shown in fig. 2, the method M200 may include operations S201 to S203, and the method M200 may be applied to a host side.

In operation S201, initial test data of each of a plurality of target code segments to be executed of a target code is acquired.

In the disclosed embodiments, a code segment may include one or more lines of code.

In the disclosed embodiment, initial test data may be obtained from an object (object) file generated for device-side compilation.

In the disclosed embodiments, the initial test data may include a code segment name, code segment information (profdata). The code segment name may be a name field (profname) of the function to which the code segment corresponds. The code segment information is used for indicating the position of the intermediate test result determined by the equipment end in the test result file. The code segment information may include a hash value (funchsh) of the function, a fifth generation message digest algorithm value (funcnameMD 5) of the function name, an offset value (offset) in the object file, and a corresponding program counter (numbers of counters).

In operation S202, configuration information corresponding to the object code is generated.

In the embodiment of the present disclosure, the configuration information may enable the device side to initialize a storage space for storing the index value of the index to be measured.

In operation S203, the object code and the configuration information are provided to the device side.

In the embodiment of the disclosure, the host side may issue the relevant information of the target code to the device side, so that the device side performs the operation corresponding to the target code. For example, taking the code coverage as an example where the index to be measured is, the relevant information of the object code includes relevant information of the function with coverage enabled.

It will be appreciated that the above describes the pre-processing before the operator kernel (launch kernel) is run. After receiving the configuration information and the related information of the object code, the device side may perform related operations to run an operator kernel function, which will be described below.

Fig. 3 is a schematic flow chart of a code testing method according to another embodiment of the present disclosure.

As shown in fig. 3, the method M310 may include operations S311 to S312, and the method M310 may be applied to a device side.

In operation S311, a target to-be-executed instruction set corresponding to the target to-be-executed code segment is acquired.

In the disclosed embodiments, the target code segment to be executed may be from multiple code segments of the target code to be executed. For example, the target code segment to be executed may correspond to the function with coverage enabled described above.

In the embodiment of the disclosure, the plurality of instructions corresponding to the object code includes N sets of index acquisition instructions to be tested. The index acquisition instruction set to be tested comprises one or more index acquisition instructions to be tested.

In an embodiment of the present disclosure, the plurality of instructions corresponding to the object code may further include M sets of instructions to be executed. The M instructions to be executed may include N sets of target instructions to be executed. The N target to-be-executed instruction sets may respectively correspond to N to-be-tested index acquisition instruction sets. The set of instructions to be executed may also include at least one instruction to be executed.

In the embodiments of the present disclosure, N may be an integer greater than or equal to 1 and less than or equal to M. M may be an integer greater than or equal to 1.

In operation S312, in response to determining that the target to-be-executed instruction set is executed by a target processor core of the plurality of processor cores of the chip to be tested, the target processor core is utilized to execute the to-be-tested index corresponding to the target to-be-executed instruction set to obtain an intermediate test result of the target to-be-executed instruction set.

In the embodiment of the disclosure, the chip to be tested may be an artificial intelligent chip included in the device side. For example, the chip to be tested may be any artificial intelligence chip such as a graphics processing unit, tensor processing unit, neural Network Processing Unit (NPU), and a kunlun core.

In embodiments of the present disclosure, the chip under test may include a plurality of processor cores. Each processor core may execute instructions in a set of instructions to be executed.

In an embodiment of the present disclosure, the plurality of processor cores may correspond to at least one memory space. For example, the plurality of processor cores may respectively correspond to the plurality of memory spaces. Taking the example that the device side is a graphics processing unit, the storage space may be a video memory space.

In embodiments of the present disclosure, the target set of instructions to be executed may be executed separately by one or more processor cores. For example, if a target to-be-executed code segment is associated with loop, jump, etc. code, the corresponding target to-be-executed instruction set may be executed one or more times. In the case of multiple executions, the target set of instructions to be executed may be executed multiple times by different processor cores.

In the embodiment of the disclosure, the intermediate test result of the target to-be-executed instruction set is stored in a target storage space corresponding to the target processor core. The target to-be-executed instruction set may be executed after the target to-be-executed instruction set is executed, so as to determine a value of the target to-be-measured index of the corresponding target to-be-executed code segment. If the target to-be-executed instruction set is executed by different processor cores for multiple times, the corresponding to-be-tested index acquisition instruction set can also be executed by the corresponding processor cores for multiple times. After each execution by a processor core, the corresponding intermediate test results may be stored to the memory space corresponding to the processor core.

According to the embodiment of the disclosure, the intermediate test result obtained by executing the index obtaining instruction set to be tested is stored in the storage space corresponding to the corresponding processor core, so that the code test of the equipment end of the heterogeneous system can be realized.

It will be appreciated that the code testing method executed by the device side is described above, and the object code of the present disclosure will be further described below.

In some embodiments, the object code is obtained by inserting a metric under test acquisition code segment into the code under execution by: and inserting N indexes to be tested to obtain code segments based on the positions of N target code segments to be executed in the M code segments to be executed.

In the disclosed embodiments, the code to be executed may include M code segments to be executed. In order to determine the value of the index to be measured, a corresponding stub may be torn down at the target location of the code to be executed based on the stub-inserting operation. For example, the target location may be the location of a basic block on the minimum spanning tree path. Based on the positions of these basic blocks, corresponding piles are inserted. If the index to be measured is code coverage, the inserted stub can record the execution times of each basic block. It will be appreciated that the location of the basic block may be the location of the target code segment to be executed and that the stub may obtain the code segment for the target index to be tested.

In the embodiment of the disclosure, the to-be-measured index acquisition instruction set and the to-be-executed instruction set may be generated based on the to-be-measured index acquisition code segment and the to-be-executed code segment, respectively. For example, based on the N to-be-measured index acquiring code segments and the M to-be-executed code segments, N to-be-measured index acquiring instruction sets and M to-be-executed instruction sets corresponding to the instruction set architecture of the to-be-measured chip may be generated. It is understood that the index to be measured acquisition code segment may be the code form of the stub described above. The index to be measured acquisition instruction set may be the instruction form of the pile.

It will be appreciated that, taking the example of an underlying virtual machine compiler, a instrumentation algorithm based on an abstract syntax tree (Abstract Syntax Tree, AST) may insert instrumentation into the code to be executed to obtain target code. In addition, after compiling the target code, initial test data corresponding to the positions of the to-be-tested index acquisition code segment and the corresponding target to-be-executed code segment can be obtained.

It will be appreciated that some ways of obtaining a code with index to be tested acquisition enabled are described above, and a storage space for storing intermediate test results of the index to be tested acquisition code will be described below.

In some embodiments, method M310 may further comprise: at least one memory space corresponding to the plurality of processor cores is determined based on the configuration information corresponding to the object code.

In an embodiment of the present disclosure, a chip under test may include a plurality of clusters (clusters) of a plurality of processor cores. Each cluster may include a plurality of processor cores.

In the embodiment of the disclosure, compared with a host end, a chip to be tested of a heterogeneous system belongs to slave equipment. The results of the pile records can be obtained by the host end and further combined. Thus, the result of the pile record can be stored in the corresponding storage space so as to be acquired by the host side. The storage space may be determined according to configuration information issued by the host side.

In the embodiment of the disclosure, for each storage space, an instruction set may be acquired for each index to be tested, and a storage subspace may be determined. For example, for the N index fetch instruction sets to be tested described above, N storage subspaces may be defined in the storage space of each processor core. Each storage subspace corresponds to one index acquisition instruction set to be tested. Therefore, each processor core can independently store the intermediate test result into the corresponding storage space, and the accuracy of the index to be tested can be effectively provided.

It will be appreciated that some ways of determining the storage space are described above, and a description of the set of index to be measured acquisition instructions of the present disclosure will be provided below.

In some embodiments, the set of index fetch to be tested instructions includes a load instruction (load), an accumulate instruction (add), and a store instruction (store).

In some embodiments, executing, with the target processor core, the target to-be-executed instruction set corresponding to the target to-be-executed instruction set to obtain the intermediate test result of the target to-be-executed instruction set may include: the load instruction is executed with the target processor core to load the current test results of the target set of instructions to be executed from the target memory space. For example, the current test result may be the number i of times the set of index fetch instructions under test is executed by the target processor core. The current test results are stored in a storage subspace of the target storage space. The storage subspace corresponds to the index acquisition instruction set to be tested. The current test result may be loaded.

In some embodiments, executing, by the target processor core, the target to-be-tested index acquisition instruction set corresponding to the target to-be-executed instruction set, and obtaining the intermediate test result of the target to-be-executed instruction set may further include: and executing an accumulation instruction by using the target processor core so as to accumulate the current test result and a preset value to obtain an intermediate test result. For example, the preset value may be 1. And adding the current test result i with a preset value 1 to obtain an intermediate test result i+1.

In some embodiments, executing, by the target processor core, the target to-be-tested index acquisition instruction set corresponding to the target to-be-executed instruction set, and obtaining the intermediate test result of the target to-be-executed instruction set may further include: the store instruction is executed with the target processor core to store the intermediate test results to the target memory space. For example, the intermediate test result may be written into a storage subspace corresponding to the index acquisition instruction set to be tested.

It will be appreciated that the foregoing describes the execution of the index to be tested acquisition instruction set of the present disclosure, and the following describes the intermediate test results of the present disclosure.

In some embodiments, there is a mapping relationship between the intermediate test results and the initial test data for the target code segment to be executed in the test results file. For example, the intermediate test results correspond to the target code segment to be executed. The target code segment to be executed corresponds to the initial test data. Thus, the intermediate test results may have a mapping relationship with the initial test data. According to the embodiment of the disclosure, after the M instruction sets to be executed are executed, based on the mapping relation between the intermediate test result and the initial test data, the test results determined by different processor cores can be corresponding to the same target code segment to be executed so as to reversely solve the test file of the code to be executed.

It will be appreciated that some ways of obtaining test results of the instruction set at the device side are described above, and some ways of obtaining test result files of the code at the host side will be described below.

Fig. 4 is a flow chart of a code testing method according to another embodiment of the present disclosure.

As shown in fig. 4, the method M401 may include operations S404 to S406. It will be appreciated that after the multiple instructions of the object code are executed, the host side may perform method M401.

In operation S404, at least one intermediate test result of a target to-be-executed instruction set of the plurality of instructions is obtained from at least one memory space corresponding to the plurality of processor cores of the chip to be tested in response to determining that the plurality of instructions corresponding to the target code have been executed by the chip to be tested.

In an embodiment of the present disclosure, the target set of instructions to be executed may be executed by one or more processor cores. In one or more processor cores that execute the target set of instructions to be executed, each processor core may execute the target set of instructions to be executed one or more times. For example, taking a plurality of processor cores corresponding to a plurality of storage spaces respectively as an example, the intermediate test result of the target instruction set to be executed by each processor core may be obtained from N storage subspaces of each storage space of the device side respectively. Next, for each target set of instructions to be executed, at least one processor core from among the plurality of processor cores that executed the target set of instructions to be executed may be determined. And taking at least one intermediate test result of the at least one processor core as at least one intermediate test result of the target to-be-executed instruction set. It can be appreciated that there may be instruction sets that are not executed by the chip under test among the M instruction sets to be executed.

In operation S405, a target test result of a target code segment to be executed in the target code corresponding to the target instruction set to be executed is determined according to at least one intermediate test result of the target instruction set to be executed.

In the embodiment of the present disclosure, taking the to-be-tested index as an example of code coverage rate, the intermediate test result may be the number of times the target to-be-executed instruction set is executed, and the statistics results of the cluster enabled by the device end and the execution number of times of the processor core are correspondingly accumulated, so as to obtain the target test result of the target to-be-executed instruction set. For example, if the target set of instructions to be executed p times by a first processor core and q times by a second processor core of the plurality of processor cores, the target test result for the target set of instructions to be executed may be p+q times. p may be an integer greater than or equal to 1 and q may be an integer greater than or equal to 1.

In operation S406, the target test data of the target code segment to be executed is determined according to the initial test data of the target code segment to be executed and the target test result of the target code segment to be executed.

In the embodiment of the disclosure, based on the mapping relation, the target test result is added to a position corresponding to the initial test data, so as to obtain the target test data. For example, taking the code coverage rate as an example, the target test result may be used as the value of the execution times profcount, and the value may be filled into the position corresponding to the initial test data, so as to obtain the target test data.

In some embodiments, the target code segment to be executed may be multiple. The method M401 may further include: and generating a test result file of the target code according to the target test data of the target code segments to be executed. For example, based on the target test data of each of the plurality of target code segments to be executed, a test result file device.

In the embodiment of the disclosure, if the heterogeneous system is controlled based on the hybrid programming mode, after the executable program is executed, the test result file default. And combining the test result files of the host end and the equipment end to obtain a unified output file.

In the embodiment of the disclosure, if the heterogeneous system is controlled based on the split programming mode and the target code is executed multiple times, multiple test result files at the device end may be fused into an output file.

In embodiments of the present disclosure, an output file may be presented. For example, taking the example that the open source compiler is an underlying virtual machine compiler and the index to be tested is code coverage, the output file may be shown by using the related tool llvm-cov of the underlying virtual machine compiler to show the corresponding test report and details.

It will be appreciated that the foregoing describes the method for testing the code of the host side and the device side of the present disclosure, respectively, and the following describes the method for testing the code of the heterogeneous system of the present disclosure with reference to fig. 5.

Fig. 5 is a schematic diagram of a heterogeneous system according to one embodiment of the present disclosure.

As shown in fig. 5, the compiler C500 may compile the code to be executed to obtain an object file. From the object file, an object file for the device side can be determined. Thus, the host 500 may perform the operations S201 and S202 described above to obtain the initial test data and the configuration information of each of the plurality of target code segments to be executed, so as to complete the preprocessing. Next, the host side 500 may perform the above-described operation S203, providing the object code and the configuration information to the device side 510. The device side 510 may execute a plurality of instructions of the target code (for example, execute the method M510 described above for executing the plurality of instructions multiple times) to obtain intermediate test results of each of a plurality of target instruction sets to be executed. After the device side 510 performs, the host side may perform the method M401 described above to perform post-processing to obtain a test result file.

It will be appreciated that the code testing method of the present disclosure is described above, and the code testing apparatus of the present disclosure will be described below.

Fig. 6 is a schematic block diagram of a code testing apparatus according to one embodiment of the present disclosure.

As shown in fig. 6, the apparatus 610 may include a first storage unit 611 and a processor core 61 2. It will be appreciated that the apparatus 610 may be the device end described above.

The first storage unit 611 includes at least one storage space.

Processor core 612 may be configured to: and acquiring a target to-be-executed instruction set corresponding to the target to-be-executed code segment. For example, the target to-be-executed code segment is from a plurality of to-be-executed code segments of the target code, the plurality of instructions corresponding to the target code include N to-be-detected index acquisition instruction sets and M to-be-executed instruction sets, the to-be-executed instruction sets correspond to at least one to-be-executed code segment, the N to-be-detected index acquisition instruction sets correspond to N target to-be-executed instruction sets in the M to-be-executed instruction sets, N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 1.

Processor core 612 may also be configured to: after the target to-be-executed instruction set is executed, executing the to-be-detected index acquisition instruction set corresponding to the target to-be-executed instruction set to obtain an intermediate test result of the target to-be-executed instruction set. Intermediate test results of a target set of instructions to be executed are stored in a target memory space corresponding to the processor core.

In some embodiments, the object code is obtained by inserting a metric under test acquisition code segment into the code under execution by: and inserting N indexes to be tested to obtain code segments based on the positions of N target code segments to be executed in the M code segments to be executed. The code to be executed comprises M code segments to be executed, and the code segment to be tested index acquisition corresponds to the instruction set to be tested index acquisition.

In some embodiments, the target to be tested acquisition instruction set includes a load instruction, an accumulate instruction, and a store instruction, the processor core is further configured to perform the following operations to execute the target to be tested acquisition instruction set corresponding to the target to be tested instruction set, resulting in an intermediate test result of the target to be tested instruction set: the load instruction is executed to load the current test result of the target set of instructions to be executed from the target memory space. Executing the accumulate instruction to: and accumulating the current test result with a preset value to obtain an intermediate test result. The store instruction is executed to store the intermediate test results to the target storage space.

In some embodiments, the intermediate test result has a mapping relationship with initial test data of the target code segment to be executed in the test result file, where the initial test data includes a code segment name and code segment information, and the code segment information is used to indicate a position of the intermediate test result in the test result file.

In some embodiments, the processor core is further configured to: and determining the target storage space in the first storage unit according to the configuration information corresponding to the target code.

Fig. 7 is a block diagram of a code testing apparatus according to another embodiment of the present disclosure.

As shown in fig. 7, the apparatus 700 may include a second storage unit 701 and a processor 702. It is understood that the apparatus 700 may be the host side described above.

The processor 702 may be configured to: in response to determining that the plurality of instructions corresponding to the target code have been executed by the chip under test, obtaining at least one intermediate test result of a target set of instructions to be executed from among the plurality of instructions in at least one memory space corresponding to the plurality of processor cores of the chip under test. The at least one intermediate test result corresponds to the at least one processor core. And determining a target test result of the target code segment to be executed in the target code corresponding to the target instruction set to be executed according to at least one intermediate test result of the target instruction set to be executed. And determining the target test data of the target code segment to be executed according to the initial test data of the target code segment to be executed and the target test result of the target code segment to be executed. And writing the target test data into the second storage unit.

In some embodiments, the target code segment to be executed is a plurality of, and the processor may be further configured to: and generating a test result file of the target code according to the target test data of the target code segments to be executed.

It will be appreciated that while the apparatus of the present disclosure has been described above, an electronic device comprising the apparatus will be described below.

Fig. 8 is a schematic block diagram of an electronic device according to one embodiment of the present disclosure.

As shown in fig. 8, the apparatus 80 may include a code testing device 800 and a code testing device 810.

In the disclosed embodiment, the code testing apparatus 800 may be the apparatus 600 described above. Code testing device 810 may be device 710 described above.

In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 9 shows a schematic block diagram of an example electronic device 900 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 9, the apparatus 900 includes a computing unit 901 that can perform various appropriate actions and processes according to a computer program stored in a Read-Only Memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access Memory (Random Access Memory, RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other by a bus 904. An Input/Output (I/O) interface 905 is also connected to bus 904.

Various components in device 900 are connected to I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, or the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, an optical disk, or the like; and a communication unit 909 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.

The computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 901 include, but are not limited to, a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graph Processing Unit, GPU), various dedicated artificial intelligence (Artificial Intelligence, AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (Digital Signal Processor, DSP), and any suitable processors, controllers, microcontrollers, etc. The computing unit 901 performs the respective methods and processes described above, such as a text processing method and/or a deployment method of a deep learning framework. For example, in some embodiments, the text processing method and/or the deployment method of the deep learning framework may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 900 via the ROM 902 and/or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the text processing method and/or the deployment method of the deep learning framework described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the text processing method and/or the deployment method of the deep learning framework in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (Field Programmable Gate Array, FPGAs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), application specific standard products (Application Specific Standard Parts, ASSPs), systems On Chip (SOC), complex programmable logic devices (Complex Programmable Logic Device, CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access Memory, a read-Only Memory, an erasable programmable read-Only Memory (EPROM) or flash Memory, an optical fiber, a portable compact disc read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a Cathode Ray Tube (CRT) display or a liquid crystal display (Liquid Crystal Display, LCD)) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area network (Local Aera Network, LAN), wide area network (Wide Aera Network, WAN) and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A code testing method, comprising:

acquiring a target to-be-executed instruction set corresponding to a target to-be-executed code segment, wherein the target to-be-executed code segment is from a plurality of to-be-executed code segments of target codes, the plurality of instructions corresponding to the target codes comprise N to-be-tested index acquisition instruction sets and M to-be-executed instruction sets, the to-be-executed instruction sets correspond to at least one to-be-executed code segment, the N to-be-tested index acquisition instruction sets correspond to N target to-be-executed instruction sets in the M to-be-executed instruction sets, N is an integer which is greater than or equal to 1 and less than or equal to M, and M is an integer which is greater than or equal to 1;

And responding to the fact that the target to-be-executed instruction set is executed by a target processor core in a plurality of processor cores of a chip to be tested, executing the to-be-tested index corresponding to the target to-be-executed instruction set by the target processor core to obtain an intermediate test result of the target to-be-executed instruction set, wherein the processor cores correspond to at least one storage space, and the intermediate test result of the target to-be-executed instruction set is stored in the target storage space corresponding to the target processor core.

2. The method of claim 1, wherein the object code is obtained by inserting an index to be measured acquisition code segment into code to be executed by:

and inserting N code segments to be obtained by the index to be tested based on the positions of N target code segments to be tested in the M code segments to be tested, wherein the code to be tested comprises M code segments to be tested, and the code segments to be tested correspond to the instruction set to be tested.

3. The method of claim 1, wherein the set of index fetch to be tested instructions comprises a load instruction, an accumulate instruction, and a store instruction,

The step of obtaining the instruction set by using the target processor core to execute the index to be tested corresponding to the target instruction set to be executed, and the step of obtaining the intermediate test result of the target instruction set to be executed includes:

executing the load instruction with the target processor core to load a current test result of the target set of instructions to be executed from the target memory space;

executing, with the target processor core, the accumulate instruction to: accumulating the current test result with a preset value to obtain the intermediate test result;

executing the store instruction with the target processor core to store the intermediate test result to the target memory space.

4. The method of claim 1, wherein the intermediate test result has a mapping relationship with initial test data of the target code segment to be executed in a test result file, the initial test data including a code segment name and code segment information, the code segment information being used to indicate a location of the intermediate test result in the test result file.

5. The method of claim 1, further comprising:

and determining at least one storage space corresponding to a plurality of processor cores according to the configuration information corresponding to the target code.

6. A code testing method, comprising:

in response to determining that a plurality of instructions corresponding to target codes have been executed by a chip to be tested, obtaining at least one intermediate test result of a target instruction set to be executed in the plurality of instructions from at least one storage space corresponding to a plurality of processor cores of the chip to be tested, wherein at least one intermediate test result corresponds to at least one processor core;

determining a target test result of a target code segment to be executed in the target code corresponding to the target instruction set to be executed according to at least one intermediate test result of the target instruction set to be executed;

and determining the target test data of the target code segment to be executed according to the initial test data of the target code segment to be executed and the target test result of the target code segment to be executed.

7. The method of claim 6, wherein the target code segment to be executed is a plurality of,

the method further comprises the steps of:

and generating a test result file of the target code according to the target test data of the target code segments to be executed.

8. A code testing apparatus comprising:

A first storage unit including at least one storage space;

a processor core configured to:

after the target to-be-executed instruction set is executed, executing the to-be-detected index acquisition instruction set corresponding to the target to-be-executed instruction set to obtain an intermediate test result of the target to-be-executed instruction set, wherein the intermediate test result of the target to-be-executed instruction set is stored in a target storage space corresponding to the processor core.

9. The apparatus of claim 8, wherein the object code is obtained by inserting an index to be measured acquisition code segment into code to be executed by:

10. The apparatus of claim 8, wherein the set of index fetch to be tested instructions comprises a load instruction, an accumulate instruction, and a store instruction,

the processor core is further configured to execute the following operations to execute the to-be-tested index acquisition instruction set corresponding to the target to-be-executed instruction set, so as to obtain an intermediate test result of the target to-be-executed instruction set:

executing the loading instruction so as to load the current test result of the target to-be-executed instruction set from the target storage space;

executing the accumulate instruction to: accumulating the current test result with a preset value to obtain the intermediate test result;

and executing the storage instruction so as to store the intermediate test result into the target storage space.

11. The apparatus of claim 8, wherein the intermediate test result has a mapping relationship with initial test data of the target code segment to be executed in a test result file, the initial test data including a code segment name and code segment information, the code segment information indicating a location of the intermediate test result in the test result file.

12. The apparatus of claim 8, wherein the processor core is further configured to:

and determining the target storage space in the first storage unit according to the configuration information corresponding to the target code.

13. A code testing apparatus comprising:

a second storage unit;

a processor configured to:

determining target test data of the target code segment to be executed according to the initial test data of the target code segment to be executed and a target test result of the target code segment to be executed;

and writing the target test data into the second storage unit.

14. The apparatus of claim 13, wherein the target code segment to be executed is a plurality of,

the processor may be further configured to:

15. A heterogeneous electronic device, comprising:

the device of any one of claims 8 to 12;

the device of any one of claims 13 to 14.

16. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.

17. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

18. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 7.