CN117873427A

CN117873427A - Arithmetic logic unit, operation processing method, chip and electronic equipment

Info

Publication number: CN117873427A
Application number: CN202311840009.9A
Authority: CN
Inventors: 李雨励; 王成卉; 丁贡献
Original assignee: Xiangdixian Computing Technology Chongqing Co ltd
Current assignee: Xiangdixian Computing Technology Chongqing Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-04-12

Abstract

The present disclosure provides an arithmetic logic unit, an arithmetic processing method, a chip, and an electronic apparatus. The arithmetic logic unit comprises a data acquisition module and an operation module, wherein the operation module comprises a multiplication processing sub-module, an addition processing sub-module, a shifting sub-module and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively; the data acquisition module is used for acquiring the to-be-multiplied addition calculation data; any sub-module in the operation module is used for calling a local processing sub-unit to process the to-be-multiplied addition calculation data according to the floating point number precision type of the to-be-multiplied addition calculation data to obtain a processing result; any processing subunit in any sub-module is used for processing a group of second precision floating point numbers, and a plurality of processing subunits in any sub-module are used for carrying out joint processing on a group of first precision floating point numbers.

Description

Arithmetic logic unit, operation processing method, chip and electronic equipment

Technical Field

The disclosure relates to the field of computer technology, and in particular, to an arithmetic logic unit, an arithmetic processing method, a chip and electronic equipment.

Background

Currently, high performance chips typically require multiply-add operations (fused multiply-add FMA, or multiply-add MAC, multiple-accept) that support multiple precision floating point numbers.

In order to enable the chip to support multiplication and addition operations of various precision floating point numbers, multiplication and addition devices are required to be respectively deployed on the chip aiming at various precision floating point numbers, and therefore more chip area is occupied.

Disclosure of Invention

The object of the present disclosure is to provide an arithmetic logic unit, an arithmetic processing method, a chip, and an electronic device.

According to a first aspect of the present disclosure, there is provided an arithmetic logic unit for processing multiply-add operations of a first precision floating point number and a second precision floating point number, where the second precision floating point number is any precision floating point number having a tail bit width not greater than 1/2 of a tail bit width of the first precision floating point number, the arithmetic logic unit including a data acquisition module and an operation module, where the operation module includes a multiplication processing sub-module, an addition processing sub-module, a shift sub-module, and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively;

the data acquisition module is used for acquiring the to-be-multiplied addition calculation data;

Any sub-module in the operation module is used for calling a local processing sub-unit to process the to-be-multiplied addition calculation data according to the floating point number precision type of the to-be-multiplied addition calculation data to obtain a processing result; any processing subunit in any sub-module is used for processing a group of second precision floating point numbers, and a plurality of processing subunits in any sub-module are used for carrying out joint processing on a group of first precision floating point numbers.

In one embodiment, the set of to-be-multiplied addition calculation data includes two multipliers and an addition number; the multiplication processing submodule comprises processing subunits as follows: at least 2N multiplication units with the same input bit width and an accumulation unit, wherein N is a positive integer not less than 2; the input bit width of the multiplication unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number;

the data acquisition module is further configured to split, for each of the two multipliers, its mantissa to obtain two sub-mantissas, if the to-be-multiplied addition calculation data is a first precision floating point number; any sub-tail digit width is equal and meets the input requirement of the multiplication unit; combining the sub-mantissas corresponding to the two multipliers to obtain four groups of combined results, wherein each group of combined results comprises two sub-mantissas corresponding to different multipliers; inputting the four groups of combined results to four multiplication units respectively;

And the multiplication processing submodule is used for calling four multiplication units of input data to execute multiplication operation on the input data, and calling the accumulation unit to execute accumulation operation on the output of the four multiplication units to obtain mantissa multiplication results of two multipliers.

In one embodiment, the shift submodule includes a processing subunit that is: at least N antipodal shift units; the input bit width of the opposite-order shifting unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number;

the addition processing submodule is specifically used for determining the product of two multipliers and the high-order level difference and the low-order level difference between addends;

the shift sub-module is specifically used for splitting the mantissa of the addend to obtain a high-order sub-mantissa and a low-order sub-mantissa, wherein the high-order sub-mantissa and the low-order sub-mantissa have the same bit width;

under the condition that the product of the two multipliers is larger than the additive number, any pair of order shifting units are called, and the order shifting is carried out on the high-order sub-mantissa by utilizing the step difference, so that a high-order sub-mantissa order shifting result is obtained, and data are shifted right;

calling any other opposite-order shifting unit, combining right shifting-out data with the low-order sub-mantissa to obtain the low-order sub-mantissa to be shifted, and carrying out opposite-order shifting on the low-order sub-mantissa to be shifted by utilizing the low-order step difference to obtain a low-order sub-mantissa opposite-order result;

Under the condition that the product of the two multipliers is smaller than the additive number, any pair of order shifting units are called, and the order shifting is carried out on the low-order sub-mantissa by utilizing the step difference, so that a low-order sub-mantissa order shifting result and left shift data are obtained;

calling any other opposite-order shifting unit, and combining the left shift-out data with the high-order sub-mantissa to obtain the high-order sub-mantissa to be shifted; and performing order shifting on the high-order sub-mantissa to be shifted by utilizing the step difference to obtain a high-order sub-mantissa order shifting result.

In one embodiment, the addition processing submodule includes a processing subunit that is: at least N addition units; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

the addition processing submodule is specifically used for splitting the mantissa multiplication results of the two multipliers to obtain a high-order mantissa multiplication result and a low-order mantissa multiplication result;

calling any adding unit, and executing adding operation on the low-order mantissa pair-order result and the low-order mantissa multiplication result to obtain a first adding result and a carry;

and calling any other addition unit, and executing addition operation on the higher mantissa pair-order result, the higher mantissa multiplication result and the carry to obtain a second addition result.

In one embodiment, the leading zero submodule includes a processing subunit that is: at least N leading zero units; the input bit width of the leading zero unit is larger than the tail digital width of the first precision floating point number and smaller than 2 times of the tail digital width of the first precision floating point number;

the leading zero sub-module is specifically configured to call any leading zero unit, and perform leading zero processing on the first addition result to obtain the leading zero number of the first addition result;

calling any other leading zero unit, and carrying out leading zero processing on the second addition result to obtain the leading zero number of the second addition result;

under the condition that the leading zero number of the second addition result is the bit width of the second addition result, determining that the leading zero result of the addition result is the sum of the leading zero number of the first addition result and the bit width of the second addition result; in the case where the leading zero number of the second addition result is not the bit width of the second addition result, the leading zero result of the addition result is the leading zero number of the second addition result.

In one embodiment, the processing subunit of the shift sub-module further comprises: at least N normalized shift units; the input bit width of the normalization shift unit is larger than the tail digital width of the first precision floating point number and smaller than 2 times of the tail digital width of the first precision floating point number;

The shift sub-module is used for calling any normalization shift unit, carrying out normalization shift on the first addition result according to the leading zero result of the addition result to obtain a first normalization mantissa and left shift-out data;

calling any other normalization shift unit, combining the left shift-out data with a second addition result to obtain a second addition result to be normalized, and performing normalization shift on the second addition result to be normalized according to a leading zero result of the addition result to obtain a second normalization mantissa;

and the method is used for combining the first normalized mantissa and the second normalized mantissa to obtain a final mantissa.

In one embodiment, the data obtaining module is specifically configured to obtain N-1 groups of to-be-multiplied and added calculation data with a type of the second precision floating point number when the to-be-multiplied and added calculation data is the second precision floating point number;

for each group of to-be-multiplied and added calculation data, the following operations are respectively executed:

shaping the mantissa of each of the two multipliers to satisfy the bit width of the multiplication unit input requirement; inputting mantissas of the two multipliers after shaping into a multiplication unit;

the multiplication processing submodule is used for calling N multiplication units of input data, and performing multiplication operation on the input data to obtain mantissa multiplication results of two multipliers in N groups of to-be-multiplied addition calculation data.

In one embodiment, the shift submodule includes a processing subunit that is: at least N antipodal shift units; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the input bit width of the opposite-order shifting unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

the addition processing submodule is specifically used for respectively determining the product of two multipliers and the step difference between addends for each group of to-be-multiplied addition calculation data;

the shifting sub-module is used for calling N antipodal shifting units, and for N groups of to-be-multiplied addition calculation data, antipodal shifting is carried out on mantissas of the addends by utilizing step differences, and N mantissa antipodal results are obtained;

the addition processing sub-module is specifically configured to call N addition units, perform an addition operation on the mantissa pair-order result and the mantissa multiplication results of the two multipliers for N groups of to-be-multiplied addition calculation data, and obtain N mantissa results.

In one embodiment, the leading zero submodule includes a processing subunit that is: at least N leading zero units; the processing subunit of the shift sub-module further includes: at least N normalized shift units; the input bit width of the leading zero unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width, and the input bit width of the normalization shift unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width;

The leading zero sub-module is specifically used for calling N leading zero units, leading zero processing is carried out on N mantissa results, and N leading zero processing results are obtained;

the shift sub-module is specifically configured to invoke N normalization shift units, perform normalization shift on N mantissa results according to N leading zero processing results for N groups of to-be-multiplied and added calculation data, and obtain N final mantissas.

In one embodiment, the arithmetic logic unit is further configured to process a multiply-add operation on an integer, wherein the integer is any integer having a bit width no greater than 1/2 of the first precision floating point number mantissa bit width; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

the data acquisition module is specifically used for acquiring N-1 groups of to-be-multiplied addition calculation data with the type of the integer under the condition that the to-be-multiplied addition calculation data are the integer;

shaping each of the two multipliers to a bit width that meets the input requirements of the multiplication unit; inputting the two shaped multipliers into a multiplication unit;

The multiplication processing submodule is used for calling N multiplication units of input data, and performing multiplication operation on the input data to obtain multiplication results of two multipliers in N groups of to-be-multiplied addition calculation data;

and the addition processing sub-module is used for calling N addition units, and respectively executing addition operation on the multiplication results of the addend and the two multipliers for N groups of to-be-multiplied addition data to obtain the final result of the to-be-multiplied addition calculation data for N groups.

According to a second aspect of the present disclosure, an arithmetic processing method is provided, applied to an arithmetic logic unit, for processing multiply-add operations of a first precision floating point number and a second precision floating point number, where the second precision floating point number is any precision floating point number with a tail digital width not greater than 1/2 of a tail digital width of the first precision floating point number, and the arithmetic logic unit includes a data acquisition module and an operation module, where the operation module includes a multiplication processing sub-module, an addition processing sub-module, a shift sub-module, and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively;

the data acquisition module identifies the floating point number precision type of the to-be-multiplied addition calculation data;

any submodule in the operation module calls a local processing subunit to process the calculation data to be multiplied and added according to the floating point number precision type to obtain a processing result; any processing subunit in any sub-module is used for processing a group of second precision floating point numbers, and a plurality of processing subunits in any sub-module are used for carrying out joint processing on a group of first precision floating point numbers.

According to a third aspect of the present disclosure, there is provided a chip comprising an arithmetic logic unit in any of the embodiments of the first aspect.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising the chip of the third aspect.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

FIG. 1 is a schematic diagram of various floating point numbers and integer formats provided by one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a multiplier-adder operation provided in one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an arithmetic logic unit according to one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of the operation of a multiplication submodule according to one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the operation of a shift submodule according to one embodiment of the present disclosure;

FIG. 6 is a schematic diagram illustrating the operation of an adder-submodule according to one embodiment of the present disclosure;

fig. 7 is a schematic operation diagram of a leading zero sub-module according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of an operation module according to an embodiment of the disclosure;

Fig. 9 is a schematic structural diagram of another operation module according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of another operation module according to an embodiment of the disclosure;

fig. 11 is a flowchart of an operation processing method according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

Currently, a high-performance chip generally needs to support multiply-add computing operations (fused multiply-add FMA, fused multiply-add MAC, or multiply-accumulate) of multiple precision floating point numbers, and the chip is usually preconfigured with multiple arithmetic logic units (arithmetic and logic unit) in a hardware form, i.e., a combinational logic circuit for implementing multiple groups of arithmetic operations and logic operations, abbreviated as ALU, for computing different data, where the ALU includes a multiply-add device, an adder, and the like, and is dedicated for performing specific computation on the data. Here, the multiplier-adder is usually a multiplier-adder dedicated to some data, for example, a multiplier-adder for performing a multiplier-adder calculation on a single-precision floating point number cannot perform a multiplier-adder calculation on a double-precision floating point number, and an ALU for performing a multiplier-adder calculation on an integer cannot perform a multiplier-adder calculation on a floating point number.

Floating point numbers are a digital representation in which various real numbers can be expressed using floating point numbers, and various methods have been proposed in the development of computer systems to express real numbers, such as fixed point numbers relative to floating point numbers, in which decimal points are fixed somewhere in the middle of all the digits of a real number. For example, the expression of currency may be used in this way, e.g. 99.00 or 00.99 may be used to express currency with two decimal places. However, since the fixed position of the decimal point is unfavorable for expressing particularly large or particularly small numbers in the fixed-point number, most computer systems currently use the expression mode of the floating-point number to express real numbers.

In floating point numbers, real numbers are expressed by a Mantissa (Mantissa), a radix (Base), an Exponent (exponents), and a sign representing positive and negative. For example, 121.1 may be expressed as 1.211 ×10 ² Where 1.211 is mantissa, 10 is radix, 2 is exponent, floating point number expresses the effect of floating decimal point with exponent, thus allowing expression of a wider range of real numbers.

Since the numerical expressions in a computer are all binary-based, the base of a floating point number defaults to 2 in a computer, and the number of digits of a mantissa is referred to as the precision of a floating point number. For example, floating point number 1.001101 ×2 ⁴ The accuracy of (2) is 7.

Various floating point formats are specified in IEEE (institute of electrical and electronics engineers), including FP64, FP32, TF32, FP16, BF16 in common. In artificial intelligence and high performance computing, in addition to the floating point number, an integer is also required to be computed, and a common integer is typically INT8.

The general floating point number and integer forms described above are shown in FIG. 1. All precision floating point representations are divided into three parts: sign bit [ (x-ray) symbol ]sign, s), exponent bits (exponents, e) and mantissa bits (fraction, f or mantissa, m). With these three fields, the two-level floating point number can be represented as (-1) ^s ×1.f×2 ^e-b Where b is bias, the choice of b is related to the bit width of e, i.e. b=2 ^{length（e）-1} -1。

Taking FP32 as an example, the floating point number has 8 digits, 1 sign, and 24 mantissa digits (with one hidden bit). Other forms of floating point numbers and so on. The integer INT8 is 8 bits since it does not distinguish between sign bits, mantissa bits and exponent bits.

The floating point number and integer format are described above, and the multiply-add operation is described below.

The multiply-add operation described herein includes FMA and MAC, where FMA and MAC are similar to the calculation operation used to perform a x B + C calculation, i.e., two multipliers are multiplied and added to an adder. Wherein A, B, C may all be floating point numbers of some precision or all be integers.

The FMA or MAC operation for floating point numbers can be generally categorized as follows:

1. floating point number splitting: the floating point number A, B, C to be used for calculation is split according to sign bit SING_A/B/C, exponent bit EXP_A/B/C and mantissa bit MANT_A/B/C, and the different field bits are sent to a later calculation component for calculation.

2. Index comparison:

1) The exponents are added and a and B are multiplied to give AB, the exponent exp_ab=exp_a+exp_b of AB.

2) Step difference is calculated, and the exponential step difference EXP_COMP of AB and C is obtained by calculating the step difference EXP_A+EXP_B-EXP_C=EXP_COMP.

3. Mantissa multiplication: mantissa of AB is mant_ab= {1, mant_a } × {1, mant_b }, { } is a bit-splice.

4. Mantissa-to-order shifting: AB and C are added (mantissa added) with the same exponent for both numbers, which requires shifting the mantissa {1, man_c } of C according to the previously obtained step exp_comp to obtain man_shift_c.

If EXP_COMP is greater than or equal to 0, the mantissa is required to be shifted right (the decimal point is shifted left) |EXP_COMP|;

if EXP_COMP < 0, then the mantissa needs to be shifted left (the decimal point shifted right) |EXP_COMP|.

The opposite-order shifts can be unified into right shift through certain conversion.

5. Mantissa addition: man_abc=man_ab+man_shift_c.

6. Leading zero detection/prediction: if the step difference between AB and C is small (1) and the sign bits of AB and C are different, MANT_ABC may be a denormalization number of less than 0 (e.g., 0.0001xxx … xxx).

Leading zero detection is to detect how many 0's, lead_zero's, are before the first non-0 value of man t_abc.

Leading zero prediction can be performed on leading 0 of MANT_ABC while mantissa addition, and the leading zero prediction generally consists of an input coding logic and leading zero detection logic.

7. Normalized shift: the left shift of the lead_zero bits is performed on MANT_ABC based on the previously obtained leading zero lead_ZEROS, resulting in normalized representation mantissa MANT_RN (1. Xxx … xxx) and corresponding adjustment of MANT_ABC exponent bits.

8. Rounding and result generation, if the mantissa is longer than the specified number of bits, rounding is required. The rounding off generates final result data sing_ Y, EXP _ Y, MANT _y.

9. Exception processing, the generated data may be an invalid number nan_y or an infinite number inf_y, which needs to be detected and identified.

10. Floating point number merging, merging sign bits, exponent bits and mantissa bits, y= { sing_y, exp_y, man_y }.

The integer multiply-add operation is much simpler and mainly includes an integer multiply calculation and an integer add calculation.

Currently, if a chip wants to support multiply-add operations for multiple floating-point numbers (e.g., 4) and integers, it is necessary to deploy 4 multiply-add devices for the 4 floating-point numbers and 1 multiply-add device for the integer, respectively. It can be seen that if the chip is intended to perform the above-described computing operation, more hardware needs to be deployed on the chip, which occupies more chip area.

In view of the above problems, the present disclosure provides an arithmetic logic unit, where each computing unit in the arithmetic logic unit can multiplex multiply-add operations of floating-point numbers with multiple precision, so that disposing an arithmetic logic unit on a chip can process multiply-add operations of floating-point numbers with multiple precision at the same time, and thus, the chip area can be effectively saved.

Based on the inventive concept, as shown in fig. 3, the present disclosure proposes an arithmetic logic unit for processing multiply-add operations of a first precision floating point number and a second precision floating point number, wherein the second precision floating point number is any precision floating point number having a mantissa bit width not greater than 1/2 of the mantissa bit width of the first precision floating point number, the arithmetic logic unit comprising: the data acquisition module 310 and the operation module 320, wherein the operation module 320 at least includes a multiplication processing sub-module 3201, an addition processing sub-module 3202, a shift sub-module 3203, and a leading zero sub-module 3204. Each sub-module in the operation module comprises a plurality of processing sub-units respectively; specifically, the multiplication processing sub-module 3201 includes processing sub-units of at least 2N multiplication units and one accumulation unit, where N is a positive integer not less than 2. The addition processing sub-module 3202 includes processing sub-units of at least N addition units; the shift sub-module 3203 includes at least N shift units as processing sub-units; the leading zero sub-module 3204 includes at least N leading zero units as processing sub-units.

In the arithmetic logic unit, a data acquisition module is used for acquiring to-be-multiplied addition calculation data;

By adopting the mode, any sub-module in the operation module can be multiplexed in the multiplication and addition operation of the first precision floating point number and the second precision floating point number, and then the multiplication and addition operation of the multiple precision floating point numbers can be processed only by disposing the arithmetic logic unit on a chip, and the multiplication and addition device is not required to be disposed on the chip aiming at the multiple precision floating point numbers respectively, so that the area of the chip can be effectively saved.

The following describes the processing of the first precision floating point number and the second precision floating point number by the arithmetic logic unit, respectively.

First, a procedure of the arithmetic logic unit for processing the first precision floating point number will be described.

The data acquisition module is specifically configured to acquire the to-be-multiplied and added calculation data from the upstream device, and when the upstream device sends the to-be-multiplied and added calculation data to the data acquisition module, the floating point number precision type of the to-be-multiplied and added calculation data is generally provided at the same time, so that the data acquisition module acquires the to-be-multiplied and added calculation data and obtains the floating point number precision type of the to-be-multiplied and added calculation data.

As mentioned above, the second precision floating point number in this disclosure is any precision floating point number having a mantissa bit width no greater than 1/2 the mantissa bit width of the first precision floating point number, then when the first precision floating point number is FP64, the second precision floating point number may be FP32, TF32, FP16, BF16. When the first precision floating point number is FP32, the second precision floating point number may be TF32, FP16, BF16. The present disclosure is not limited to the types of the first precision floating point number and the second precision floating point number, and those skilled in the art may set according to actual requirements. The first precision floating point number FP32 is described below as an example.

After the data acquisition module determines that the floating point number precision type of the to-be-multiplied and added calculation data is the first precision floating point number, the data acquisition module can send a signal representing the floating point number precision type of the first precision floating point number to the operation module so that the operation module knows that the to-be-multiplied and added calculation data is the first precision floating point number, and each sub-module can process the to-be-multiplied and added calculation data of the first precision floating point number.

The multiplication processing sub-module processes the first precision floating point number as follows.

The multiplication processing submodule provided by the present disclosure may include 2N multiplication units with the same input bit width and one accumulation unit, where N is a positive integer not less than 2. In order to enable the multiplication unit to process both the first precision floating point number and the second precision floating point number, the input bit width of the multiplication unit is set to be not less than 1/2 of the tail bit width of the first precision floating point number and less than the tail bit width of the first precision floating point number;

After determining that the to-be-multiplied and added calculation data is the first precision floating point number, the data acquisition module splits the mantissa of each multiplier of the two multipliers to obtain two sub-mantissas; any sub-tail digit width is equal and meets the input requirement of the multiplication unit; combining the sub-mantissas corresponding to the two multipliers to obtain four groups of combined results, wherein each group of combined results comprises two sub-mantissas corresponding to different multipliers; inputting the four groups of combined results to four multiplication units respectively;

and the multiplication processing sub-module is used for calling four multiplication units of the input data to execute multiplication operation on the input data, and calling the accumulation unit to execute accumulation operation on the output of the four multiplication units to obtain the mantissa multiplication result of the two multipliers.

In addition, the operations of splitting and combining the mantissas of each of the two multipliers can also be performed by the multiplication processing sub-module, and the data acquisition module only needs to inform the operation module or inform the multiplication processing sub-module of the type of the data to be multiplied and added.

As shown in fig. 4, a schematic diagram of the operation of a multiplication processing sub-module according to the present disclosure is provided.

As shown in the figure, after determining that the to-be-multiplied and added calculation data is the first precision floating point number, the data acquisition module splits the mantissa data { A2, A1} and { B2, B1} of the two multipliers with the bit width of 2n into a high n-bit sub-mantissa and a low n-bit sub-mantissa, and combines the sub-mantissas corresponding to the two multipliers to obtain four groups of combined results A1B1, A2B1, A1B2 and A2B2. Meanwhile, four groups of combined results are sent to 4 n-bit wide multiplication units for calculation, when the multiplication processing submodule determines that the data to be multiplied and added are first-precision floating point numbers, four multiplication units of the input data can be called for calculating the input data to obtain calculation results of A1B1, A2B1, A1B2 and A2B2, and the accumulation unit adds {2n ' h0, A1B }, { n ' h0, A2B1, n ' h0}, { n ' h0, A1B2, n ' h0}, { A2B2, 2n ' h0} to obtain mantissa multiplication results of two multipliers, wherein { } is a bit splice, and n ' h0 represents n-bit 0. The data acquisition module may send a signal double to each sub-module of the operation module, where double is 0 to indicate that the to-be-multiplied and added data is the second precision floating point number, and double is 1 to indicate that the to-be-multiplied and added data is the first precision floating point number.

In view of the above, when processing to-be-multiplied data of a first precision floating point number and multiplying mantissas of two multipliers, four multiplication units and one accumulation unit are required to perform joint processing. Therefore, the arithmetic logic unit proposed in the present disclosure may process multiplication in the to-be-multiplied-and-added computation of 2N/4 groups of first precision floating point numbers in parallel, and in a specific embodiment, in order to reduce the occupied area of the arithmetic logic unit as much as possible, the N may be 2, that is, the multiplication processing submodule includes 4 multiplication units with identical input bit widths. The arithmetic logic unit may then be used to process multiply-add operations for a set of first precision floating point numbers.

The addition processing sub-module and the shift sub-module can perform the opposite-order shift on the mantissa of the addend while the multiplication processing sub-module obtains the mantissa multiplication result of the two multipliers aiming at the to-be-multiplied addition calculation data of the first precision floating point number. The shift submodule provided by the present disclosure includes a processing subunit that is: at least N antipodal shift units. In order to enable the opposite-order shifting unit to process the first precision floating point number or the second precision floating point number, the input bit width of the opposite-order shifting unit is set to be not less than 1/2 of the tail bit width of the first precision floating point number and less than the tail bit width of the first precision floating point number.

The shift sub-module processes the first precision floating point number as follows.

The addition processing submodule is specifically used for determining the product of two multipliers and the step difference between addends under the condition that the to-be-multiplied addition calculation data is the first precision floating point number;

the shift sub-module is specifically configured to split the mantissa of the addend to obtain a high-order sub-mantissa and a low-order sub-mantissa when the to-be-multiplied addition calculation data is the first precision floating point number, where the bit widths of the high-order sub-mantissa and the low-order sub-mantissa are the same;

when the product of the two multipliers is larger than the product of the addends, namely, when the product of the two multipliers and the step difference between the addends are larger than zero, any pair of step shifting units are called, step shifting is carried out on the high-order child mantissas by utilizing the step difference, and a high-order child mantissa pair step result and right shift-out data are obtained;

and calling any other opposite-order shifting unit, combining the right shift-out data with the low-order sub-mantissa to obtain the low-order sub-mantissa to be shifted, and carrying out opposite-order shifting on the low-order sub-mantissa to be shifted by using the step difference to obtain a low-order sub-mantissa opposite-order result.

Under the condition that the product of the two multipliers is smaller than the product of the addend, namely, the product of the two multipliers and the step difference between the addend are smaller than zero, any pair of step shifting units are called, step shifting is carried out on the low-order sub-mantissa by using the step difference, and a low-order sub-mantissa step-to-step result and left shift shifted-out data are obtained;

Specifically, the addition processing submodule is specifically configured to determine a product of two multipliers and a step difference between addends when the to-be-multiplied addition calculation data is the first precision floating point number, and calculate the step difference between the product of the two multipliers and the addends, where the step of the product of the multipliers, i.e., the exponent, and the exponent of the addend are subjected to difference. As can be seen from fig. 1, the exponent widths of the precision floating point numbers have small differences, so that the exponent adding units of the precision floating point numbers can be directly multiplexed, as long as the bit widths of the exponent adding units are equal to or greater than the bit widths of the first precision floating point numbers. The addition processing submodule in the present disclosure includes both a mantissa addition unit that performs calculation on mantissas and an exponent addition unit that performs calculation on exponents. When calculating the product of the two multipliers and the step difference between the addends, the exponential addition unit is specifically adopted to execute, according to the above, it can be known that the product of the two multipliers and the step difference between the addends can be greater than or equal to zero or less than zero, when the product is greater than zero, the mantissa of the addends needs to be shifted to the right, and when the product is less than zero, the mantissa of the addends needs to be shifted to the left. In addition, the shift of the steps may be unified into the shift of the right through a certain conversion, and the disclosure will not be described in detail with reference to the related art.

The shift submodule can be processed as shown in fig. 5, and a working schematic diagram of the shift submodule is provided for the present disclosure instead.

The shift sub-module may determine whether to shift the mantissa of the first precision floating point number or shift the mantissa of the second precision floating point number according to the representation signal double sent by the data acquisition module.

When double is 1, determining that the input data is mantissa { A2, A1} of the first precision floating point number addend, wherein the SHIFT bit number is identified as sh2 (step difference) and sh1 (step difference), the SHIFT bit number is identified as sh 2=sh1, the SHIFT submodule calls a SHIFT unit SHIFT2 to SHIFT n bit A2 of the high-order mantissa according to sh2 to obtain a high-order mantissa pair-order result B2, calls another SHIFT unit SHIFT1 to SHIFT n bit A1 of the low-order mantissa according to sh1, wherein the SHIFT data shifted to the right in the disclosure is referred to as SHIFT data (when the step difference is greater than zero), and also serves as the input of SHIFT1 to obtain a low-order mantissa pair-order result A2, and the final SHIFT result is { B2, B1}.

After the addition processing submodule and the shift submodule perform the order shifting on the mantissa of the addend, the addition processing submodule can add the mantissa multiplication results of the two multipliers and the mantissa of the addend. The processing subunit included in the addition processing submodule provided by the present disclosure is: at least N addition units. In order to enable the addition unit to process the first precision floating point number and the second precision floating point number, the input bit width of the addition unit is set to be not smaller than the tail bit width of the first precision floating point number and smaller than 2 times of the tail bit width of the first precision floating point number;

The addition processing submodule processes the first precision floating point number as follows.

It will be appreciated that the addition unit described herein is specifically a mantissa addition unit that processes mantissas.

Fig. 6 is a schematic diagram illustrating the operation of an addition processing submodule according to the present disclosure.

Likewise, the data acquisition module may identify whether the data to be multiplied is a first precision floating point number or a second precision floating point number with a representation signal double.

When receiving double 1, the addition processing sub-module splits the mantissa multiplication results { A2, A1} of two multipliers with 2n bit width to obtain a high-order mantissa multiplication result A2 and a low-order mantissa multiplication result A1. Calling an n-bit wide addition unit ADD1, and executing addition operation on the low-order mantissa pair-order result B1 and the low-order mantissa multiplication result A1 to obtain a first addition result S1 and a carry C1; and calling another n-bit wide addition unit ADD2, and performing addition operation on the high-order sub-mantissa pair order result B2, the high-order mantissa multiplication result A2 and the carry C1 to obtain a second addition result { C2, S2}. The addition units ADD1, ADD2 may employ a high-speed addition unit structure such as a carry-ahead addition unit in consideration of the rate of the addition units.

When the addition processing submodule adds the mantissa multiplication results of the two multipliers and the mantissa of the addend, the leading zero submodule can conduct leading zero processing on the addition result. The processing subunit included in the leading zero submodule provided by the present disclosure is: at least N leading zero units. In order to enable the leading zero unit to process the first precision floating point number or the second precision floating point number, the input bit width of the leading zero unit is set to be larger than the tail bit width of the first precision floating point number and smaller than 2 times of the tail bit width of the first precision floating point number;

the first precision floating point number is processed by the leading zero submodule as follows.

The leading zero sub-module is specifically used for calling any leading zero unit, and leading zero processing is carried out on the first addition result to obtain the leading zero number of the first addition result;

Wherein the leading zero processing in the present disclosure includes leading zero detection or leading zero prediction, which is not limited by the present disclosure.

Fig. 7 is a schematic diagram illustrating the operation of a leading zero sub-module according to the present disclosure.

And after receiving double 1, the leading zero sub-module calls one leading zero unit LZD2 to process the high n bit A2 (second addition result) to obtain the leading zero number B2 of the second addition result, and calls the other leading zero unit LZD1 to process the low n bit A1 (first addition result) to obtain the leading zero number B1 of the first addition result. If the high n bit is all zero, the leading zero number of the large bit width number { A2, A1} is n+B1, and if the high n bit is not all zero, the leading zero number of the large bit width number is B2.

After the leading zero sub-module carries out leading zero processing on the addition result, the shifting sub-module can carry out normalized shifting on the mantissa result to obtain the final mantissa. The processing subunit of the shift sub-module proposed in the present disclosure further includes: at least N normalized shift units. In order to enable the normalization shift unit to process the first precision floating point number or the second precision floating point number, the input bit width of the normalization shift unit is set to be larger than the tail bit width of the first precision floating point number and smaller than 2 times of the tail bit width of the first precision floating point number.

The shift sub-module is specifically used for calling any normalization shift unit, and performing normalization shift on the first addition result according to the leading zero result of the addition result to obtain a first normalization mantissa and left shift-out data;

and combining the first normalized mantissa and the second normalized mantissa to obtain a final mantissa.

Referring to FIG. 5, for example, when double is 1, it indicates that the data to be multiplied and added is the first precision floating point number.

The SHIFT submodule calls a normalized SHIFT unit SHIFT1 to SHIFT the low n bit A1 (first addition result), obtain B1 (second normalized mantissa) and SHIFT out data to the left according to sh1 (leading zero result of addition result), calls another normalized SHIFT unit SHIFT2 to SHIFT the high n bit A2 (second addition result), SHIFT out data to the left according to sh2 (leading zero result of addition result), and also takes the SHIFT1 as input of SHIFT2 to obtain B2 (second normalized mantissa), and the final SHIFT result is { B2, B1} which is the final mantissa.

In combination with the above, when processing the to-be-multiplied and added calculation data of a group of first precision floating point numbers, two opposite-order shifting units and two normalization shifting units are needed to perform joint processing in the shifting sub-module, two adding units are needed to perform joint processing in the adding sub-module, and two leading zero units are needed to perform joint processing in the leading zero sub-module. Therefore, the arithmetic logic unit proposed in the present disclosure may process multiplication computation in the to-be-multiplied addition computation of N/2 groups of first precision floating point numbers in parallel, and in a specific embodiment, in order to reduce the occupied area of the arithmetic logic unit as much as possible, N may be 2, that is, the addition unit, the leading zero unit, the opposite-order shift unit, and the normalization shift unit are all 2. The arithmetic logic unit may then be used to process multiply-add operations for a set of first precision floating point numbers.

The process of processing the first precision floating point number by the arithmetic logic unit is described above, and it can be seen that, in the operation module of the arithmetic logic unit, multiple processing sub-units in any sub-module can perform joint processing for a group of first precision floating point numbers, so as to process multiplication and addition operations of the first precision floating point numbers.

The process by which the arithmetic logic unit processes the second precision floating point number is described below. The multiplication processing sub-module processes the first precision floating point number as follows.

The data acquisition module is specifically used for acquiring N-1 groups of to-be-multiplied addition calculation data with the type of the second precision floating point number under the condition that the to-be-multiplied addition calculation data are the second precision floating point number;

shaping the mantissa of each of the two multipliers to a bit width that meets the input requirements of the multiplication unit; inputting mantissas of the two multipliers after shaping into a multiplication unit;

and the multiplication processing submodule is used for calling N multiplication units of the input data, and performing multiplication operation on the input data to obtain mantissa multiplication results of two multipliers in N groups of to-be-multiplied addition calculation data.

For example, in connection with the above embodiment, the N may be 2, i.e. the multiplication processing sub-module comprises 4 multiplication units. And the data acquisition module can acquire 1 group of the to-be-multiplied addition calculation data with the type of the second precision floating point number again under the condition that the to-be-multiplied addition calculation data is the second precision floating point number.

After the mantissa of the first precision floating point number is split into two parts, each part can meet the requirement of the input bit width of the multiplication unit, and the mantissa bit width of the second precision floating point number is not more than 1/2 of the mantissa bit width of the first precision floating point number, so that the input bit width of each multiplication unit is more than or equal to the mantissa bit width of the second precision floating point number. Therefore, when the mantissa bit width of the second precision floating point number is smaller than the input bit width of the multiplication unit, the mantissa of each multiplier may be shaped, for example, 0 is complemented in the high order of the mantissa, so that the bit width of the mantissa satisfies the input bit width of the multiplication unit. After integer, each multiplication unit may be configured to process the multiplication of the mantissas of the two multipliers in the set of second precision floating point numbers to obtain the mantissa multiplication result of the two multipliers. The multiplication unit may be directly configured to process multiplication computations of mantissas of two multipliers in the set of second precision floating-point numbers when the mantissa bit width of the second precision floating-point number is equal to the input bit width of the multiplication unit.

Because N groups of to-be-multiplied calculation data are simultaneously acquired, the data acquisition module respectively inputs mantissas of two multipliers after the integer of the N groups of to-be-multiplied calculation data to the multiplication units, therefore, the N multiplication units are all input with data, the multiplication processing submodule calls the N multiplication units of the input data after determining that the to-be-multiplied calculation data is the second precision floating point number, and performs multiplication operation on the input data, so that the mantissa multiplication result of the two multipliers in the N groups of to-be-multiplied calculation data can be obtained.

After N multiplication results are obtained for mantissas of two multipliers in N groups of to-be-multiplied calculation data, the shift submodule and the addition processing submodule process the second precision floating point number as follows. As described above, the shift submodule in the present disclosure includes the processing subunits as follows: n opposite-order shifting units; the addition processing submodule comprises processing subunits as follows: n addition units. The opposite-order shifting unit is not smaller than 1/2 of the tail digital width of the first precision floating point number and smaller than the tail digital width of the first precision floating point number; the input bit width of the addition unit is not smaller than the tail bit width of the first precision floating point number and is smaller than 2 times of the tail bit width of the first precision floating point number;

When the product of two multipliers and the step difference between addends are respectively determined for each group of to-be-multiplied addition calculation data, the calculation can be specifically performed by adopting an exponential addition unit.

When the shift submodule works, as shown in fig. 5, when N is 2, the shift submodule comprises two opposite-order shift units, and the shift submodule can determine whether to shift the mantissa of the first precision floating point number or the mantissa of the second precision floating point number according to the representation signal double sent by the data acquisition module.

When double is 0, the input data is determined to be the mantissa of the second precision floating point number addend. The shifting submodule calls a contrast shifting unit SHFIT2 and a contrast shifting unit SHFIT1 to work independently, and generates shifting results B2 and B1 corresponding to n-bit widths according to input n-bit width data A2 and A1 and corresponding shifting bit number marks sh2 and sh1, namely mantissa contrast results are obtained for to-be-multiplied addition calculation data of two groups of second precision floating point numbers.

When the addition processing submodule works, as shown in fig. 6, when N is 2, the addition processing submodule comprises two addition units, and the addition processing submodule can determine whether the data to be multiplied and added are the first precision floating point number or the second precision floating point number according to the representation signal double sent by the data acquisition module. When double is 0, it is determined to be the second precision floating point number. Then 2 addition units are called, and for 2 groups of to-be-multiplied addition calculation data, addition operation is respectively carried out on the mantissa pair-order result and the mantissa multiplication result of the two multipliers, so as to obtain 2 mantissa results S1 and S2.

And the leading zero sub-module and the shifting sub-module are also used for processing the N mantissa results to obtain N final mantissas after the N mantissa results are obtained by carrying out addition operation on the mantissa pair-order result and the mantissa multiplication results of the two multipliers aiming at the N groups of to-be-multiplied addition calculation data. As described above, the leading zero submodule in the present disclosure includes the processing subunits as follows: at least N leading zero units; the processing subunit of the shift sub-module further comprises: at least N normalized shift units. The input bit width of the leading zero unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width, and the input bit width of the normalization shift unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width.

Specifically, the leading zero sub-module is specifically configured to call N leading zero units, and perform leading zero processing on the N mantissa results to obtain N leading zero processing results;

As shown in fig. 7, when N is 2, the leading zero submodule includes two leading zero units, and when double is 0, the leading zero submodule determines that the input data is the mantissa of the second precision floating point number adder. Leading zero submodule call, leading zero unit LZD2 and leading zero unit LZD1 work independently, and leading zero results B2 and B1 with corresponding n-bit width are generated according to inputs A2 and A1.

As further shown in fig. 5, when N is 2, the shift submodule includes two normalized shift units, and when double is 0, the to-be-multiplied data is determined to be the second precision floating point number. The shift submodule calls a normalization shift unit SHFIT2 and a normalization shift unit SHFIT1 to work independently, and generates shift results B2 and B1 corresponding to n-bit widths according to input n-bit width data A2 and A1 and corresponding shift bit number identifiers sh2 and sh1, namely two final mantissas are obtained according to-be-multiplied and added calculation data of two groups of second-precision floating point numbers.

In combination with the above process of processing the second precision floating point number, that is, in the arithmetic logic unit provided in the present disclosure, any processing subunit in any submodule is configured to process a group of second precision floating point numbers, so that the arithmetic logic unit can process at least N groups of second precision floating point numbers to be multiplied and added in parallel.

In one embodiment, the arithmetic logic unit further comprises: and the rounding module is used for rounding and generating a result, and if the mantissa is longer than the specified bit number, rounding is needed. The rounding off generates final result data sing_ Y, EXP _ Y, MANT _y. And the exception processing module is used for detecting whether the generated data is an invalid number NaN_Y or an infinite number INF_Y and identifying. And the floating point number merging module is used for merging the sign bit, the exponent bit and the mantissa bit, and obtaining a final floating point number form result by Y= { SING_Y, EXP_Y and MANT_Y }. Specific implementations of the rounding module, exception handling module, and floating point number merge module may refer to the related art, which is not described in detail in this disclosure.

The arithmetic logic unit can process multiplication and addition operations of integers besides the first precision floating point number and the second precision floating point number, wherein the integers are any integers with bit widths not larger than 1/2 of the tail bit width of the first precision floating point number; as described above, the multiplication processing submodule includes processing subunits of: at least 2N multiplication units with the same input bit width and an accumulation unit, wherein N is a positive integer not less than 2; the addition processing submodule comprises processing subunits as follows: at least N addition units; the input bit width of the addition unit is not smaller than the tail bit width of the first precision floating point number and is smaller than 2 times of the tail bit width of the first precision floating point number.

As shown in FIG. 1, if the first precision floating point number is FP32 or FP64, the integer may be INT8.

For example N may be 2, i.e. the multiplication processing sub-module comprises 4 multiplication units. The data acquisition module may acquire 1 set of the to-be-multiplied and added calculation data with the type of integer again under the condition that the to-be-multiplied and added calculation data is integer.

After the mantissa of the first precision floating point number is split into two parts, each part can meet the requirement of the input bit width of the multiplication unit, and the integer bit width is not more than 1/2 of the mantissa bit width of the first precision floating point number, so that the input bit width of each multiplication unit is more than or equal to the integer bit width. Thus, when the bit width of the integer is smaller than the input bit width of the multiplication unit, each integer may be shaped, for example, 0 is added in the upper order, so that the bit width of the integer satisfies the input bit width of the multiplication unit. After shaping, each multiplication unit may be used to process the multiplication of two multipliers in a set of integers to obtain the multiplication result of the two multipliers. When the bit width of an integer is equal to the input bit width of the multiplication unit, the multiplication unit may be used directly for the multiplication calculation of two multipliers in a set of integers.

Because N groups of to-be-multiplied calculation data are acquired at the same time, the data acquisition module inputs two multipliers of the N groups of to-be-multiplied calculation data after shaping to one multiplication unit respectively, therefore, the N multiplication units are all input with data, the multiplication processing sub-module calls the N multiplication units of the input data after determining that the to-be-multiplied calculation data are integers, and performs multiplication operation on the input data, so that multiplication results of the two multipliers in the N groups of to-be-multiplied calculation data can be obtained.

Because the addition unit can be directly used for processing the addition operation of a group of integers, the addition processing submodule can call N addition units to respectively execute the addition operation on the multiplication results of the addend and the two multipliers aiming at N groups of to-be-multiplied addition data to obtain the final result aiming at N groups of to-be-multiplied addition calculation data.

In summary, by adopting the above manner, the arithmetic logic unit provided in the present disclosure may process N groups of integers to be multiplied and added in parallel.

In combination with the above processing procedure of the arithmetic logic unit on the first precision floating point number, the second precision floating point number and the integer, the arithmetic logic unit provided by the disclosure can multiplex multiply-add operations of the first precision floating point number, the second precision floating point number and the integer. The arithmetic logic unit proposed by the present disclosure is described below in connection with several specific embodiments.

As shown in fig. 8, a schematic diagram of a specific operation module proposed in the present disclosure is taken as an example, where the first precision floating point number is FP32 and the second precision floating point number is FP 16. Since the mantissa bit width 24 bits of FP32 is greater than 2 times the mantissa bit width 11 bits of FP16, the input bit width of the multiplication unit may be set to 1/2 of the mantissa of FP32, so that four multiplication units (mul 0, mul1, mul2, mul 3) +1 accumulation units (part product add) in the multiplication processing sub-module may be used to process the to-be-multiplied addition calculation data of one set of FP32, and the to-be-multiplied addition calculation data of four sets of FP 16. The addition processing submodule comprises two addition units, the input bit width of each addition unit is the mantissa bit width of the FP32, and the processing of the to-be-multiplied addition calculation data of the two groups of FP16 and the to-be-multiplied addition calculation data of the 1 group of FP32 can be realized. Similarly, the leading zero sub-module comprises two leading zero units, the input bit width of each leading zero unit can be 1bit larger than the mantissa bit width of the corresponding FP32, and the processing of the to-be-multiplied and added calculation data of the two groups of FPs 16 and the processing of the to-be-multiplied and added calculation data of the 1 group of FPs 32 can be realized. The shift sub-module comprises two opposite-order shift units (the input bit width is 1/2 of the mantissa of the FP 32) and two normalization shift units (the input bit width is 1bit larger than the mantissa bit width of the FP 32), so that the processing of the to-be-multiplied and added calculation data of two groups of FP16 and the processing of the to-be-multiplied and added calculation data of 1 group of FP32 can be realized.

So, by multiplexing, the arithmetic logic unit can process the multiply-add operation of one set of FP32 or two sets of FP16 in parallel without significantly increasing the additional area, and it can be understood that the arithmetic logic unit can also be used to process the multiply-add operation of TF32, BF16, INT8 because the mantissa or bit width of the TF32, BF16, INT8 is smaller than the mantissa bit width of FP 32.

As shown in fig. 9, in order to further improve the parallel processing capability of the arithmetic logic unit, two addition units, two leading zero units, and two shift units may be added on the basis of the operation module shown in fig. 8. Thus, the arithmetic logic unit can process multiply-add operations for one group of FPs 32, or four groups of FPs 16 in parallel.

As shown in fig. 10, a schematic diagram of another specific operation module provided in the present disclosure is shown, and 1 format conversion sub-module 3205 is added to the operation module shown in fig. 9, which includes 4 format conversion units for integer-forming four groups of second precision floating point numbers or integers, i.e., FP16, TF32, BF16, INT8, into formats meeting the input requirements of each operation sub-module, and after the calculation is completed, the format conversion sub-module restores the data format to FP16, TF32, BF16, INT8, so that the parallel processing capability can be further accelerated.

Based on the above inventive concept, as shown in fig. 11, the disclosure proposes an operation processing method applied to an arithmetic logic unit, for processing multiply-add operations of a first precision floating point number and a second precision floating point number, where the second precision floating point number is any precision floating point number with a tail digital width not greater than 1/2 of the tail digital width of the first precision floating point number, where the arithmetic logic unit includes a data acquisition module and an operation module, and the operation module includes a multiplication processing sub-module, an addition processing sub-module, a shift sub-module, and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively; the method comprises the following steps:

s101, a data acquisition module acquires to-be-multiplied addition calculation data;

s102, any sub-module in the operation module calls a local processing sub-unit to process the to-be-multiplied addition calculation data according to the floating point number precision type of the to-be-multiplied addition calculation data to obtain a processing result; any processing subunit in any sub-module is used for processing a group of second precision floating point numbers, and a plurality of processing subunits in any sub-module are used for carrying out joint processing on a group of first precision floating point numbers.

in the case where the to-be-multiplied and added computation data is a first precision floating point number, the method further includes: the data acquisition module splits the mantissa of each multiplier of the two multipliers to obtain two sub-mantissas; any sub-tail digit width is equal and meets the input requirement of the multiplication unit; combining the sub-mantissas corresponding to the two multipliers to obtain four groups of combined results, wherein each group of combined results comprises two sub-mantissas corresponding to different multipliers; inputting the four groups of combined results to four multiplication units respectively;

any submodule in the operation module calls a local processing subunit to process the calculation data to be multiplied and added according to the floating point number precision type to obtain a processing result, and the processing result comprises the following steps:

The multiplication processing submodule calls four multiplication units of input data to execute multiplication operation on the input data, and calls an accumulation unit to execute accumulation operation on the output of the four multiplication units to obtain mantissa multiplication results of two multipliers.

the addition processing submodule determines the product of the two multipliers and the step difference between addends;

the shifting sub-module splits the mantissa of the addend to obtain a high-order sub-mantissa and a low-order sub-mantissa, wherein the bit widths of the high-order sub-mantissa and the low-order sub-mantissa are the same;

The addition processing sub-module splits the mantissa multiplication results of the two multipliers to obtain a high-order mantissa multiplication result and a low-order mantissa multiplication result;

In one embodiment, the leading zero submodule includes a processing subunit that is: at least N leading zero units; the input bit width of the leading zero unit is larger than the tail digital width of the first precision floating point number and smaller than 2 times of the tail digital width of the first precision floating point number; any submodule in the operation module calls a local processing subunit to process the calculation data to be multiplied and added according to the floating point number precision type to obtain a processing result, and the processing result comprises the following steps:

the leading zero submodule calls any leading zero unit, leading zero processing is carried out on the first addition result, and leading zero number of the first addition result is obtained;

In one embodiment, the processing subunit of the shift sub-module further comprises: at least N normalized shift units; the input bit width of the normalized shift unit is larger than the first precision floating point number tail digital width and smaller than 2 times of the first precision floating point number tail digital width, any submodule in the operation module calls a local processing submodule to process the to-be-multiplied and added calculation data according to the floating point number precision type to obtain a processing result, and the processing result comprises the following steps:

the shift submodule calls any normalization shift unit, performs normalization shift on the first addition result according to the leading zero result of the addition result, and obtains a first normalization mantissa and left shift-out data;

In one embodiment, the method further comprises: the data acquisition module acquires N-1 groups of to-be-multiplied addition calculation data with the type of the second precision floating point number under the condition that the to-be-multiplied addition calculation data is the second precision floating point number;

and the multiplication processing submodule calls N multiplication units of the input data, performs multiplication operation on the input data, and obtains mantissa multiplication results of two multipliers in N groups of to-be-multiplied addition calculation data.

In one embodiment, the shift submodule includes a processing subunit that is: at least N antipodal shift units; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the opposite-order shifting unit is not smaller than 1/2 of the tail digital width of the first precision floating point number and smaller than the tail digital width of the first precision floating point number; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

the addition processing submodule respectively determines the product of two multipliers and the step difference between addends for each group of to-be-multiplied addition calculation data;

the shift submodule calls N antipodal shift units, and antipodal shift is carried out on mantissas of the addends by utilizing step differences according to N groups of to-be-multiplied addition calculation data to obtain N mantissa antipodal results;

the addition processing submodule calls N addition units, and performs addition operation on mantissa pair-order results and mantissa multiplication results of two multipliers according to N groups of to-be-multiplied addition calculation data to obtain N mantissa results.

the leading zero submodule calls N leading zero units, leading zero processing is carried out on N mantissa results, and N leading zero processing results are obtained;

the shift submodule calls N normalization shift units, performs normalization shift on N mantissa results according to N leading zero processing results aiming at N groups of to-be-multiplied addition calculation data, and obtains N final mantissas.

In one embodiment, the arithmetic logic unit is further configured to process a multiply-add operation on an integer, wherein the integer is any integer having a bit width no greater than 1/2 of the first precision floating point number mantissa bit width; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number; the method further comprises the steps of:

the data acquisition module acquires N-1 groups of to-be-multiplied addition calculation data with the type of the integer under the condition that the to-be-multiplied addition calculation data is the integer;

the multiplication processing submodule calls N multiplication units of the input data, performs multiplication operation on the input data, and obtains multiplication results of two multipliers in N groups of to-be-multiplied addition calculation data;

the addition processing submodule calls N addition units, and performs addition operation on the multiplication results of the addend and the two multipliers respectively aiming at N groups of to-be-multiplied addition data to obtain a final result aiming at N groups of to-be-multiplied addition calculation data.

The embodiment of the disclosure also provides a chip comprising the multiplication processor. The chip may be a GPU (graphics processing unit, graphics processor), CPU (Central Processing Unit ), etc., which is not limited by this disclosure.

The embodiment of the disclosure also provides electronic equipment, which comprises the chip. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

While preferred embodiments of the present disclosure have been described above, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiments and all alterations and modifications that fall within the scope of this disclosure, and that those skilled in the art will recognize that the invention also includes the true scope of the embodiments of the disclosure without departing from the spirit and scope of the disclosure.

Claims

1. An arithmetic logic unit for processing multiply-add operations of a first precision floating point number and a second precision floating point number, wherein the second precision floating point number is any precision floating point number with a tail number bit width not greater than 1/2 of the tail number bit width of the first precision floating point number; the arithmetic logic unit comprises a data acquisition module and an operation module, wherein the operation module comprises a multiplication processing sub-module, an addition processing sub-module, a shifting sub-module and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively;

2. The arithmetic logic unit of claim 1, the set of to-be-multiplied add calculation data comprising two multipliers and one addend; the multiplication processing submodule comprises processing subunits as follows: at least 2N multiplication units with the same input bit width and an accumulation unit, wherein N is a positive integer not less than 2; the input bit width of the multiplication unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number;

3. The arithmetic logic unit of claim 2, the shift submodule comprising a processing subunit of: at least N antipodal shift units; the input bit width of the opposite-order shifting unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number;

the addition processing submodule is specifically used for determining the product of two multipliers and the step difference between addends;

4. An arithmetic logic unit in accordance with claim 3, the addition processing sub-module comprising processing sub-units of: at least N addition units; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

5. The arithmetic logic unit of claim 4, the leading zero submodule comprising a processing subunit of: at least N leading zero units; the input bit width of the leading zero unit is larger than the tail digital width of the first precision floating point number and smaller than 2 times of the tail digital width of the first precision floating point number;

6. The arithmetic logic unit of claim 5,

the processing subunit of the shift sub-module further includes: at least N normalized shift units; the input bit width of the normalization shift unit is larger than the tail digital width of the first precision floating point number and smaller than 2 times of the tail digital width of the first precision floating point number;

7. The arithmetic logic unit of claim 2,

the data acquisition module is specifically configured to acquire N-1 groups of to-be-multiplied addition calculation data with a type of the second precision floating point number when the to-be-multiplied addition calculation data is the second precision floating point number;

8. The arithmetic logic unit of claim 7, the shift submodule comprising processing subunits of: at least N antipodal shift units; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the input bit width of the opposite-order shifting unit is not less than 1/2 of the tail digital width of the first precision floating point number and is less than the tail digital width of the first precision floating point number; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

9. The arithmetic logic unit of claim 8, the leading zero submodule comprising a processing subunit of: at least N leading zero units; the processing subunit of the shift sub-module further includes: at least N normalized shift units; the input bit width of the leading zero unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width, and the input bit width of the normalization shift unit is larger than the first precision floating point tail digital width and smaller than 2 times of the first precision floating point tail digital width;

10. The arithmetic logic unit of claim 2 further configured to process multiply-add operations on integers, wherein the integers are any integer having a bit width no greater than 1/2 of a first precision floating point number mantissa bit width; the addition processing submodule comprises a processing subunit which is as follows: at least N addition units; the input bit width of the addition unit is not smaller than the tail digital width of the first precision floating point number and is smaller than 2 times of the tail digital width of the first precision floating point number;

11. The arithmetic processing method is applied to an arithmetic logic unit and is used for processing multiplication and addition operations of a first precision floating point number and a second precision floating point number, wherein the second precision floating point number is any precision floating point number with the tail digital width not larger than 1/2 of the tail digital width of the first precision floating point number, the arithmetic logic unit comprises a data acquisition module and an operation module, and the operation module comprises a multiplication processing sub-module, an addition processing sub-module, a shift sub-module and a leading zero sub-module; each sub-module in the operation module comprises a plurality of processing sub-units respectively; the method comprises the following steps:

the data acquisition module acquires to-be-multiplied addition calculation data;

any sub-module in the operation module calls a local processing sub-unit to process the to-be-multiplied addition calculation data according to the floating point number precision type of the to-be-multiplied addition calculation data to obtain a processing result; any processing subunit in any sub-module is used for processing a group of second precision floating point numbers, and a plurality of processing subunits in any sub-module are used for carrying out joint processing on a group of first precision floating point numbers.

12. A chip comprising the arithmetic logic unit of any one of claims 1-10.

13. An electronic device comprising the chip of claim 12.