CN117873304A - Low-power-consumption operation method and device applied to chip, chip and storage medium - Google Patents
Low-power-consumption operation method and device applied to chip, chip and storage medium Download PDFInfo
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Abstract
The application relates to a low-power-consumption operation method, a device, a chip, a storage medium and a computer program product applied to a chip, and relates to the technical field of chips. The method and the device can reduce the unit operation power consumption of each chip and improve the power consumption reduction degree of the chip. The method comprises the following steps: acquiring a thread pool of a chip and historical data information and function information of the thread pool; determining the operation criticality of each piece of functional information of the thread pool; determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from the function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information and the target function information of the thread pool; and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a low power consumption operation method, apparatus, chip, storage medium and computer program product applied to a chip.
Background
With the high-speed development of integrated circuit chips, the operation efficiency and the daily gain of the integrated circuit chips are increased, but with the acceleration of the operation efficiency, the data processing capacity of the chips per unit time is also increased greatly, so that the operation power consumption of the chips is increased sharply, the loss rate of the integrated circuit chips is increased, and the service life of the integrated circuit chips is shortened greatly; therefore, how to reduce the operation power consumption of the chip under the condition of ensuring that the data processing capacity of the chip is unchanged is the current research focus.
In the conventional technology, the power consumption of the chip is reduced by reducing the data processing amount of the chip in unit time and sequencing each data, so that the operation power consumption of the chip is reduced, but the data processing amount of the chip in unit time is reduced while the operation power consumption is reduced, so that the operation power consumption of the chip is still at a higher level under the condition of ensuring the operation efficiency of the chip.
Disclosure of Invention
Based on this, it is necessary to provide a low power consumption operation method, apparatus, chip, computer readable storage medium and computer program product applied to the chip in view of the above technical problems.
In a first aspect, the present application provides a low power consumption operation method applied to a chip. The method comprises the following steps:
Acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool;
determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip;
determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information;
constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information;
and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
In one embodiment, the determining the operation criticality of each piece of functional information of the thread pool includes:
identifying the operation mode, operation efficiency and operation program information of each piece of the function information; according to the operation efficiency of each piece of function information, efficiency sequencing is carried out on each piece of function information to obtain an efficiency sequence of each piece of function information; identifying the operation difficulty of each piece of the function information according to the operation mode of each piece of the function information; identifying the data processing criticality of each piece of function information according to the operation program information of each piece of function information; and determining the operation criticality of each piece of functional information of the thread pool based on the efficiency sequence, the operation difficulty and the data processing criticality of each piece of functional information.
In one embodiment, the determining the power consumption information of each function information of the thread pool based on the historical data information and the simulation running model includes:
identifying data processing tasks corresponding to the historical data information and functional information corresponding to each data processing task; simulating the process of processing the historical data information by the chip through the simulation running model on the basis of the historical data information of the data processing task corresponding to the functional information aiming at each piece of functional information to obtain the data processing process information of the historical data information; identifying the power consumption distribution information of each data processing process information, and screening out the maximum power consumption information in the power consumption distribution information to be used as sub-power consumption information corresponding to each data processing process information; and carrying out average processing on all the sub-power consumption information to obtain the power consumption information of the function information.
In one embodiment, the screening the target function information from the function information based on the power consumption information of each function information and the operation criticality of each function information includes:
screening out function information with power consumption information larger than a power consumption threshold value from the function information as first function information, and screening out function information with operation criticality smaller than the operation criticality threshold value as second function information; and taking the function information belonging to the first function information and the function information belonging to the second function information as the target function information.
In one embodiment, the constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information includes:
obtaining a sample thread pool; acquiring thread pool demand information corresponding to each piece of target function information, and determining target thread parameter information applicable to all pieces of thread pool demand information; and adjusting the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
In one embodiment, the configuring the target function information in the auxiliary thread pool and establishing an association relationship between the auxiliary thread pool and the chip includes:
identifying an execution program of each target function information, and configuring the execution program of each target function information into the auxiliary thread pool; closing the execution program of each target function information in the thread pool; acquiring a target power consumption value of the chip, establishing a switching strategy of an operation mode of the chip based on the target power consumption value, and establishing an enabling strategy of each target function information in the auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
In one embodiment, after establishing the association relationship between the auxiliary thread pool and the chip, the method further includes:
detecting the current power consumption value of the chip, and converting the operation mode of the chip into a target operation mode under the condition that the current power consumption value is larger than the target power consumption value; and identifying the processing process of the current data information being processed by the chip, and carrying out data processing on the current data information cooperatively based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the current data information.
In a second aspect, the present application further provides a low power consumption operation device applied to a chip. The device comprises:
the information acquisition module is used for acquiring a thread pool of the chip and historical data information of the thread pool and identifying functional information corresponding to the thread pool;
the model construction module is used for determining the operation criticality of each piece of functional information of the thread pool and constructing a simulation running model corresponding to the chip;
the information screening module is used for determining the power consumption information of each piece of functional information of the thread pool based on the historical data information and the simulation operation model, and screening target functional information from the functional information based on the power consumption information of the functional information and the operation criticality of the functional information;
The auxiliary application module is used for constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information;
and the association establishing module is used for configuring the target function information in the auxiliary thread pool and establishing an association relation between the auxiliary thread pool and the chip.
In a third aspect, the present application also provides a chip. The chip comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the following steps when executing the computer program:
acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool; determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip; determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information; and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
In a fourth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool; determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip; determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information; and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
In a fifth aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the steps of:
Acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool; determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip; determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information; and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
The low-power-consumption operation method, the device, the chip, the storage medium and the computer program product applied to the chip are realized by acquiring the thread pool of the chip and the historical data information of the thread pool and identifying the functional information corresponding to the thread pool; determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip; determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from the function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information and the target function information of the thread pool; and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip. In this way, the method and the device effectively reduce the unit operation power consumption of each chip and improve the power consumption reduction degree of the chip by splitting the target function information with lower operation criticality and larger power consumption in the function information of the chip thread pool and constructing a plurality of auxiliary thread pools to bear the target function information, thereby ensuring the unchanged operation efficiency of the chip and reducing the data processing task corresponding to the function information with high power consumption and low operation criticality of the chip.
Drawings
FIG. 1 is a flow chart of a low power operation method applied to a chip in one embodiment;
FIG. 2 is a flow chart illustrating steps for determining power consumption information in one embodiment;
FIG. 3 is a flow chart of a low power operation method applied to a chip in one embodiment;
FIG. 4 is a block diagram of a low power operation device applied to a chip in one embodiment;
fig. 5 is an internal structural diagram of a chip in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, a low power consumption operation method applied to a chip is provided, and the embodiment is applied to a terminal for illustration by using the method, it can be understood that the method can also be applied to application environments of an internet of things chip, an integrated circuit chip and a server, and can also be applied to a system comprising the terminal and the server, and is realized through interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and the like; the server may be implemented as a stand-alone server or as a server cluster composed of a plurality of servers. In this embodiment, the method includes the steps of:
Step S101, acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool.
Wherein, the thread pool is a mechanism for managing and multiplexing threads, which can improve the performance and efficiency of the multi-threaded application; a thread queue is maintained in the thread pool, and available threads are stored in the thread queue; when the task needs to be executed, an idle thread can be obtained from the thread pool to execute the task, and after the execution is completed, the thread returns to the thread pool and waits for the next task allocation.
Specifically, the terminal responds to the information uploading operation of the user to acquire the thread pool information of the chip, wherein the thread pool of the chip is the thread pool which needs to be cooperatively processed when the chip processes data. Then, the terminal acquires a plurality of processed data information in a history database to obtain history data information; wherein the historical data information includes unprocessed data information, processed data information, and data processing tasks for the data information. Finally, the terminal acquires each data processing function of the chip and identifies the execution mode of each data processing function; among the data processing functions, screening the data processing functions corresponding to the execution modes executed by the thread pool as the function information corresponding to the thread pool; the function information is a data processing function corresponding to a data processing task which can be executed by the thread pool; such as data storage, data segmentation, data identification, and data transformation.
Step S102, determining operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip.
Wherein a simulation run model refers to the simulation and running of a series of predefined rules and parameters by a computer to simulate and predict the behavior and outcome of a certain system, process or event.
Specifically, the terminal determines the operation criticality of each function information based on the operation mode, operation efficiency and operation program information of each function information for executing data processing on the chip, and constructs a simulation operation model corresponding to the chip; the operation criticality is used for representing the importance degree of the functional information on chip processing; the operation mode is the execution mode of the function information, for example, the operation mode of data combination is a data combination, the operation mode of data segmentation is data information splitting and the like; the operation program information is used for representing operation steps corresponding to the function information, namely steps required to be executed when the thread pool executes the function information.
Step S103, based on the historical data information and the simulation running model, determining the power consumption information of each piece of function information of the thread pool, and based on the power consumption information of each piece of function information and the operation criticality of each piece of function information, screening out target function information from each piece of function information.
Specifically, the terminal determines the power consumption information of each piece of function information of a thread pool of a chip through a simulation operation model based on each piece of historical data information, and screens out a plurality of pieces of target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information; the target function information is the function information with large power consumption and small operation criticality, the power consumption is larger than a power consumption threshold, the operation criticality is smaller than a criticality threshold, and the power consumption threshold and the criticality threshold are preset in the terminal.
Step S104, constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information and the target function information of the thread pool.
Wherein, the auxiliary thread pool generally refers to a thread pool additionally created outside the main thread pool and used for processing specific or asynchronous tasks; in some cases, we may need multiple different types of tasks, and the execution time, frequency or priority of these tasks are different; to better manage these tasks, a pool of helper threads may be created to better control the execution of the tasks.
Specifically, the terminal identifies thread parameter information of a thread pool, and builds an auxiliary thread pool corresponding to the thread pool based on the thread parameter information and each target function information; the auxiliary thread pool is used for sharing part of functional information of the thread pool so as to share the power consumption of the chip.
Step S105, configuring the target function information in the auxiliary thread pool, and establishing an association relationship between the auxiliary thread pool and the chip.
Specifically, the terminal configures each target function information of the thread pool in the auxiliary thread pool, and establishes an association relationship between the auxiliary thread pool and the chip.
In the low-power-consumption operation method applied to the chip, the target function information with lower operation criticality and larger power consumption in the function information of the chip thread pool is split, and a plurality of auxiliary thread pools are constructed to bear the target function information, so that the unit operation power consumption of each chip is effectively reduced and the power consumption reduction degree of the chip is improved by reducing the data processing tasks corresponding to the function information with high power consumption and low operation criticality of the chip under the condition of ensuring the unchanged operation efficiency of the chip.
In one embodiment, in the step S102, the determining the operation criticality of each piece of function information of the thread pool specifically includes the following steps:
identifying the operation mode, operation efficiency and operation program information of each piece of functional information; according to the operation efficiency of each function information, efficiency sequencing is carried out on each function information to obtain an efficiency sequence of each function information; identifying the operation difficulty of each function information according to the operation mode of each function information; identifying the data processing criticality of each function information according to the operation program information of each function information; and determining the operation criticality of each piece of functional information of the thread pool based on the efficiency sequence, the operation difficulty and the data processing criticality of each piece of functional information.
The operation criticality is a comprehensive criticality comprising an operation sequence, operation difficulty and data processing criticality.
Specifically, the terminal recognizes the operation mode of each function information, the operation efficiency of each function information, and the operation program information of each function information. Then, the terminal performs efficiency sequencing on each function information based on the operation efficiency of each function information to obtain an efficiency sequence of each function information, and identifies the operation difficulty of each function information based on the corresponding relation between each operation mode and the operation difficulty preset in the terminal based on the operation mode of each function information. The terminal identifies the data processing criticality of each function information based on the operation program information of each function information, and determines the operation criticality of each function information based on the operation program information of each function information, the operation difficulty of each function information, and the data processing criticality of each function information.
In this embodiment, the operation criticality of each piece of functional information is determined by analyzing the operation sequence, the operation difficulty and the data processing criticality of each piece of functional information, so that the comprehensiveness of determining the operation criticality is improved.
In one embodiment, as shown in fig. 2, in the step S103, the power consumption information of each function information of the thread pool is determined based on the history data information and the simulation running model, and specifically includes the following steps:
Step S201, identifying a data processing task corresponding to the historical data information and function information corresponding to each data processing task.
Step S202, for each piece of function information, based on the historical data information of the data processing task corresponding to the function information, simulating the process of processing the historical data information by the chip through a simulation operation model to obtain the data processing process information of the historical data information.
Step S203, the power consumption distribution information of each data processing process information is identified, and the maximum power consumption information in the power consumption distribution information is screened out and used as the sub-power consumption information corresponding to each data processing process information.
Step S204, carrying out averaging processing on all the sub-power consumption information to obtain the power consumption information of the function information.
Specifically, the terminal identifies the data processing tasks of each history data information, and identifies the function information corresponding to each data processing task. Then, the terminal simulates the process of processing the historical data information corresponding to the functional information by the chip according to the historical data information of the data processing task corresponding to the functional information and through a simulation operation model to obtain the data processing process information of each historical data information of the functional information. Then, the terminal identifies the power consumption distribution information of each data processing process information, and screens the maximum power consumption information in each power consumption distribution information as the sub-power consumption information of each data processing process information. And finally, the terminal performs average processing on all the sub-power consumption information to obtain the power consumption information of the function information.
In this embodiment, the power consumption information is identified by a simulation technique, so that the accuracy of identifying the power consumption information is improved.
In one embodiment, in the step S103, the target function information is selected from the function information based on the power consumption information of each function information and the operation criticality of each function information, and the method specifically includes the following steps:
among the function information, screening out the function information with the power consumption information larger than the power consumption threshold value as first function information, and screening out the function information with the operation criticality smaller than the operation criticality threshold value as second function information; the function information belonging to the first function information and the second function information is taken as target function information.
Specifically, the terminal screens out function information corresponding to the power consumption information larger than the power consumption threshold value from the function information as first function information, and screens out function information corresponding to the operation criticality smaller than the operation criticality threshold value from the function information as second function information. And finally, the terminal takes the function information which belongs to the first function information and the second function information at the same time as target function information.
In this embodiment, by screening out the functional information with high power consumption and low operation criticality, the operation power consumption of the chip can be effectively reduced by sharing the power consumption under the condition of avoiding affecting the overall operation efficiency of the chip.
In one embodiment, in the step S104, an auxiliary thread pool corresponding to the thread pool is constructed according to the thread parameter information and the target function information of the thread pool, and the method specifically includes the following steps:
obtaining a sample thread pool; acquiring thread pool demand information corresponding to each piece of target function information, and determining target thread parameter information applicable to all pieces of thread pool demand information; and adjusting the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
The sample thread pool information is any one of the downstream thread pools of the integrated circuit chip.
The thread pool requirement information is requirement information of thread pool parameters, and the thread pool parameters include, but are not limited to, core thread number, maximum thread number, idle time, time unit, rejection strategy, and the like.
The thread parameter information of the auxiliary thread pool meets the thread parameter information and the target thread parameter information.
Specifically, the terminal acquires sample thread pool information. Then, the terminal identifies thread pool requirement information corresponding to each target function information. And then, the terminal determines target thread parameter information applicable to all the thread pool requirement information. And finally, the terminal adjusts the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
In the embodiment, the auxiliary thread pool for executing the target function information is determined on the basis of the sample thread pool, so that the execution efficiency of the thread pool on the target function information is effectively improved.
In one embodiment, in the step S105, the target function information is configured in the auxiliary thread pool, and an association relationship between the auxiliary thread pool and the chip is established, and the method specifically includes the following steps:
identifying an execution program of each target function information, and configuring the execution program of each target function information into an auxiliary thread pool; closing an executive program of each target function information in the thread pool; acquiring a target power consumption value of a chip, establishing a switching strategy of an operation mode of the chip based on the target power consumption value, and establishing an enabling strategy of each target function information in an auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
Specifically, the terminal identifies an execution program of each target function information and configures the execution program of each target function information into an auxiliary thread pool; then, the terminal closes the execution program of each target function information in the thread pool; and finally, the terminal acquires a target power consumption value of the chip, establishes a switching strategy of an operation mode of the chip based on the target power consumption value, and establishes an enabling strategy of each target function information in the auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
In the embodiment, through operations such as configuration, closing and the like, the operation mode corresponding to the chip is determined, and the power consumption sharing effect of the chip is improved; and then, through setting the association relation between the target auxiliary thread pool and the chip, the efficiency and the accuracy of the chip for calling the target auxiliary thread pool are improved, and then, through setting the switching strategy and the starting strategy, the switching accuracy from the running mode of the chip to the target running mode is improved.
In one embodiment, after establishing the association relationship between the auxiliary thread pool and the chip, the method further comprises the following steps:
detecting the current power consumption value of the chip, and converting the operation mode of the chip into a target operation mode under the condition that the current power consumption value is larger than the target power consumption value; and identifying the processing process of the current data information being processed by the chip, and carrying out data processing on the current data information based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the current data information.
Specifically, the terminal detects the current power consumption value of the chip, and converts the operation mode of the chip into a target operation mode under the condition that the current power consumption value of the chip is larger than the target power consumption value; the terminal identifies the processing process of the data information being processed by the chip, and performs data processing on the data information based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the data information.
In this embodiment, by identifying the power consumption value of the chip, the operation mode of the chip is adjusted, so that the flexibility of switching the operation mode of the chip is improved while the power consumption information of the chip is reduced.
In one embodiment, as shown in fig. 3, a low power consumption operation method applied to a chip in a specific embodiment is provided, which specifically includes the following steps:
step S301, acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool.
Step S302, identifying the operation mode, operation efficiency and operation program information of each piece of function information; according to the operation efficiency of each function information, efficiency sequencing is carried out on each function information to obtain an efficiency sequence of each function information; identifying the operation difficulty of each function information according to the operation mode of each function information; identifying the data processing criticality of each function information according to the operation program information of each function information; and determining the operation criticality of each piece of functional information of the thread pool based on the efficiency sequence, the operation difficulty and the data processing criticality of each piece of functional information.
Step S303, constructing a simulation running model corresponding to the chip.
Step S304, identifying data processing tasks corresponding to the historical data information and function information corresponding to each data processing task; for each piece of functional information, based on the historical data information of the data processing task corresponding to the functional information, simulating the process of processing the historical data information by the chip through a simulation operation model to obtain the data processing process information of the historical data information; identifying the power consumption distribution information of each data processing process information, screening out the maximum power consumption information in the power consumption distribution information, and taking the maximum power consumption information as the sub-power consumption information of each data processing process information; and carrying out average processing on all the sub-power consumption information to obtain the power consumption information of the function information.
Step S305, screening out function information with power consumption information larger than a power consumption threshold value from the function information as first function information, and screening out function information with operation criticality smaller than the operation criticality threshold value as second function information; the function information belonging to the first function information and the second function information is taken as target function information.
Step S306, a sample thread pool is obtained; acquiring thread pool demand information corresponding to each piece of target function information, and determining target thread parameter information applicable to all pieces of thread pool demand information; and adjusting the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
Step S307, identifying the execution program of each target function information, and configuring the execution program of each target function information into an auxiliary thread pool; closing the execution program of each target function information in the thread pool.
Step S308, obtaining a target power consumption value of the chip, establishing a switching strategy of an operation mode of the chip based on the target power consumption value, and establishing an enabling strategy of each target function information in the auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
Step S309, detecting the current power consumption value of the chip, and converting the operation mode of the chip into a target operation mode when the current power consumption value is greater than the target power consumption value; and identifying the processing process of the current data information being processed by the chip, and carrying out data processing on the current data information based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the current data information.
The beneficial effects brought by the embodiment are as follows:
according to the scheme, the target functional information with lower operation criticality and larger power consumption in the functional information of the chip thread pool is split, and a plurality of auxiliary thread pools are constructed to bear the target functional information, so that under the condition that the operation efficiency of the chip is ensured to be unchanged, the unit operation power consumption of each chip is effectively reduced and the power consumption reduction degree of the chip is improved by reducing the data processing tasks corresponding to the functional information with high power consumption and low operation criticality of the chip.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a low-power-consumption operation device applied to the chip for realizing the low-power-consumption operation method applied to the chip. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in one or more embodiments of the low power consumption operation device applied to the chip provided below may refer to the limitation of the low power consumption operation method applied to the chip, which is not repeated herein.
In one embodiment, as shown in fig. 4, there is provided a low power consumption operation apparatus applied to a chip, including:
the information acquisition module 401 is configured to acquire a thread pool of a chip and historical data information of the thread pool, and identify function information corresponding to the thread pool;
the model construction module 402 is configured to determine an operation criticality of each piece of functional information of the thread pool, and construct a simulation running model corresponding to the chip;
the information screening module 403 is configured to determine power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation operation model, and screen target function information from each piece of function information based on the power consumption information of each piece of function information and operation criticality of each piece of function information;
The auxiliary application module 404 is configured to construct an auxiliary thread pool corresponding to the thread pool according to the thread parameter information and the target function information of the thread pool;
and the association establishing module 405 is configured to configure the target function information in the auxiliary thread pool, and establish an association relationship between the auxiliary thread pool and the chip.
In one embodiment, the model building module 402 is further configured to identify an operation mode, an operation efficiency, and operation program information of each function information; according to the operation efficiency of each function information, efficiency sequencing is carried out on each function information to obtain an efficiency sequence of each function information; identifying the operation difficulty of each function information according to the operation mode of each function information; identifying the data processing criticality of each function information according to the operation program information of each function information; and determining the operation criticality of each piece of functional information of the thread pool based on the efficiency sequence, the operation difficulty and the data processing criticality of each piece of functional information.
In one embodiment, the information filtering module 403 is further configured to identify a data processing task corresponding to the historical data information and function information corresponding to each data processing task; for each piece of functional information, based on the historical data information of the data processing task corresponding to the functional information, simulating the process of processing the historical data information by the chip through a simulation operation model to obtain the data processing process information of the historical data information; identifying the power consumption distribution information of each data processing process information, screening out the maximum power consumption information in the power consumption distribution information, and taking the maximum power consumption information as the sub-power consumption information corresponding to each data processing process information; and carrying out average processing on all the sub-power consumption information to obtain the power consumption information of the function information.
In one embodiment, the information filtering module 403 is further configured to filter, from among the function information, function information with power consumption information greater than a power consumption threshold as first function information, and filter, as second function information, function information with operation criticality less than an operation criticality threshold; the function information belonging to the first function information and the second function information is taken as target function information.
In one embodiment, the auxiliary application module 404 is further configured to obtain a sample thread pool; acquiring thread pool demand information corresponding to each piece of target function information, and determining target thread parameter information applicable to all pieces of thread pool demand information; and adjusting the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
In one embodiment, the association module 405 is further configured to identify an execution program of each target function information, and configure the execution program of each target function information into the auxiliary thread pool; closing an executive program of each target function information in the thread pool; acquiring a target power consumption value of a chip, establishing a switching strategy of an operation mode of the chip based on the target power consumption value, and establishing an enabling strategy of each target function information in an auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
In one embodiment, the low power consumption operation device applied to the chip further comprises a co-processing module, configured to detect a current power consumption value of the chip, and convert an operation mode of the chip into a target operation mode when the current power consumption value is greater than the target power consumption value; and identifying the processing process of the current data information being processed by the chip, and carrying out data processing on the current data information based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the current data information.
The above-described respective modules in the low power consumption operation device applied to the chip may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or independent of a processor in a chip, or may be stored in software in a memory in the chip, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a chip is provided, the internal structure of which may be as shown in FIG. 5. The chip includes a processor, a memory, an input/output interface, and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the chip is configured to provide computing and control capabilities. The memory of the chip includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input/output interface of the chip is used for exchanging information between the processor and the external device. The communication interface of the chip is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a low power running method for a chip.
It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the chip on which the present application is applied, and that a particular chip may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, there is also provided a chip including a memory and a processor, the memory storing a computer program, the processor implementing the steps of the method embodiments described above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the method embodiments described above.
In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
It should be noted that, the user information (including, but not limited to, user equipment information, user personal information, etc.) and the data (including, but not limited to, data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data are required to comply with the related laws and regulations and standards of the related countries and regions.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A low power consumption operation method applied to a chip, the method comprising:
acquiring a thread pool of a chip and historical data information of the thread pool, and identifying functional information corresponding to the thread pool;
determining the operation criticality of each piece of functional information of the thread pool, and constructing a simulation running model corresponding to the chip;
determining the power consumption information of each piece of function information of the thread pool based on the historical data information and the simulation running model, and screening target function information from each piece of function information based on the power consumption information of each piece of function information and the operation criticality of each piece of function information;
Constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information;
and configuring the target function information in the auxiliary thread pool, and establishing an association relation between the auxiliary thread pool and the chip.
2. The method of claim 1, wherein determining operational criticality of each functional information of the thread pool comprises:
identifying the operation mode, operation efficiency and operation program information of each piece of the function information;
according to the operation efficiency of each piece of function information, efficiency sequencing is carried out on each piece of function information to obtain an efficiency sequence of each piece of function information; identifying the operation difficulty of each piece of the function information according to the operation mode of each piece of the function information; identifying the data processing criticality of each piece of function information according to the operation program information of each piece of function information;
and determining the operation criticality of each piece of functional information of the thread pool based on the efficiency sequence, the operation difficulty and the data processing criticality of each piece of functional information.
3. The method of claim 1, wherein the determining power consumption information for each function information of the thread pool based on the historical data information and a simulation run model comprises:
Identifying data processing tasks corresponding to the historical data information and functional information corresponding to each data processing task;
simulating the process of processing the historical data information by the chip through the simulation running model on the basis of the historical data information of the data processing task corresponding to the functional information aiming at each piece of functional information to obtain the data processing process information of the historical data information;
identifying the power consumption distribution information of each data processing process information, and screening out the maximum power consumption information in the power consumption distribution information to be used as sub-power consumption information corresponding to each data processing process information;
and carrying out average processing on all the sub-power consumption information to obtain the power consumption information of the function information.
4. The method of claim 1, wherein the screening the target function information from the function information based on the power consumption information of the function information and the operation criticality of the function information comprises:
screening out function information with power consumption information larger than a power consumption threshold value from the function information as first function information, and screening out function information with operation criticality smaller than the operation criticality threshold value as second function information;
And taking the function information belonging to the first function information and the function information belonging to the second function information as the target function information.
5. The method according to claim 1, wherein the constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information includes:
obtaining a sample thread pool;
acquiring thread pool demand information corresponding to each piece of target function information, and determining target thread parameter information applicable to all pieces of thread pool demand information;
and adjusting the thread parameter information of the sample thread pool based on the thread parameter information and the target thread parameter information to obtain an auxiliary thread pool corresponding to the thread pool.
6. The method according to any one of claims 1 to 5, wherein the configuring the target function information in the assist thread pool and establishing an association between the assist thread pool and the chip includes:
identifying an execution program of each target function information, and configuring the execution program of each target function information into the auxiliary thread pool;
closing the execution program of each target function information in the thread pool;
Acquiring a target power consumption value of the chip, establishing a switching strategy of an operation mode of the chip based on the target power consumption value, and establishing an enabling strategy of each target function information in the auxiliary thread pool to obtain an association relation between the auxiliary thread pool and the chip.
7. The method of claim 6, further comprising, after establishing the association of the helper thread pool with the chip:
detecting the current power consumption value of the chip, and converting the operation mode of the chip into a target operation mode under the condition that the current power consumption value is larger than the target power consumption value;
and identifying the processing process of the current data information being processed by the chip, and carrying out data processing on the current data information cooperatively based on the target thread pool and the target auxiliary thread pool of the chip to obtain a data processing result of the current data information.
8. A low power consumption operation device for a chip, the device comprising:
the information acquisition module is used for acquiring a thread pool of the chip and historical data information of the thread pool and identifying functional information corresponding to the thread pool;
The model construction module is used for determining the operation criticality of each piece of functional information of the thread pool and constructing a simulation running model corresponding to the chip;
the information screening module is used for determining the power consumption information of each piece of functional information of the thread pool based on the historical data information and the simulation operation model, and screening target functional information from the functional information based on the power consumption information of the functional information and the operation criticality of the functional information;
the auxiliary application module is used for constructing an auxiliary thread pool corresponding to the thread pool according to the thread parameter information of the thread pool and the target function information;
and the association establishing module is used for configuring the target function information in the auxiliary thread pool and establishing an association relation between the auxiliary thread pool and the chip.
9. A chip comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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| CN202311855791.1A CN117873304A (en) | 2023-12-29 | 2023-12-29 | Low-power-consumption operation method and device applied to chip, chip and storage medium |
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