CN117872009B

CN117872009B - Monitoring method, system, equipment and storage medium of excitation rectifying equipment

Info

Publication number: CN117872009B
Application number: CN202410047492.3A
Authority: CN
Inventors: 谢连忠; 李�根; 阳清风; 杨立强
Original assignee: Beijing Kedian Yiheng Electric Power Technology Co ltd
Current assignee: Beijing Kedian Yiheng Electric Power Technology Co ltd
Priority date: 2024-01-11
Filing date: 2024-01-11
Publication date: 2024-06-18
Anticipated expiration: 2044-01-11
Also published as: CN117872009A

Abstract

A monitoring method, a system, equipment and a storage medium of excitation rectifying equipment relate to the field of power monitoring. In the method, a digital signal processor is used for collecting a first monitoring signal of a generator excitation rectifying device, wherein the first monitoring signal comprises a voltage signal, a current signal and a frequency signal, and a second monitoring signal is obtained after format conversion of the first monitoring signal and is sent to a high-performance simplified instruction set processor; collecting waveform data of excitation rectifying equipment of the generator by a high-performance simplified instruction set processor, and generating a rectifying waveform by the waveform data; judging whether the rectified waveform is consistent with a preset waveform or not and whether the value of the second monitoring signal is consistent with the value of the rectified waveform or not; and when the rectified waveform is inconsistent with the preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform, prompting the generator excitation rectifying equipment to fail. By implementing the technical scheme provided by the application, the aim of improving the monitoring effect is fulfilled.

Description

Monitoring method, system, equipment and storage medium of excitation rectifying equipment

Technical Field

The application relates to the technical field of power monitoring, in particular to a monitoring method and system of excitation rectifying equipment, electronic equipment and a storage medium.

Background

With the development of technology, the requirements of the power system are also higher and higher, and the stability and reliability of the power system are the focus of attention. The normal operation of the excitation rectifying device is critical to the stable operation of the generator, and therefore, the monitoring of the excitation rectifying device becomes an important content of power monitoring.

At present, excitation rectifying equipment monitors through a singlechip, but the performance is poor due to the fact that monitoring data and real-time waveforms are collected uniformly.

Therefore, there is a need for a monitoring method of an excitation rectifying device capable of separately processing monitoring data and real-time waveform data.

Disclosure of Invention

The application provides a monitoring method, a system, equipment and a storage medium of excitation rectifying equipment, which are used for separately collecting monitoring signals and real-time rectifying waveforms and providing convenience for fault processing and analysis.

In a first aspect of the present application, there is provided a monitoring method of an excitation rectifying device, applied to a power monitoring platform, the power monitoring platform including a digital signal processor and a high-performance reduced instruction set processor, the monitoring method comprising: collecting a first monitoring signal of generator excitation rectifying equipment through the digital signal processor, wherein the first monitoring signal comprises a voltage signal, a current signal and a frequency signal, performing format conversion on the first monitoring signal to obtain a second monitoring signal, and transmitting the second monitoring signal to a high-performance simplified instruction set processor;

collecting waveform data of the generator excitation rectifying equipment through the high-performance simplified instruction set processor, and generating a rectifying waveform through the waveform data;

judging whether the rectified waveform is consistent with a preset waveform or not and whether the value of the second monitoring signal is consistent with the value of the rectified waveform or not;

and prompting that the generator excitation rectifying equipment fails when the rectified waveform is inconsistent with a preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform.

By adopting the technical scheme, the monitoring signal and the real-time waveform data are processed separately, so that the waveform data is prevented from occupying the total data bus bandwidth, and meanwhile, the burden of a digital signal processor is reduced. The digital signal processor is used for collecting monitoring signals of the excitation rectifying equipment, the high-performance simplified instruction set processor is used for collecting waveform data of the excitation rectifying equipment, the accuracy and reliability of monitoring are improved through the dual-processor architecture, equipment faults can be found timely, and corresponding maintenance measures are taken.

Optionally, the performing format conversion on the monitoring signal to obtain a second monitoring signal and sending the second monitoring signal to the high-performance simplified instruction set processor includes:

Inputting the first monitoring signal into an analog-to-digital conversion circuit to obtain the second monitoring signal, and sending the second monitoring signal to a field programmable gate array;

The second monitor signal is sent to the high performance reduced instruction set processor through the field programmable gate array.

By adopting the technical scheme, through the cooperative work of the analog-to-digital conversion circuit, the field programmable gate array and the high-performance simplified instruction set processor, accurate conversion and efficient processing of monitoring signals are realized, and the reliability and the instantaneity of monitoring of the excitation rectifying equipment are improved.

Optionally, the sending the second monitoring signal to a field programmable gate array includes:

Checking whether a transmission mark exists in a memory of the digital signal processor when the digital signal processor transmits data to the field programmable gate array;

Checking whether a receiving area of the field programmable gate array has space or not when a transmitting mark exists in the memory of the digital signal processor;

and transmitting data to the field programmable gate array when the receiving area of the field programmable gate array has space.

By adopting the technical scheme, the transmission mark can ensure that the subsequent transmission operation is performed only when the data needs to be transmitted, thereby avoiding unnecessary communication and resource waste. When the transmission flag is present, it is further checked whether the receiving area of the field programmable gate array has room. This is to ensure that the transmitted data can be correctly received and processed, avoiding communication errors or data loss due to the full reception area. This checking mechanism ensures the integrity and reliability of the data.

when the space of the receiving area of the field programmable gate array is full, the amount of data sent by the digital signal processor is decremented until zero.

By adopting the technical scheme, the problem that the space of the receiving area is full is effectively solved by using the mode of decreasing the quantity of the transmitted data, and the stability and the reliability of monitoring the excitation rectifying equipment are improved. This mechanism enhances the adaptability and robustness of the system, enabling it to provide accurate monitoring data under a variety of conditions.

Arranging the measurement data, the switching value data and various communication marks of the second monitoring signal together and sending the measurement data, the switching value data and various communication marks to the field programmable gate array;

When new data is needed to be transmitted to the field programmable gate array, a corresponding communication mark is set according to the new data.

By adopting the technical scheme, the measurement data, the switching value data and the communication mark are integrated and transmitted, so that the processing efficiency of the monitoring data and the communication accuracy are improved. Meanwhile, the real-time performance and flexibility of the system are enhanced by setting the dynamic communication mark, and convenience is provided for future function expansion. The data organization mode can better meet the complex requirement of excitation rectifying equipment monitoring, and the overall performance of the monitoring platform is improved.

Optionally, the monitoring method further includes:

and storing sampling point data into a synchronous dynamic random access memory through the high-performance simple instruction set processor and storing waveform data into a secure digital card, wherein the acquisition frequency of the high-performance simple instruction set processor is dynamically adjusted according to the frequency of a digital signal processor.

By adopting the technical scheme, the high-capacity synchronous dynamic random access memory can provide waveform cache, the high-speed high-capacity secure digital card can provide waveform data, and the historical data can be read after power failure, so that the state waveform analysis capability of the excitation rectifying equipment is greatly improved.

Optionally, the monitoring method further includes:

when a request for remotely watching waveforms is received, data in the high-performance reduced instruction set processor is transmitted to a remote upper computer through Ethernet communication.

By adopting the technical scheme, the remote monitoring capability, the data sharing level and the fault processing efficiency of the excitation rectifying equipment are improved by utilizing remote data transmission. The method is beneficial to improving maintainability and operation stability of equipment, reducing maintenance cost and promoting cross-regional and cross-department equipment management cooperation.

In a second aspect of the present application, a monitoring system for an excitation rectifying device is provided, including an acquisition module, a waveform module, a judgment module, and a prompt module, where:

The acquisition module is configured to acquire a first monitoring signal of the generator excitation rectifying device through the digital signal processor, wherein the first monitoring signal comprises a voltage signal, a current signal and a frequency signal, and the first monitoring signal is subjected to format conversion to obtain a second monitoring signal and is sent to the high-performance simplified instruction set processor;

The waveform module is configured to collect waveform data of the generator excitation rectifying equipment through the high-performance simplified instruction set processor and generate a rectifying waveform through the waveform data;

The judging module is configured to judge whether the rectified waveform is consistent with a preset waveform and whether the value of the second monitoring signal is consistent with the value of the rectified waveform;

and the prompting module is configured to prompt the generator excitation rectifying equipment to fail when the rectified waveform is inconsistent with a preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform.

In a third aspect the application provides an electronic device comprising a processor, a memory for storing instructions, a user interface and a network interface, both for communicating with other devices, the processor being for executing instructions stored in the memory to cause the electronic device to perform a method as claimed in any one of the preceding claims.

In a fourth aspect of the application there is provided a computer readable storage medium storing instructions which, when executed, perform a method as claimed in any one of the preceding claims.

In summary, one or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

1. The monitoring signal and the real-time waveform data are processed separately, so that the waveform data are prevented from occupying the total data bus bandwidth, and meanwhile, the burden of the digital signal processor is relieved.

2. The digital signal processor is used for collecting monitoring signals of the excitation rectifying equipment, the high-performance simplified instruction set processor is used for collecting waveform data of the excitation rectifying equipment, the accuracy and reliability of monitoring are improved through the dual-processor architecture, equipment faults can be found timely, and corresponding maintenance measures are taken.

Drawings

Fig. 1 is a schematic flow chart of a monitoring method of an excitation rectifying device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an architecture of a power monitoring platform according to an embodiment of the present application;

FIG. 3 is a schematic diagram of communication of a field programmable array in accordance with an embodiment of the disclosure;

FIG. 4 is a schematic diagram of an on-line working state of excitation rectifying equipment according to an embodiment of the present application;

fig. 5 is a schematic diagram showing waveforms of excitation rectifying equipment sent to an upper computer according to an embodiment of the present application;

FIG. 6 is a schematic block diagram of a monitoring system for an excitation rectifier device according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Reference numerals illustrate: 601. an acquisition module; 602. a waveform module; 603. a judging module; 604. a prompting module; 701. a processor; 702. a communication bus; 703. a user interface; 704. a network interface; 705. a memory.

Detailed Description

In order that those skilled in the art will better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.

In describing embodiments of the present application, words such as "for example" or "for example" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "such as" or "for example" in embodiments of the application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "or" for example "is intended to present related concepts in a concrete fashion.

In the description of embodiments of the application, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The embodiment discloses a monitoring method of excitation rectifying equipment, which is applied to an electric power monitoring platform, wherein the electric power monitoring platform comprises a digital signal processor and a high-performance simplified instruction set processor, and fig. 1 is a schematic flow diagram of the monitoring method of the excitation rectifying equipment disclosed by the embodiment of the application, as shown in fig. 1, and comprises the following steps:

s110, acquiring a first monitoring signal of generator excitation rectifying equipment through the digital signal processor, wherein the first monitoring signal comprises a voltage signal, a current signal and a frequency signal, performing format conversion on the first monitoring signal to obtain a second monitoring signal, and transmitting the second monitoring signal to a high-performance simplified instruction set processor;

S120, acquiring waveform data of excitation rectifying equipment of the generator through the high-performance simplified instruction set processor, and generating a rectifying waveform through the waveform data;

S130, judging whether the rectified waveform is consistent with a preset waveform and whether the value of the second monitoring signal is consistent with the value of the rectified waveform;

And S140, when the rectified waveform is inconsistent with a preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform, prompting that the generator excitation rectifying equipment fails.

Fig. 2 is a schematic architecture diagram of a power monitoring platform according to an embodiment of the present application, and an embodiment of the present application is described with reference to fig. 2.

As shown in fig. 2, a Digital Signal Processor (DSP) obtains a first monitoring signal from a generator excitation rectifying device, where the first monitoring signal includes, but is not limited to, a voltage signal, a current signal, and a frequency signal, converts a format of the first monitoring signal to obtain a second monitoring signal, and sends the second monitoring signal to a high-performance reduced instruction set processor. The high-performance simplified instruction set processor (ARM) can directly collect waveform data of the generator excitation rectifying equipment through another channel, can generate a rectifying waveform through the waveform data, and can display the rectifying waveform through an LCD (liquid crystal display). Judging whether the rectified waveform is consistent with a preset waveform or not and whether the value of the second monitoring signal is consistent with the value of the rectified waveform or not, wherein the consistent of the rectified waveform and the preset waveform means that the difference between the wave crest and the wave trough of the rectified waveform and the wave crest and the wave trough of the preset waveform are within the allowable error range, and the rectified waveform does not have obvious fluctuation, wherein the fluctuation means that the wave crest or the wave trough exceeds a reasonable range or the waveform is irregular; determining a first value of a second monitoring signal, and determining a corresponding second value in the rectified waveform at the same time, wherein whether the value of the second monitoring signal is consistent with the value of the rectified waveform or not means that the first value is the same as or similar to the second value, and the similarity means that the first value and the second value are within an error allowable range. And prompting that the generator excitation rectifying equipment fails when the rectified waveform is inconsistent with a preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform.

In the embodiment of the application, the DSP adopts an F283xx chip of TI company, which comprises a plurality of on-chip resources such as a 32-bit processor built-in 34KB SRAM, a 256KB flash memory, a 12-bit 16-channel ADC, a high-precision timer, a high-speed communication interface and the like, wherein the F283xx main frequency is 150MHz, and the on-chip resources are rich. The DSP acquisition control processes monitoring signals such as voltage, current and the like of the rectifying equipment through the A/D acquisition unit, and the sampling frequency of the system is set according to the frequency of the power supply and can be dynamically adjusted. ARM adopts ST company stm32F7xx as main control chip, and operating frequency reaches 216MHz, and system interface resource is abundant, and high accuracy AD sampling utilizes DMA passageway in a large number, and data processing is rapid, does not occupy CPU instruction cycle, and cache acceleration function uses in a flexible way, and configuration is convenient, and the GUI interface adopts 5.7 inch TFT color LCD, and resolution ratio 640x480 is as important man-machine conversation window, combines keyboard operation, can carry out information interaction such as measurement display, parameter setting, system test, wave form display, event record, trend graph. ARM stores sampling point data into SDRAM, opens up 1200 waveform buffer, the acquisition frequency is dynamically adjusted according to the frequency transmitted by DSP, the sampling mode selects a circulation mode, the channel DMA is controlled, CPU time is not occupied, the resolution of the liquid crystal screen is 640x480, 400 point data is displayed at most, the upper computer can read waveform, and 600 point data is transmitted at most. The waveform data of the rectifying equipment are collected in real time and presented to a customer for analysis and use through a liquid crystal display screen, open loop tests are carried out through a fixed angle test function, different silicon controlled trigger angles can be set, different real-time waveforms are corresponding, and a processing scheme is provided for the user by combining on-site data analysis and fault positioning.

The monitoring signal and the real-time waveform data are processed separately, so that the waveform data are prevented from occupying the total data bus bandwidth, and meanwhile, the burden of the digital signal processor is relieved. By comparing the rectified waveform with a preset waveform, the running state of the rectifying device can be rapidly judged. The technical effect is helpful for timely finding out equipment faults and improving the accuracy and efficiency of fault diagnosis. The operating state of the rectifying device is further verified by comparing the value of the second monitoring signal with the value in the rectified waveform. The numerical consistency check can enhance the reliability of fault diagnosis and avoid false alarm or missing alarm. The rectification waveform is directly displayed through the liquid crystal display, so that an operator or a maintainer can intuitively know the running state of the equipment. The visual man-machine interaction mode improves the usability and the user experience of the monitoring system.

The communication mode of the digital signal processor and the high-performance simplified instruction set processor is transferred through a Field Programmable Gate Array (FPGA), the high-performance simplified instruction set processor is connected with the field programmable gate array through a parallel port, and the field programmable gate array and the digital signal processor are communicated through the parallel port. As shown in fig. 2, the first monitoring signal is input into an analog-to-digital conversion circuit in a digital signal processor to obtain a second monitoring signal, and the second monitoring signal is sent to a field programmable gate array through the digital signal processor. The digital signal processor interrupts the internal acquisition and calculation of the monitoring data, the transmission and the reception of the process data are carried out in the main cycle without occupying interrupt time, and the data frame interval is not less than 2mS. The high-performance simple instruction set processor adopts a DMA (direct memory access) mode for sending and receiving, and the sending and receiving processes are not interfered by a CPU. In order to make the digital signal processor easy to process the received data, the number of bytes sent by the high-performance simple instruction set processor is fixed to 16 bytes, and the sending length of the digital signal processor can be dynamically adjusted according to the requirement.

And inputting the first monitoring signal into an analog-to-digital conversion circuit to obtain a second monitoring signal. The analog-to-digital conversion circuit is used for converting the analog signal into a digital signal so as to facilitate subsequent processing and transmission. This step ensures the accuracy and reliability of the signal and eliminates noise and distortion of the analog signal during transmission and processing. The second monitoring signal can be further processed and scheduled through the FPGA, so that the signal can be ensured to be sent to the high-performance simplified instruction set processor according to a preset format and time sequence. Through the interface with the FPGA, the ARM processor can efficiently receive and process the second monitoring signal, and real-time monitoring and fault early warning of the excitation rectifying equipment are realized.

When the FPGA is full of 16 bytes of data, processing of received data is started, and corresponding operation is carried out after the received data is checked. The sending data is provided with a buffer area, the length of the buffer area is 256 words, and the buffer area is stored according to bytes. FIG. 3 is a communication schematic diagram of a field programmable gate array according to an embodiment of the present application, as shown in FIG. 3, S310, when a digital signal processor prepares to send data to the field programmable gate array, check whether a send flag exists in a memory of the digital signal processor; s320, when a sending mark exists, writing data into the FPGA cache until the FPGA cache is full, and decrementing the quantity of the sending data; s330, judging whether the transmitted data reaches zero; s340, when the transmitted data reaches zero, the transmission mark is cleared; s350, ending the transmission.

Before the digital signal processor sends data to the field programmable gate array, it is first checked whether a transmission flag exists in the memory of the digital signal processor. The transmission flag is a flag bit for indicating whether data needs to be transmitted. By checking the transmission flag, it is possible to ensure that the subsequent transmission operation is performed only when data transmission is required, avoiding unnecessary communication and resource waste. When the send flag is present, the system further checks whether the receiving region of the field programmable gate array has room. This is to ensure that the transmitted data can be correctly received and processed, avoiding communication errors or data loss due to the full reception area. This checking mechanism ensures the integrity and reliability of the data. If the receiving area of the field programmable gate array has room, the digital signal processor will send data to it. This step enables the actual transmission of data so that the second monitoring signal can be sent to the field programmable gate array without error.

When the FPGA buffer area is full, the sending data is decremented until the sending data is 0. The communication rate may be 5MHz. The communication rate is calculated according to the following steps: the DSP configures the AD7606 to sample 8 channels with 4us, the number of sampling points per cycle is 32, the alternating frequency range is 20-100 Hz, the highest sampling interval time is 1S/100 Hz/32=312.5us, the AD data throughput rate meets the requirement, assuming that the communication rate is 5MHz, 1/(5/10) =2us is required for transmitting one byte, the 16 byte transmission time is about 32us, and about 500K words per second can be transmitted.

When the space of the receiving area is full, if the data is continuously transmitted, the data may overflow, thereby losing important information. By decrementing the amount of data sent, such overflow of data can be avoided, ensuring that all data is properly received and processed. By controlling the amount of data sent, the system is able to more efficiently utilize the receiving area space of the field programmable gate array. This helps to optimize the resource allocation and improve the overall efficiency of the system. This decrementing mechanism allows the system to adapt to the situation. When space in the receiving area becomes available, the system can resume normal data transmission, ensuring continuity and integrity of the monitored data. Through the control mechanism, the system can better cope with various emergency situations, and the stability and the reliability of the system are enhanced. Even under the condition that the space of the receiving area is limited, the system can still operate normally, and monitoring interruption or error caused by data overflow cannot occur.

The FPGA communication protocol of the invention is as follows:

Starter symbol	Function code	Memory address	Data	Check code
					0xAA	0xXX	2-Word	…	1-Shaped

In order to read the monitoring data on the DSP rapidly, a communication protocol non-communication address is specially designed. The low byte is preceding and the high byte is following. The doubleword data is sent in low, low high, high low, high byte order. The frame length takes words as a unit, and all messages remove all data lengths after the check codes. The address is the actual RAM address of the access DSP, 16 bits wide. Checksum in data refers to: all word data except the checksum is added, the inverse of the sum. When ARM sends data, the length is fixed to 16 bytes. When writing data, the DSP does not respond.

The function codes in the embodiment of the application are shown in the following table:

Sequence number	Function code	Function definition
			1	0x01	Reading data
2	0x02	Writing single word data (int)
			3	0x03	Writing double word data (long)
4	0x04	Writing four-word data (double)

For a 0x01 function code:

ARM sends the message as follows:

Function code

Address low word

High address word

Data 1

Data 2

Data 3

Data 4

Checksum

01AAH

0000H

0006H

xxxxH

The address is the first address of the register for reading data, the data 1 is the data quantity to be read, the data 2, 3 and 4 are invalid, and the message indicates that 6 data are read from the address 0x 0000. The DSP should send out data with addresses 0x0000 to 0x 0005.

The DSP response message is as follows:

Function code

Address low word

High address word

Data length

Data 1

…

Data n

Checksum

01AAH

0000H

0xXXXX

0200H

…

0201H

xxxxH

The DSP arranges all the measured data, the switching value data and various communication marks together, and the ARM takes away the common data at one time. When new information needs to be transmitted to the ARM, a corresponding communication sign is set, and the ARM reads relevant data such as a switching value change record, an alarm record and the like after receiving the information. The input and output of the switch value are formed in the form of words, each bit corresponds to one switch value, and when the switch value address is read, ARM interprets the switch value according to the bit.

For a 0x02 function code:

ARM sends the message as follows:

Function code

Address low word

High address word

Data 1

Data 2

Data 3

Data 4

Checksum

02AAH

0034H

0000H

0002H

xxxxH

The address is the register address for writing data, data 1 is the data to be written, data 2, 3, 4 are invalid, and the above message indicates writing 0x0002 to address 0x 00000034.

For a 0x03 function code:

ARM sends the message as follows:

Function code

Address low word

High address word

Data 1

Data 2

Data 3

Data 4

Checksum

03AAH

0034H

0000H

0002H

0001H

xxxxH

The address is the register head address for writing data, data 1 and 2 are the data to be written, and data 3 and 4 are invalid, and the message indicates that 0x0002 is written to address 0x00000034 and 0x0001 is written to address 0x 00000035.

For a 0x04 function code:

ARM sends the message as follows:

Function code

Address low word

High address word

Data 1

Data 2

Data 3

Data 4

Checksum

04AAH

0030H

0000H

0012H

3456H

3344H

5566H

xxxxH

The address is the register head address for writing data, and data 1/2/3 is the data to be written, and the above message indicates that 0x0012 is written to address 0x00000030, 0x3456 is written to address 0x00000031, 0x3344 is written to address 0x00000032, and 0x5566 is written to address 0x 00000033. The message is written to the DSP for 18 milliseconds at 24 minutes, 06 seconds and 19 hours at 1 month and 13 days in 2000. This time point is 1 month 1 day 0 from 2000, 0 minutes and 0 seconds.

Different types of monitoring data (such as measurement data and switching value data) are sent together with the communication mark, so that unified processing and analysis of the data are facilitated. The integration mode simplifies the data processing flow and improves the processing efficiency. Through setting up various communication flags, can classify and the sign to data according to different communication demands. This helps to more accurately parse and process data at the receiving end, and improves the accuracy and reliability of communication. When new data needs to be transmitted, the system can dynamically set a corresponding communication mark according to the new data. The dynamic response mechanism ensures the real-time performance of the data, so that the system can process and update the monitoring data in time. By combining the communication sign with the monitoring data, the system can more flexibly process and transmit the data when the function of the system is expanded or adjusted in the future. This design enhances the maintainability and scalability of the system.

Optionally, the monitoring method further includes:

The high-speed large-capacity SDRAM caches waveform data and liquid crystal picture data, the SD card driver is provided with a high-speed large-capacity SD memory card, and event records, fault waveform data and historical trend data are stored in real time, so that the user can conveniently analyze and call the data.

The waveform data is stored in the secure digital card, so that the security and durability of the data can be ensured. The secure digital card is used as a reliable storage medium and can provide encryption and protection for data and prevent the data from being lost or illegally accessed. The acquisition frequency of the high-performance simple instruction set processor can be dynamically adjusted according to the frequency of the digital signal processor, which is beneficial to realizing dynamic management and efficient storage of data. According to actual needs, the system can flexibly adjust the acquisition frequency to adapt to different monitoring requirements and resource allocation. By storing the sampling point data into the synchronous dynamic random access memory, the system can realize quick reading and writing of the data and dynamic management. The synchronous dynamic random access memory provides a larger storage space and a higher data access speed, and is beneficial to improving the processing efficiency and response speed of the monitored data. The data storage mechanism provides a flexible data management mode and can be expanded or adjusted according to actual requirements. For example, the number of secure digital cards may be increased or the capacity of the synchronous dynamic random access memory may be adjusted to meet the ever-increasing data storage requirements.

Optionally, the monitoring method further includes:

Fig. 4 is a schematic diagram of an on-line working state of an excitation rectifying device according to an embodiment of the present application, and as shown in fig. 4, there is a regular waveform in the diagram, where the waveform indicates that the current working state of the excitation rectifying device is normal.

The host computer of the upper computer monitoring system adopts an Intel (R) Celeron (R) processor, and the main frequency is 1.6GHz or more; memory: 4GB and above; hard disk: 500GB and above; industrial liquid crystal touch screen: resolution 1024 x 768; operating system requirements: window7 and higher versions; the upper computer monitoring system monitors the voltage, current, frequency, active power, reactive power, exciting voltage and exciting current of the generator in real time through Ethernet communication and ARM interactive data, the waveform data of the rectification triggering angle and the waveform of the rectification voltage can be displayed in real time and dynamically analyzed, and the background simultaneously stores and records fault and historical data. ARM is connected with the upper computer monitoring system through the high-speed Ethernet interface, the communication rate is 100Mbps, waveform data are transmitted in real time, and the remote client can conveniently store and analyze and process the functions in the background.

Fig. 5 is a schematic diagram showing waveforms of excitation rectifying equipment sent to an upper computer according to an embodiment of the present application, and as shown in fig. 5, waveforms and time of fault alarm can be seen in the upper computer.

Real-time monitoring and data access of the remote upper computer to the excitation rectifying equipment are realized through Ethernet communication. This means that operators who are not on site can also check the waveform data of the equipment in real time, know the running state of the equipment in time, and the maintainability and convenience of the system are enhanced. The remote upper computer can be used for further processing, analyzing and storing the data, so that the monitoring data can be shared and cooperated between different places and departments. This technical effect facilitates collaboration and communication of cross-department, cross-regional equipment management and maintenance. By remotely accessing waveform data of the excitation rectifying equipment, a professional technician can remotely perform fault diagnosis and early warning analysis, so that timeliness and accuracy of fault processing are improved. The technical effect is beneficial to reducing the frequency and time of field maintenance and reducing the maintenance cost. The remote data transmission function accords with the current trend of networking and intellectualization in the industrial monitoring field. Through Ethernet communication, the system can be better integrated into the environments of the Internet of things and the industrial Internet, and the modernization level of equipment monitoring is improved.

The embodiment also discloses a monitoring system of excitation rectifying equipment, fig. 6 is a schematic block diagram of the monitoring system of excitation rectifying equipment disclosed in the embodiment of the application, as shown in fig. 6, the monitoring system includes an acquisition module 601, a waveform module 602, a judging module 603 and a prompting module 604, wherein:

The acquisition module 601 is configured to acquire a first monitoring signal of the generator excitation rectifying device through the digital signal processor 701, where the first monitoring signal includes a voltage signal, a current signal and a frequency signal, and format-convert the first monitoring signal to obtain a second monitoring signal and send the second monitoring signal to the high-performance simplified instruction set processor 701;

A waveform module 602 configured to collect waveform data of the generator excitation rectifying device by the high performance reduced instruction set processor 701 and generate a rectified waveform by the waveform data;

A judging module 603 configured to judge whether the rectified waveform is consistent with a preset waveform and whether the value of the second monitoring signal is consistent with the value of the rectified waveform;

And the prompting module 604 is configured to prompt the generator excitation rectifying device to fail when the rectified waveform is inconsistent with a preset waveform or the value of the second monitoring signal is inconsistent with the value of the rectified waveform.

Optionally, the acquisition module 601 is configured to:

The second monitor signal is sent to the high performance reduced instruction set processor 701 through the field programmable gate array.

Optionally, the acquisition module 601 is further configured to:

Checking whether a transmission mark exists in a memory of the digital signal processor 701 when the digital signal processor 701 transmits data to the field programmable gate array;

Checking whether a receiving area of the field programmable gate array has space or not when a transmission mark exists in the memory of the digital signal processor 701;

Optionally, the acquisition module 601 is further configured to:

When the space of the receiving area of the field programmable gate array is full, the amount of data transmitted by the digital signal processor 701 is decremented until zero.

Optionally, the acquisition module 601 is further configured to:

Optionally, the monitoring system further comprises a storage module configured to:

sample point data is stored into the synchronous dynamic random access memory 705 by the high performance reduced instruction set processor 701, and waveform data is stored into the secure digital card, wherein the acquisition frequency of the high performance reduced instruction set processor 701 is dynamically adjusted according to the frequency of the digital signal processor 701.

Optionally, the monitoring system further comprises a remote module configured to:

when a request to view waveforms remotely is received, the data in the high performance reduced instruction set processor 701 is transmitted to a remote host computer via ethernet communication.

It should be noted that: in the device provided in the above embodiment, when implementing the functions thereof, only the division of the above functional modules is used as an example, in practical application, the above functional allocation may be implemented by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to implement all or part of the functions described above. In addition, the embodiments of the apparatus and the method provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the embodiments of the method are detailed in the method embodiments, which are not repeated herein.

The embodiment also discloses an electronic device, referring to fig. 7, the electronic device may include: at least one processor 701, at least one communication bus 702, a user interface 703, a network interface 704, at least one memory 705.

Wherein the communication bus 702 is used to enable connected communications between these components.

The user interface 703 may include a Display screen (Display), a Camera (Camera), and the optional user interface 703 may further include a standard wired interface, and a wireless interface.

The network interface 704 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Wherein the processor 701 may include one or more processing cores. The processor 701 connects various portions of the overall server using various interfaces and lines, performs various functions of the server and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 705, and invoking data stored in the memory 705. Alternatively, the processor 701 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 701 may integrate one or a combination of several of a central processor 701 (Central Processing Unit, CPU), an image processor 701 (Graphics Processing Unit, GPU), a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 701 and may be implemented by a single chip.

The Memory 705 may include a random access Memory 705 (Random Access Memory, RAM), or may include a Read-Only Memory 705 (Read-Only Memory). Optionally, the memory 705 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 705 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 705 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the storage data area may store data or the like involved in the above respective method embodiments. The memory 705 may also optionally be at least one storage device located remotely from the processor 701. As shown, an operating system, a network communication module, a user interface module, and an application program of a monitoring method of the excitation rectifying device may be included in the memory 705 as one type of computer storage medium.

In the electronic device shown in fig. 7, the user interface 703 is mainly used for providing an input interface for a user, and acquiring data input by the user; and the processor 701 may be used to invoke an application program in the memory 705 that stores the monitoring method of the excitation rectifying device, which when executed by the one or more processors 701, causes the electronic device to perform the method as in one or more of the embodiments described above.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all of the preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory 705. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory 705, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. Whereas the aforementioned memory 705 includes: various media capable of storing program codes, such as a U disk, a mobile hard disk, a magnetic disk or an optical disk.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a scope and spirit of the disclosure being indicated by the claims.

Claims

1. A method of monitoring an excitation rectifier device, the method being applied to a power monitoring platform, the power monitoring platform comprising a digital signal processor and a high performance reduced instruction set processor, the method comprising:

Collecting a first monitoring signal of generator excitation rectifying equipment through the digital signal processor, wherein the first monitoring signal comprises a voltage signal, a current signal and a frequency signal, performing format conversion on the first monitoring signal to obtain a second monitoring signal, and transmitting the second monitoring signal to a high-performance simplified instruction set processor;

2. The method of claim 1, wherein the performing format conversion on the first monitoring signal to obtain a second monitoring signal and sending the second monitoring signal to a high-performance reduced instruction set processor comprises:

3. The method of monitoring an excitation rectifier device according to claim 2, wherein said transmitting the second monitoring signal to a field programmable gate array comprises:

4. The method of monitoring an excitation rectifier device of claim 3 wherein said transmitting said second monitoring signal to a field programmable gate array includes:

5. The method of monitoring an excitation rectifier device according to claim 2, wherein said transmitting the second monitoring signal to a field programmable gate array comprises:

6. The method of monitoring an excitation rectifying device according to claim 1, characterized in that the method of monitoring further comprises:

7. The method of monitoring an excitation rectifying device according to claim 1, characterized in that the method of monitoring further comprises:

8. The utility model provides a monitoring system of excitation rectifying device which characterized in that, including collection module, waveform module, judgement module and suggestion module, wherein:

9. An electronic device comprising a processor, a memory, a user interface, and a network interface, the memory for storing instructions, the user interface and the network interface each for communicating with other devices, the processor for executing instructions stored in the memory to cause the electronic device to perform the method of any of claims 1-7.

10. A computer readable storage medium storing instructions which, when executed, perform the method of any one of claims 1-7.