CN117855222A

CN117855222A - Driving backboard, manufacturing method thereof, display panel and display device

Info

Publication number: CN117855222A
Application number: CN202410033442.XA
Authority: CN
Inventors: 李卓; 冯煊; 刘立伟; 玄明花; 刘冬妮; 杨明; 韩承佑; 张慧; 张定昌
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-04-09

Abstract

The embodiment of the disclosure provides a driving backboard, a manufacturing method thereof, a display panel and a display device, and belongs to the technical field of display. The drive backboard comprises a substrate base plate and a drive circuit layer, wherein the drive circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially laminated on the first surface of the substrate base plate, the source drain layer comprises a plurality of signal wires, the plurality of signal wires extend along a first direction and are arranged along a second direction, and the first direction and the second direction are intersected. The driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is located on the active layer, in at least one pixel driving circuit, active areas of the at least two thin film transistors are connected through the first connecting wire, and orthographic projection of the first connecting wire on the first surface is at least partially overlapped with orthographic projection of the signal wire on the first surface. The embodiment of the disclosure can improve the resolution of the display panel.

Description

Driving backboard, manufacturing method thereof, display panel and display device

Technical Field

The embodiment of the disclosure relates to the technical field of display, in particular to a driving backboard, a manufacturing method thereof, a display panel and a display device.

Background

The display device has wide application scenes in life, such as electronic equipment of mobile phones, tablet computers and the like. The display panel is an important component of the display device. The display panel includes a stacked driving back plate and a light emitting function layer.

In the related art, the driving back plate includes a substrate base plate and a driving circuit layer on a first surface of the substrate base plate, the driving circuit layer including a plurality of pixel driving circuits. The area of the orthographic projection of the pixel driving circuit on the first surface is larger, resulting in lower resolution of the display panel.

Disclosure of Invention

The embodiment of the disclosure provides a display panel, a manufacturing method thereof and a display device, and can improve the resolution of the display panel. The technical scheme is as follows:

in one aspect, a driving back plate is provided, the driving back plate includes a substrate and a driving circuit layer, the driving circuit layer includes an active layer, a gate layer and a source drain layer sequentially stacked on a first surface of the substrate, the source drain layer includes a plurality of signal lines, each of the plurality of signal lines extends along a first direction and is arranged along a second direction, and the first direction and the second direction intersect; the driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is positioned in the active layer, at least one pixel driving circuit is characterized in that the active areas of at least two thin film transistors are connected through the first connecting wire, and the orthographic projection of the first connecting wire on the first surface is at least partially overlapped with the orthographic projection of the signal wire on the first surface.

Optionally, the plurality of signal lines includes a first power line, and an orthographic projection of the first connection line on the first surface is located in the orthographic projection of the first power line on the first surface; alternatively, the plurality of signal lines includes a data line, and the orthographic projection of the first connection line on the first surface is located in the orthographic projection of the data line on the first surface.

Optionally, the plurality of signal lines includes a first power line and a data line; the pixel driving circuit further comprises a second connecting line, wherein the second connecting line is connected with the active areas of at least two thin film transistors, and the at least two thin film transistors connected with the second connecting line are different from the at least two thin film transistors connected with the first connecting line; the front projection of the first connecting line on the first surface is positioned in the front projection of the first power line on the first surface, and the front projection of the second connecting line on the first surface is positioned in the front projection of the data line on the first surface.

Optionally, the plurality of signal lines includes a first power line and a data line; the pixel driving circuit further comprises a second connecting line, wherein the second connecting line is connected with the active areas of at least two thin film transistors, and the at least two thin film transistors connected with the second connecting line are different from the at least two thin film transistors connected with the first connecting line; the front projection of the first connecting line on the first surface is positioned in the front projection of the first power line on the first surface, and the front projection of the second connecting line on the first surface is positioned outside the front projection of the data line on the first surface.

Optionally, the orthographic projection of the second connection line on the first surface is located between the orthographic projection of the data line on the first surface and the orthographic projection of the first power line on the first surface.

Optionally, the pixel driving circuit further includes a third connection line located at the active layer and connected between the first connection line and the second connection line; the at least two thin film transistors comprise driving transistors, and active areas of the driving transistors are located in the third connecting line.

Optionally, an orthographic projection of the active region of the driving transistor on the first surface is long-strip-shaped and extends along the second direction.

Optionally, the orthographic projection of the active region of the driving transistor on the first surface includes a first portion, a second portion and a third portion which are sequentially connected, the first portion and the third portion extend along the second direction, and the second portion extends along the first direction.

Optionally, the driving circuit layer further includes a light shielding layer, the light shielding layer being located between the substrate base plate and the active layer, the light shielding layer including a plurality of light shielding structures; the orthographic projection of the active region of the driving transistor on the first surface is positioned in the orthographic projection of the shading structure on the first surface; the source electrode of the driving transistor is electrically connected with the shading structure.

Optionally, the pixel driving circuit includes a storage capacitor, a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor, where the fifth thin film transistor is the driving transistor; the active region of the first thin film transistor, the active region of the third thin film transistor and the active region of the fourth thin film transistor are located in the first connection line; the active region of the second thin film transistor, the active region of the sixth thin film transistor and the active region of the seventh thin film transistor are located in the second connecting line; the driving backboard further comprises a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line and an initial signal line, wherein the control electrode of the first thin film transistor is connected with the third scanning signal line, the control electrode of the second thin film transistor is connected with the first scanning signal line, the control electrode of the third thin film transistor is connected with the second scanning signal line, the control electrode of the fourth thin film transistor is connected with the light-emitting signal line, the control electrode of the sixth thin film transistor is connected with the light-emitting signal line, and the control electrode of the seventh thin film transistor is connected with the second scanning signal line; the first electrode of the first thin film transistor is electrically connected to the first power line, the second electrode of the first thin film transistor, the first electrode of the third thin film transistor, the control electrode of the fifth thin film transistor and the first end of the storage capacitor are electrically connected, the second electrode of the third thin film transistor, the fourth thin film transistor and the second electrode of the first electrode of the fifth thin film transistor are electrically connected, the second end of the storage capacitor, the first electrode of the second thin film transistor and the second electrode of the sixth thin film transistor are electrically connected, the second electrode of the fifth thin film transistor, the first electrode of the sixth thin film transistor and the first electrode of the seventh thin film transistor are electrically connected, the second electrode of the second thin film transistor is electrically connected to the initial signal line, the first electrode of the fourth thin film transistor is electrically connected to the first power line, and the second electrode of the seventh thin film transistor is electrically connected to the data line.

Optionally, the storage capacitor includes a first polar plate located on the light shielding layer, a second polar plate located on the gate layer, and a third polar plate located on the source drain layer, where the orthographic projection of the first polar plate on the first surface and the orthographic projection of the second polar plate on the first surface at least partially coincide, the orthographic projection of the third polar plate on the first surface and the orthographic projection of the second polar plate on the first surface at least partially coincide, and the first polar plate is electrically connected with the third polar plate.

Optionally, the driving backboard further includes a transfer via hole, the transfer via hole includes a first portion and a second portion, the first portion and the second portion are connected in a direction parallel to the first surface, the first portion is used for connecting a first transfer structure and a second transfer structure, the second portion is used for connecting the first transfer structure and a third transfer structure, wherein the first transfer structure is located in the source drain layer, the second transfer structure is located in the active layer or the gate layer, and the third transfer structure is located in the light shielding layer; the first switching structure is the first power line, the second switching structure is the first pole of the first thin film transistor, and the third switching structure is a wiring positioned on the shading layer; or, the first switching structure is a switching part located on the source drain layer, the second switching structure is a second pole of the second thin film transistor, and the third switching structure is the initial signal line.

In another aspect, a method for manufacturing a driving backboard is provided, the method including: providing a substrate; manufacturing a driving circuit layer on the surface of the substrate; the driving circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially laminated on the first surface of the substrate, the source drain layer comprises a plurality of signal wires, the plurality of signal wires extend along a first direction and are arranged along a second direction, the first direction and the second direction are intersected, the driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is located in the active layer, at least one pixel driving circuit is arranged, active areas of at least two thin film transistors are connected through the first connecting wire, and orthographic projection of the first connecting wire on the first surface and orthographic projection of the signal wire on the first surface are at least partially overlapped.

Optionally, the display panel includes a stacked light-emitting functional layer and any one of the foregoing driving back plates, and the driving back plate is used for driving the light-emitting functional layer to emit light.

In yet another aspect, a display device is provided, the display device including a power supply circuit and the aforementioned display panel, the power supply circuit supplying power to the display panel.

The beneficial effects that this disclosure provided technical scheme brought include at least: by enabling the orthographic projection of the first connecting wire on the first surface and the orthographic projection of the signal wire on the first surface to be at least partially overlapped in the pixel driving circuit, the occupied area of the pixel driving circuit is reduced, so that a display panel with smaller pixel size can be manufactured conveniently, and the resolution of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is an equivalent circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

FIG. 2 is a schematic plan view of a driving back plate according to an embodiment of the disclosure;

FIG. 3 is a schematic plan view of a plurality of membrane layers in the driving back plate of FIG. 2;

FIG. 4 is a schematic cross-sectional view taken along line AA in FIG. 2;

FIG. 5 is a schematic plan view of another drive back plate according to an embodiment of the present disclosure;

FIG. 6 is a schematic plan view of a plurality of membrane layers in the alternative driving backplate of FIG. 5;

FIG. 7 is a schematic plan view of another drive back plate according to an embodiment of the present disclosure;

FIG. 8 is a schematic plan view of a plurality of membrane layers in the alternative driving backplate of FIG. 7;

fig. 9 is a flowchart illustrating a method for manufacturing a driving back board according to an embodiment of the disclosure.

Legend description:

x, first direction y, second direction

10. Substrate base plate 10a, first surface

20. Drive circuit layer

21. An active layer 211, a first connection line 212, a second connection line 213, an active region 213a of the driving transistor, a first portion 213b of the active region of the driving transistor, a second portion 213c of the active region of the driving transistor, a third portion 214 of the active region of the driving transistor, a third connection line 215, a first extension 216, a second extension

22. Gate layer 221, second electrode plate

23. Source/drain electrode layer 230, signal line 231, first power line 232, data line 233, third electrode plate 234, connection portion 235, and switching portion

24. Light shielding layer 241, first electrode plate 242, wiring 243 for transmitting VDD signal, light shielding structure

25. Buffer layer 26, gate insulating layer 27, insulating layer 28, and planarizing layer

31. First via 32, second via 33, third via 34, fourth via 34a, first portion of fourth via 34b, second portion of fourth via 35, fifth via 36, sixth via 37, seventh via 38, eighth via 39, ninth via

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," "third," and the like in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. References to directional terms in this disclosure, such as "top", "bottom", "upper", "lower", "left" or "right", etc., are merely with reference to the orientation of the drawings, and thus are used in order to better and more clearly illustrate and understand the disclosed embodiments, rather than to indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the disclosed embodiments.

Embodiments of the present disclosure provide a drive backplate. The driving backboard comprises a substrate base plate and a driving circuit layer, wherein the driving circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially laminated on the first surface of the substrate base plate. The source drain electrode layer comprises a plurality of signal lines, the plurality of signal lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction are intersected. The driving circuit layer includes a plurality of pixel driving circuits, each including at least two TFTs (Thin Film Transistor, thin film transistors) and a first connection line located at the active layer. In at least one pixel driving circuit, the active regions of at least two TFTs are connected by a first connecting line, and the orthographic projection of the first connecting line on the first surface is at least partially overlapped with the orthographic projection of the signal line on the first surface.

The first connection line includes a region which is conductive and is not metallized, and the active regions of at least two TFTs are connected by the first connection line, which means that the active regions of at least two TFTs are located in the region which is not metallized in the first connection line, and the electrical connection is achieved by the region which is conductive and is metallized in the first connection line.

In the related art, in order to avoid the channel portion of the thin film transistor, most of the area is occupied when the wiring is arranged, so that the area of orthographic projection of the pixel driving circuit on the first surface is larger, which is not beneficial to improving the resolution of the display panel. In the embodiment of the disclosure, the active area is arranged in the first connecting line, and the front projection of the first connecting line on the first surface and the front projection of the signal line on the first surface are at least partially overlapped, so that the area of the front projection of the pixel driving circuit on the first surface is reduced, the arrangement of pixels with smaller size on the display panel is facilitated, and the resolution of the display panel is improved.

In one possible embodiment, the plurality of signal lines includes a first power line, and the orthographic projection of the first connection line on the first surface is located within the orthographic projection of the first power line on the first surface. In another possible embodiment, the plurality of signal lines includes data lines, and the orthographic projection of the first connection line on the first surface is located within the orthographic projection of the data line on the first surface. The front projection of the first connecting wire on the first surface is completely arranged in the front projection of the first power wire on the first surface, or the front projection of the second connecting wire on the first surface is completely arranged in the front projection of the data wire on the first surface, so that the area of the front projection of the pixel driving circuit on the first surface can be reduced as much as possible, and the resolution of the display panel can be further improved.

In an embodiment of the present disclosure, each pixel driving circuit includes at least two TFTs. The pixel driving circuit may be of a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C or 8T1C structure according to the number of TFTs and the number of storage capacitors Cst included in each pixel driving circuit.

For a pixel driving circuit including a large number of TFTs, for example, a 7T1C pixel driving circuit, the pixel driving circuit further includes a second connection line for connecting the active regions of at least two TFTs in addition to the first connection line due to the large number of TFTs, and at least two TFTs connected to the first connection line are different from at least two TFTs connected to the second connection line.

Since the plurality of signal lines include the first power supply line and the data line, in the pixel driving circuit, the projection relationship of the connection line and the signal line may include the following two cases:

the first type is that the orthographic projection of the first connecting wire on the first surface is positioned in the orthographic projection of the first power wire on the first surface, and the orthographic projection of the second connecting wire on the first surface is positioned in the orthographic projection of the data wire on the first surface;

the second type, the orthographic projection of the first connecting line on the first surface is positioned in the orthographic projection of the first power line on the first surface, and the orthographic projection of the second connecting line on the first surface is positioned outside the orthographic projection of the data line on the first surface;

Third, the orthographic projection of the first connecting line on the first surface is located outside the orthographic projection of the first power line on the first surface, and the orthographic projection of the second connecting line on the first surface is located in the orthographic projection of the data line on the first surface.

Experiments prove that for the signal wire above the connecting wire, no matter the electric signal in the signal wire is a constant signal or a non-constant signal, the influence of the signal wire on the connecting wire is small, namely the influence of the signal wire on the TFT is small, so that the signal wire above the connecting wire can be a first power wire for transmitting the constant electric signal or a data wire for transmitting the non-constant electric signal.

Hereinafter, a driving back plate provided by an embodiment of the present disclosure will be exemplarily described using a 7T1C pixel driving circuit as an example.

Fig. 1 is an equivalent circuit diagram of a pixel driving circuit provided in an embodiment of the present disclosure. As shown in fig. 1, one pixel driving circuit includes one storage capacitor Cst and seven TFTs, which are a first TFT T1, a second TFT T2, a third TFT T3, a fourth TFT T4, a fifth TFT T5, a sixth TFT T6, and a seventh TFT T7, respectively. Each TFT includes a first electrode located on the source/drain layer 23 or the active layer 21 (e.g., a portion of the active layer 21 is metallized to form a first electrode), a second electrode located on the source/drain layer 23 or the active layer 21 (e.g., a portion of the active layer 21 is metallized to form a second electrode), and a control electrode located on the gate layer 22 for controlling whether or not conduction is performed between the first and second electrodes.

In the embodiment of the disclosure, the control electrode is a gate electrode, the first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the control electrode is a gate electrode, the first electrode is a drain electrode, and the second electrode is a source electrode.

As shown in fig. 1, the pixel driving circuit is connected to 7 signal lines including a first power line 231, a data line 232, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light emitting signal line EM, and an initial signal line Vinit. The first, second, and third scan signal lines 31, 32, and 33 are configured to supply on signals to the pixel driving circuits, respectively, the light emitting signal line EM is configured to supply a light emitting control signal to the pixel driving circuits, and the initial signal line Vinit, the DATA line 232, and the first power line 231 are configured to supply an initial voltage signal, a DATA voltage (also referred to as a DATA signal), and a first voltage signal (also referred to as a VDD signal) to the pixel driving circuits, respectively.

As shown in fig. 1, the control electrode of the first TFT T1 is connected to the third scan signal line S3, the first electrode of the first TFT T1 is for receiving the VDD signal, and the second electrode of the first TFT T1 is connected to the first node N1. When the on signal is applied to the third scan signal line S3, the first TFT T1 is turned on, and transmits a first voltage signal to the first node N1.

The first terminal of the storage capacitor Cst is connected to the first node N1, and the second terminal of the storage capacitor Cst is connected to the fourth node N4.

The control electrode of the second TFT T2 is connected to the first scan signal line S1, the first electrode of the second TFT T2 is connected to the fourth node N4, and the second electrode of the second TFT T2 is connected to the initial signal line Vinit. The fourth node N4 is also electrically connected to the first electrode of the light emitting device EL controlled by the pixel driving circuit. When a turn-on signal is applied to the first scan signal line S1, the second TFT T2 is turned on, transmits an initialization voltage to the fourth node N4, and initializes the second terminal of the storage capacitor C and the first electrode of the light emitting device EL.

The control electrode of the third TFT T3 is connected to the second scan signal line S2, the first electrode of the third TFT T3 is connected to the first node N1, and the second electrode of the third TFT T3 is connected to the second node N2.

The control electrode of the fourth TFT T4 is connected to the emission signal line EM, the first electrode of the fourth TFT T4 is connected to the second node N2 for receiving the VDD signal, and the second electrode of the fourth TFT T4 is connected to the second node N2.

The control electrode of the fifth TFT T5 is connected to the first node N1, the first electrode of the fifth TFT T5 is connected to the second node N2, and the second electrode of the fifth TFT T5 is connected to the third node N3. The fifth TFT T5 may be referred to as a driving transistor, and the fifth TFT T5 determines the magnitude of the driving current of the light emitting device EL according to the potential difference between its control electrode and the first electrode.

The control electrode of the sixth TFT T6 is connected to the emission signal line EM, the first electrode of the sixth TFT T6 is connected to the third node N3, and the second electrode of the sixth TFT T6 is connected to the fourth node N4.

The control electrode of the seventh TFT T7 is connected to the second scan signal line S2, the second electrode of the seventh TFT T7 is connected to the data line, and the first electrode of the seventh TFT T7 is connected to the third node N3.

In the embodiment of the present disclosure, the driving back plate further includes a second power line (VSS), the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power line VSS.

The light emitting device EL may be an OLED (Organic Light Emitting Diode ) including a first electrode, an organic light emitting layer, and a second electrode sequentially stacked; alternatively, the light emitting device EL is a QLED (Quantum Dot Light Emitting Diode ) including a first electrode, a quantum dot light emitting layer, and a second electrode stacked in this order.

Illustratively, the first power line supplies a constant VDD signal to the pixel driving circuit, the second power line supplies a constant second voltage signal (also referred to as a VSS signal) to the light emitting device EL, and the VDD signal is greater than the VSS signal. The initial signal line Vinit supplies an initial voltage signal to the pixel driving circuit, and the initial voltage signal may be a constant voltage signal, and the magnitude thereof may be less than or equal to the VSS signal, which is not limited herein. For example, the VDD signal has a magnitude range of 7V to 15V, the VSS signal has a magnitude range of 0V to 5V, the initial voltage signal has a magnitude range of 0V to 5V, and the initial voltage signal is smaller than the VSS signal.

The plurality of TFTs of the pixel driving circuit may be N-type transistors, or may be P-type transistors, for example. The pixel driving circuit adopts the transistors of the same type, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved. Alternatively, among the plurality of TFTs of the pixel driving circuit, part of the TFTs may be N-type transistors and part of the TFTs may be P-type transistors.

The operation of the pixel driving circuit and the layout of the pixel driving circuit will be described below taking the example in which the first to seventh TFTs T1 to T7 included in the pixel driving circuit are N-type transistors.

The operation of the pixel driving circuit may include the following three stages.

The first phase, called the initialization phase. The first scan signal line S1 and the third scan signal line S3 supply a high level signal, the second TFT T2 and the first TFT T1 are turned on, and the third TFT T3, the fourth TFT T4, the fifth TFT T5, the sixth TFT T6, and the seventh TFT T7 are turned off. An initial voltage signal supplied from the initial signal line Vinit is transferred to the fourth node N4 through the second TFT T2 to initialize the second terminal of the storage capacitor Cst and the first electrode of the light emitting device EL. The VDD signal provided by the first power line is transferred to the first node N1 through the first TFT T1 to charge the storage capacitor Cst.

The second phase, called the data write phase or the threshold compensation phase. The second scan signal line S2 supplies a high level signal to turn on the third TFT T3 and the seventh TFT T7, and at this time, the fifth TFT T5 is still in an on state, and the other TFTs are not turned on. The DATA signal provided by the DATA line is transferred to the first node N1 through the third node N3, the fifth TFT T5, the second node N2, and the turned-on third TFT T3, in which the sum of the DATA signal and the threshold voltage of the fifth TFT T5 is written into the first terminal of the storage capacitor Cst.

The third phase, called the light-emitting phase. The light emitting signal line EM supplies a high level signal to turn on the fourth TFT T4 and the sixth TFT T6, and at this time, the fifth TFT T5 is still in a turned-on state, and the other TFTs are turned off. The first voltage signal supplied from the first power line 231 is transferred to the first electrode of the light emitting device EL through the fourth, fifth and sixth TFTs T4, T5 and T6, and drives the light emitting device EL to emit light.

Fig. 2 is a schematic plan view of a driving back plate according to an embodiment of the disclosure, which shows a structure of a 7T1C pixel driving circuit. Fig. 3 is a schematic plan view of a plurality of film layers in the driving backplate of fig. 2, and fig. 3 (a) is a schematic plan view of the light shielding layer 24 in the embodiment of fig. 2, fig. 3 (b) is a schematic plan view of the active layer 21 in the embodiment of fig. 2, fig. 3 (c) is a schematic plan view of the gate layer 22 in the embodiment of fig. 2, and fig. 3 (d) is a schematic plan view of the source/drain layer 23 in the embodiment of fig. 2.

It should be noted that, fig. 2 and 3 only show one pixel driving circuit by way of example, and the driving back plate includes a plurality of pixel driving circuits shown in fig. 2, and the plurality of pixel driving circuits may be arrayed along the first direction x and the second direction y. In the embodiment of the disclosure, the first direction x is a row direction, and the second direction y is a column direction; alternatively, the first direction x is a column direction and the second direction y is a row direction.

The first case described above is exemplified below. Illustratively, as shown in fig. 2 and 3, the front projection of the first connection line 211 on the first surface 10a is located within the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a is located within the front projection of the data line 232 on the first surface 10 a. The front projection of the first connection line 211 on the first surface 10a is completely disposed in the front projection of the first power line 231 on the first surface 10a, the front projection of the second connection line 212 on the first surface 10a is completely disposed in the front projection of the data line 232 on the first surface 10a, so that the area of the front projection of the pixel driving circuit on the first surface 10a can be reduced as much as possible, thereby facilitating the arrangement of pixels with smaller size on the display panel, and being beneficial to further improving the resolution of the display panel.

In other possible embodiments, the front projection of the first connection line 211 on the first surface 10a coincides with the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a coincides with the front projection of the data line 232 on the first surface 10 a. Alternatively, the front projection of the first connection line 211 on the first surface 10a is located within the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a overlaps with the front projection of the data line 232 on the first surface 10 a. Alternatively, the front projection of the first connection line 211 on the first surface 10a overlaps with the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a is located within the front projection of the data line 232 on the first surface 10 a. Illustratively, the orthographic projection of the first connection line 211 on the first surface 10a coincides with the orthographic projection of the first power line 231 on the first surface 10a, which may be a portion of the orthographic projection of the first connection line 211 on the first surface 10a that does not coincide with the orthographic projection of the first power line 231 on the first surface 10a in the second direction y, and is located at a side of the portion of the orthographic projection of the first connection line 211 on the first surface 10a that coincides with the orthographic projection of the first power line 231 on the first surface 10 a. The same applies to the case where the front projection of the second connection line 212 on the first surface 10a coincides with the front projection of the data line 232 on the first surface 10a, which is not described herein.

Illustratively, as shown in fig. 2 and 3, the active layer 21 further includes a plurality of first protrusions 215 and a plurality of second protrusions 216. The plurality of first protruding portions 215 are connected to the first connection line 211 and extend in a direction approaching the second connection line 212, and the plurality of second protruding portions 216 are connected to the second connection line 212 and extend in a direction approaching the first connection line 211. A via may be provided at the plurality of first protrusions 215 and the plurality of second protrusions 216 so that the first connection line 211 is electrically connected with other structures and the second connection line 212 is electrically connected with other structures.

Illustratively, as shown in fig. 2 and 3, the driving circuit layer 20 further includes a light shielding layer 24, the light shielding layer 24 being located between the substrate base 10 and the active layer 21. Illustratively, the light shielding layer 24 includes a plurality of light shielding structures 243, and the orthographic projection of the active region of the fifth TFT T5 on the first surface 10a is located within the orthographic projection of the light shielding structures 243 on the first surface 10 a.

Referring to fig. 2 and 3, the light emitting signal line EM, the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are all located in the gate layer 22, the initial signal line Vinit is located in the light shielding layer 24, the first power line 231 is electrically connected to the trace 242 for transmitting the VDD signal located in the light shielding layer 24 and extending in the second direction y, and the trace 242 for transmitting the VDD signal is electrically connected to the first power line 231 through the fourth via 34.

Alternatively, the front projection of each row of pixel driving circuits on the first surface 10a coincides with the front projection of the wiring 242 on the light shielding layer 24 for transmitting VDD signals on the first surface 10a, that is, each wiring 242 for transmitting VDD signals corresponds to one row of pixel driving circuits.

Illustratively, the shapes of the trace 242, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the light emitting signal line EM, and the initial signal line Vinit, which transfer the VDD signal, are straight or approximately straight and extend in the second direction y, and the shapes of the data line 232 and the first power line 231 are straight or approximately straight and extend in the first direction x. Alternatively, in the first direction x, the wiring 242 transmitting the VDD signal, the third scan signal line S3, the second scan signal line S2, the light emitting signal line EM, the first scan signal line S1, and the initial signal line Vinit are sequentially arranged.

In the embodiment of the present disclosure, for the first TFT T1, the second TFT T2, the third TFT T3, the fourth TFT T4, the fifth TFT T5, the sixth TFT T6, and the seventh TFT T7, both the first pole and the second pole are located at the active layer 21, and the control pole is located at the gate layer 22. The first end of the storage capacitor Cst is located at the gate layer 221, and the second end of the storage capacitor Cst is located at the light shielding layer 24 and the source drain layer 23.

As shown in fig. 2, the first connection line 211 connects the active regions of the first TFT T1, the third TFT T3, and the fourth TFT T4, that is, the active regions of the first TFT T1, the third TFT T3, and the fourth TFT T4 are a part of the first connection line 211 and this part is not subjected to a metallization process, and the parts of the first connection line 211 other than the above active regions and the plurality of first protruding portions 215 are subjected to a metallization process, and are changed from a semiconductor to a conductor, and are able to conduct electricity.

As shown in fig. 2, the first power line 231 is electrically connected to the first electrode of the first TFT T1 through the fourth via hole 34, and the portion of the active layer 21 located above the dotted line frame illustrating the first TFT T1 in fig. 2 is capable of conducting electricity through a metallization process, and the portion of the active layer 21 is the first electrode of the first TFT T1. Fig. 4 is a schematic cross-sectional structure along the AA cross-sectional line in fig. 2, as shown in fig. 2 and 4, the wiring 242 for transmitting the VDD signal is disposed in the light shielding layer 24, the fourth via hole 34 is also referred to as a transfer via hole, the fourth via hole 34 includes a first portion 34a and a second portion 34b, the first portion 34a and the second portion 34b are connected in a direction parallel to the first surface 10a, the first portion 34a is used for connecting the first transfer structure and the second transfer structure, and the second portion 31b is used for connecting the first transfer structure and the third transfer structure. Here, the first switching structure refers to the first power line 231, the second switching structure refers to the first pole of the first TFT T1, and the third switching structure refers to the trace 242 for transmitting the VDD signal. The design can simultaneously and electrically connect three structures respectively positioned on three film layers in one opening, achieves the purposes of electrically connecting the wiring 242 for transmitting VDD signals with the first power line 231 and electrically connecting the first power line 231 with the first pole of the first TFT T1 in the shading layer, and is convenient for saving wiring space, thereby reducing the orthographic projection area of the pixel driving circuit on the first surface 10a as much as possible and being beneficial to improving the resolution of the display panel.

Illustratively, the first portion 31a is located in the insulating layer between the source and drain layer 23 and the active layer 21, and the second portion 31b is located in the insulating layer between the source and drain layer 23 and the light shielding layer 24.

As shown in fig. 2, the gate electrode of the first TFT T1 is electrically connected to the third scan line S3, and may be, for example, a part of the third scan line S3, including at least a part of the third scan line S3 overlapping the first connection line 211.

As shown in fig. 2, the portion of the active layer located between the dotted line frame illustrating the corresponding first TFT T1 and the dotted line frame illustrating the third TFT T3 can be electrically conductive through the metallization process, and the portion of the active layer 21 is the second pole of the first TFT T1 as well as the first pole of the third TFT T3. The gate electrode of the third TFT T3 is electrically connected to the second scan line S2, and may be, for example, a part of the second scan line S2, including at least a part where the second scan line S2 overlaps the first connection line 211.

As shown in fig. 2, the portion of the active layer located between the dotted line frame illustrating the corresponding third TFT T3 and the dotted line frame illustrating the fourth TFT T4 can be electrically conductive through the metallization process, and the portion of the active layer 21 is the second pole of both the third TFT T3 and the fourth TFT T4. The control electrode of the fourth TFT T4 is electrically connected to the emission signal line EM, and may be, for example, a part of the emission signal line EM, including at least a part where the emission signal line EM overlaps the first connection line 211. The portion of the active layer located under the dotted line frame corresponding to the fourth TFT T4 illustrated is capable of conducting electricity through a metallization process, and the portion of the active layer 21 may be referred to as a first pole of the fourth TFT T4 and is electrically connected to the first power line 231 through the seventh via hole 37. The seventh via hole 37 is located between the source and drain layer 23 and the active layer 21.

As shown in fig. 2, the second connection line 212 connects the active regions of the second TFT T2, the sixth TFT T6, and the seventh TFT T7, that is, the active regions of the second TFT T2, the sixth TFT T6, and the seventh TFT T7 are a part of the second connection line 212, and this part is not subjected to a metallization process, and the parts of the second connection line 212 other than the active regions and the plurality of second protrusions 216 are subjected to a metallization process, and are changed from a semiconductor to a conductor, and thus, can conduct electricity.

As shown in fig. 2, the portion of the active layer located under the dotted line frame illustrating the second TFT T2 in fig. 2 and which is capable of conducting electricity through a metallization process, the portion of the active layer 21 is the second pole of the second TFT T2. An initial signal line Vinit is arranged in the light shielding layer 24, and at the second via hole 32, the light shielding layer 24, the source drain layer 23 and the active layer 21 are electrically connected, so that the purpose that a wiring for transmitting VDD signals is arranged in the light shielding layer and the second electrode of the second TFT T2 are electrically connected is achieved. The second via 32 is also called a switching via, the cross-sectional structure of the second via 32 is similar to that of the fourth via 34, and for the first switching structure, the second switching structure and the third switching structure connected to the second via 32, the first switching structure refers to the switching portion 235 of the source drain layer 23, the second switching structure refers to the second pole of the second TFT T2, and the third switching structure refers to the initial signal line Vinit. The gate electrode of the second TFT T2 is electrically connected to the first scanning signal line S1, and may be, for example, a part of the first scanning signal line S1, and at least includes a part where the first scanning signal line S1 overlaps the second connection line 212. The effect of the second via 32 is the same as that of the fourth via 34, so that the wiring space can be saved, and the description thereof will not be repeated here.

As shown in fig. 2, the portion of the active layer located between the dotted line frame illustrating the corresponding second TFT T2 and the dotted line frame illustrating the sixth TFT T6 can be electrically conductive through the metallization process, and the portion of the active layer 21 is both the first pole of the second TFT T2 and the second pole of the sixth TFT T6. The control electrode of the sixth TFT T6 is electrically connected to the emission signal line EM, and may be, for example, a part of the emission signal line EM, including at least a part where the emission signal line EM overlaps the second connection line 212.

As shown in fig. 2, the portion of the active layer located between the dotted line frame illustrating the sixth TFT T6 and the dotted line frame illustrating the seventh TFT T7 can be electrically conductive through the metallization process, and the portion of the active layer 21 is the first electrode of both the sixth TFT T6 and the seventh TFT T7. The gate electrode of the seventh TFT T7 is electrically connected to the second scan signal line S2, and may be, for example, a part of the second scan signal line S2, including at least a part where the second scan signal line S2 overlaps the second connection line 212.

As shown in fig. 2, the portion of the active layer located above the dotted line frame illustrating the corresponding seventh TFT T7 can be electrically conductive through the metallization process, and the portion of the active layer 21 is the second pole of the seventh TFT T7. The second pole of the seventh TFT T7 is electrically connected to the data line 232 located in the source/drain layer 23 through the eighth via hole 38. The eighth via 38 is located between the source-drain layer 23 and the active layer 21.

The second pole of the first TFT T1 is connected to one end of the connection portion 234 located in the source/drain layer 23 through the first via hole 31, and the other end of the connection portion 234 is connected to the control pole of the fifth TFT T5 located in the gate layer 22 through the fifth via hole 35, so that the second pole of the first TFT T1 is electrically connected to the control pole of the fifth TFT T5. Illustratively, the connecting portion 234 is a bar-shaped structure, and the extending direction is a first direction x.

Since the control electrode of the fifth TFT T5 and the first end of the storage capacitor Cst are both located in the gate layer 23 and connected, the second electrode of the first TFT T1 is electrically connected to the control electrode of the fifth TFT T5, and meanwhile, the second electrode of the first TFT T1 is electrically connected to the first end of the storage capacitor Cst through the first via hole 31, the connection portion 234, and the fifth via hole 35 in sequence, and the first end of the storage capacitor is the second plate 221 located in the gate layer 22. The first via hole 31 is located between the source/drain layer 23 and the active layer 21, and the fifth via hole 35 is located between the source/drain layer 23 and the gate layer 22.

As shown in fig. 2, the pixel driving circuit further includes a third connection line 214, where the third connection line 214 is connected between the first connection line 211 and the second connection line 212, so as to facilitate the arrangement of an active region, a first pole and a second pole of the fifth TFT T5, where the active region of the fifth TFT T5 is located in the third connection line 214, the first pole and the second pole of the fifth TFT T5 are located in the metallized region of the active layer 21, the first pole of the fifth TFT T5 is located at the left side of the corresponding dashed line frame in the drawing and is electrically connected to the second pole of the third TFT T3, and the second pole of the fifth TFT T5 is located at the right side of the corresponding dashed line frame in the drawing and is electrically connected to the first pole of the seventh TFT T7, and the active region of the fifth TFT T5 is located in the corresponding dashed line frame in the drawing. Optionally, the third connection line 214 is located between the second scan signal line S2 and the light emitting signal line EM. Illustratively, one of the first and second poles of the fifth TFT T5 is a source electrode, and the source electrode is electrically connected to a light shielding structure 243 under the fifth TFT T5, and a structure of the fifth TFT T5 having the light shielding structure 243 and the light shielding structure 243 connected to the source electrode is also referred to as a BS (Bottom Gate Connect Source) structure. Optionally, the source electrode of the fifth TFT T5 is electrically connected to a switching structure located on the source-drain layer, and the switching structure is electrically connected to the light shielding structure 243, so as to electrically connect the source electrode of the fifth TFT T5 to the light shielding structure 243. In other possible embodiments, the source of the fifth TFT T5 is electrically connected through a via between the light shielding layer 24 and the active layer 24.

Since the active layer is located at the side of the gate layer close to the substrate, the fifth TFT T5 of the driving transistor is of a top gate structure, and if no light shielding layer is provided, external light may be emitted into the driving back plate from one side of the substrate, which affects the active region of the driving transistor, for example, generates carriers, increases the concentration of free carriers, and decreases the threshold voltage Vth, thereby causing conduction between the first pole and the second pole of the driving transistor when a smaller voltage is applied to the control pole. In the embodiment of the disclosure, the light shielding layer is arranged below the driving transistor, so that the saturation characteristic of the driving transistor is more stable, the threshold voltage is not influenced by illumination and is reduced, the current of the fifth TFT T5 of the driving transistor is more stable when the gate voltage changes, the brightness of the display panel is more stable, and the display effect is improved.

The second end of the storage capacitor Cst is a first polar plate 241 and a third polar plate 233 which are electrically connected, and the first polar plate 241 and the third polar plate 233 are respectively located on the light shielding layer 24 and the source drain electrode layer 23. The first electrode plate 241 and the third electrode plate 233 are electrically connected through the third via hole 33, and the third electrode plate 233 is electrically connected with the first electrode of the second TFT T2 through the sixth via hole 36, so that the second end of the storage capacitor Cst is electrically connected with the first electrode of the second TFT T2. The third electrode plate 233 is electrically connected to the first electrode of the light emitting device EL controlled by the pixel driving circuit through the ninth via hole 39, and the second end of the storage capacitor Cst is electrically connected to the first electrode of the light emitting device EL controlled by the pixel driving circuit. The third via 33 is located between the light shielding layer 24 and the source drain layer 23, the sixth via 36 is located between the source drain layer 23 and the active layer 21, and the ninth via 39 is located above the source drain layer 23.

The front projection of the first polar plate 241 on the first surface 10a at least partially coincides with the front projection of the second polar plate 233 on the first surface 10a, and the front projection of the third polar plate 233 on the first surface 10a at least partially coincides with the front projection of the second polar plate 221 on the first surface 10 a. Setting Cst as a three-layer structure may increase the capacitance of Cst. Because the gate voltage of the fifth TFT T5 of the driving transistor is influenced by the capacitance of Cst and other coupling capacitances, the capacitance of Cst is increased, the influence duty ratio of Cst to the gate voltage of the fifth TFT T5 can be increased, which is equivalent to reducing the influence duty ratio of other coupling capacitances to the gate voltage of the fifth TFT T5, and is beneficial to stabilizing the gate voltage of the fifth TFT T5.

Illustratively, as shown in fig. 3, the orthographic projection of the active region of the fifth TFT T5 of the driving transistor on the first surface 11a extends along the second direction y, i.e., the active region of the fifth TFT T5 of the driving transistor is in a straight shape, which can save wiring space. On the premise that the orthographic projection area of the pixel driving circuit on the first surface 10a is constant, the active region of the fifth TFT T5 is a part of the active layer 21 located in the corresponding dashed line frame in the drawing, and the control electrode of the fifth TFT T5 is located on the gate layer 22 and directly above the active region of the fifth TFT T5. By reducing the area of the active region of the fifth TFT T5, the area of the control electrode of the fifth TFT T5 is reduced, and since the control electrode of the fifth TFT T5 and the second electrode plate 221 are both located in the gate layer 22, the area of the first end (the second electrode plate 221) for setting the capacitance Cst can be increased, thereby increasing the capacitance of Cst. Since the gate voltage of the fifth TFT T5 of the driving transistor is affected by the capacitance of Cst and other coupling capacitance, increasing the capacitance of Cst can increase the duty ratio of the influence of Cst on the gate voltage of the fifth TFT T5 of the driving transistor, which is beneficial to stabilizing the gate voltage of the driving transistor.

Illustratively, as shown in FIG. 2, the fourth via 34 is located over the trace 242 that conveys the VDD signal. The first and fifth vias 31 and 35 are located at both sides of the second scan signal line S2 in the first direction x, and the first via 31 is located between the second scan signal line S2 and the third scan signal line S3. The connection portion 234 overlaps the second scan signal line S2. The eighth via 38 is located between the second scan signal line S2 and the third scan signal line S3. The third via hole 33 is located at a side of the light emitting signal line EM remote from the first scan signal line S1, and the sixth via hole 36, the seventh via hole 37, and the ninth via hole 39 are located between the first scan signal line S1 and the light emitting signal line EM. The second via 32 is located above the initial signal line Vinit.

Referring again to fig. 4, the driving circuit layer further includes other film layers, and the following exemplifies the structure of each layer in the driving back plate by taking the embodiment shown in fig. 4 as an example. As shown in fig. 4, the driving circuit layer 20 includes a light shielding layer 24, a buffer layer 25, an active layer 21, a gate insulating layer 26, a gate layer 22 (not shown in fig. 4), an interlayer dielectric layer 27, a source drain layer 23, and a planarization layer 28, which are sequentially stacked on the first surface 10a of the substrate 10.

Illustratively, the substrate 10 may be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, other transparent hard substrate, or other transparent flexible substrate, which may be a single-layer or multi-layer structure. Taking a multilayer structure as an example, the substrate 10 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer, which are sequentially stacked from bottom to top, where the two protective layers are used to protect the PI layer and prevent damage to the PI layer by a subsequent process. The second protective layer is also covered with a buffer layer which can block water and oxygen and block alkaline ions.

Illustratively, the light shielding layer 24 may be made of a metal material, including but not limited to molybdenum, aluminum, titanium, copper, and the like.

Illustratively, the active layer 21 is made of a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide ).

Illustratively, the gate layer 22 is made of a metallic material, such as one or more of molybdenum, copper, and aluminum.

Alternatively, the source-drain electrode layer 23 is a single metal layer, and is made of molybdenum or aluminum, for example; or, it is formed by laminating a plurality of metal layers, for example, a molybdenum layer, an aluminum layer and a molybdenum layer, or a titanium layer, an aluminum layer and a titanium layer, etc. which are laminated.

Illustratively, the materials of the buffer layer 25, the gate insulating layer 26, and the insulating layer 27 may be silicon oxide or silicon nitride, silicon oxynitride, or the like.

Illustratively, the planarization layer 28 is made of an organic insulating material, such as a resin or the like.

In other possible embodiments, the driving backplate may also include two stacked active layers, such as a first active layer and a second active layer sequentially stacked on the first surface 10a, where the first active layer is made of a low-temperature polysilicon material, and the second active layer is made of a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide ). The driving back plane including the first active layer and the second active layer is also called LTPO (Low-temperature Polycrystalline oxide, low temperature polysilicon oxide) driving back plane, and among the plurality of TFTs in the pixel driving circuit of the driving back plane, an active region of a part of the TFTs is located in the first active layer, and an active region of a part of the TFTs is located in the second active layer.

The second case is exemplarily described below, that is, the front projection of the first connection line 211 on the first surface 10a is located within the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a is located outside the front projection of the data line 232 on the first surface. I.e. the front projection of the second connecting line 212 on the first surface 10a does not coincide with the front projection of the data line 232 on the first surface. The design that the second connection line 212 and the data line 232 do not overlap can reduce the coupling capacitance as much as possible, and reduce the load, thereby reducing the power consumption of the display panel.

Fig. 5 is a schematic plan view of another driving back plate according to an embodiment of the present disclosure, fig. 6 is a schematic plan view of a plurality of film layers in the another driving back plate shown in fig. 5, part (a) of fig. 6 is a schematic plan view of a light shielding layer 24 in the embodiment shown in fig. 5, part (b) of fig. 6 is a schematic plan view of an active layer 21 in the embodiment shown in fig. 5, part (c) of fig. 6 is a schematic plan view of a gate layer 22 in the embodiment shown in fig. 5, and part (d) of fig. 6 is a schematic plan view of a source/drain layer 23 in the embodiment shown in fig. 5. In contrast to the embodiment shown in fig. 2 and 3, in the embodiment shown in fig. 5 and 6, the orthographic projection of the second connection line 212 on the first surface 10a is located between the orthographic projection of the first power line 231 on the first surface and the orthographic projection of the data line 232 on the first surface. In other possible embodiments, the front projection of the second connection line 212 on the first surface 10a is located on a side of the front projection of the data line 232 on the first surface, which is far from the front projection of the first power line 231 on the first surface. Since the second connection lines 212 are connected to the plurality of second protruding portions 216, so that the second connection lines 212 are electrically connected to other structures through the third via holes 33, the sixth via holes 36, and the like, the overlapping area of the first connection lines 212 and the data lines 232 can be reduced as much as possible in the embodiment shown in fig. 5 and 6, compared to the embodiment in which the front projection of the second connection lines 212 on the first surface 10a is located on the side of the front projection of the data lines 232 on the first surface, which is far away from the front projection of the first power lines 231, so that the coupling capacitance can be reduced as much as possible, the load can be reduced, and the power consumption of the display panel can be reduced.

The third case is exemplarily described below, that is, the front projection of the first connection line 211 on the first surface 10a is located outside the front projection of the first power line 231 on the first surface 10a, and the front projection of the second connection line 212 on the first surface 10a is located inside the front projection of the data line 232 on the first surface 10 a. The third case is similar to the second case and will not be described again here. In the third case, by disposing the front projection of the second connection line 232 on the first surface 10a entirely within the front projection of the data line 232 on the first surface 10a, the area of the front projection of the pixel driving circuit on the first surface can be reduced as much as possible, which is beneficial to further improving the resolution of the display panel.

Fig. 7 is a schematic plan view of another driving back plate according to an embodiment of the present disclosure, fig. 8 is a schematic plan view of a plurality of film layers in the another driving back plate shown in fig. 7, part (a) of fig. 8 is a schematic plan view of a light shielding layer 24 in the embodiment shown in fig. 7, part (b) of fig. 8 is a schematic plan view of an active layer 21 in the embodiment shown in fig. 7, part (c) of fig. 8 is a schematic plan view of a gate layer 22 in the embodiment shown in fig. 7, and part (d) of fig. 8 is a schematic plan view of a source/drain layer 23 in the embodiment shown in fig. 7. In contrast to the embodiment shown in fig. 2 and 3, in the embodiment shown in fig. 7 and 8, the front projection of the active region 213 of the driving transistor T5 on the first surface 10a includes a first portion 213a, a second portion 213b, and a third portion 213c connected in sequence, the first portion 213a and the third portion 213c extending in the second direction y, and the second portion 213b extending in the first direction x. The active region of the driving transistor T5 is configured to include the first portion 213a, the second portion 213b, and the third portion 213c extending in different directions, so that the area of the orthographic projection of the active region of the driving transistor T5 on the first surface 10a is increased as much as possible, thereby increasing the channel length, increasing the range (data range) of the data voltage, and facilitating full gray scale development.

In other embodiments, the driving transistor T5 in the embodiment shown in fig. 5 and 6 may be provided as the structure of the driving transistor in the embodiment shown in fig. 7 and 8.

Fig. 9 is a flowchart illustrating a method for manufacturing a driving back board according to an embodiment of the disclosure. As shown in fig. 9, the method includes:

in step S1, a substrate base plate is provided;

in step S2, a driving circuit layer is formed on the surface of the substrate;

the driving circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially laminated on the first surface of the substrate, the source drain layer comprises a plurality of signal wires, the plurality of signal wires extend along a first direction and are arranged along a second direction, the first direction and the second direction are intersected, the driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is located in the active layer, at least one pixel driving circuit, active areas of the at least two thin film transistors are connected through the first connecting wire, and orthographic projection of the first connecting wire on the first surface and orthographic projection of the signal wire on the first surface are at least partially overlapped.

Step S2 will be exemplarily described below taking the structure shown in fig. 2 as an example. Illustratively, this step S2 may include:

First, a light shielding metal layer is obtained on a substrate by a deposition method, and patterning treatment is performed on the light shielding metal layer to obtain the light shielding layer.

And secondly, forming a buffer layer on the shading layer in a deposition mode. Then, a semiconductor material layer is formed on the buffer layer by, for example, deposition, and patterning is performed on the semiconductor material layer to obtain an active layer. The active layer includes a first connection line and a second connection line.

Third, an initial gate insulating layer and an initial gate material layer are sequentially formed on the active layer by, for example, deposition. The initial gate insulating layer covers the active layer. And patterning the initial gate material layer to obtain a gate layer.

And fourthly, forming an initial insulating layer and an initial source drain electrode material layer on the gate electrode layer in sequence in a deposition mode, and performing patterning treatment on the initial source drain electrode material layer to obtain a source drain electrode layer. The source drain electrode layer comprises a first power line and a data line.

And fifthly, forming a planarization layer on the source electrode layer by a deposition mode.

The materials of each layer are referred to the foregoing embodiments, and will not be described herein.

Optionally, the patterning process includes photoresist coating, exposure, development, etching, stripping, and the like.

The embodiment of the disclosure also provides a display panel, which comprises a laminated light-emitting functional layer and any one of the driving back plates, wherein the driving back plate is used for driving the light-emitting functional layer to emit light.

Illustratively, the light emitting functional layer includes a plurality of light emitting cells distributed in an array, each of the light emitting cells being electrically connected to one of the pixel driving circuits. Each pixel driving circuit is used for controlling the connected light emitting units to emit light. Alternatively, the light emitting unit may be the aforementioned light emitting device, such as an OLED or QLED.

Illustratively, the light emitting unit includes a first electrode, a light emitting layer, and a second electrode sequentially stacked on the first surface 10 a. Optionally, the first electrode is an anode and the second electrode is a cathode. Optionally, the first electrode is electrically connected to the pixel driving circuit.

The embodiment of the disclosure also provides a display device, which comprises any one of the display panels and a power supply circuit, wherein the power supply circuit is used for supplying power to the display panels.

The display device provided by the embodiment of the disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

The display device has the same effects as the aforementioned display panel, and will not be described herein.

The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, any modification, equivalent replacement, improvement, etc. that comes within the spirit and principles of the present disclosure are included in the scope of the present disclosure.

Claims

1. The driving backboard is characterized by comprising a substrate base plate and a driving circuit layer, wherein the driving circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially stacked on the first surface of the substrate base plate, the source drain layer comprises a plurality of signal wires, the plurality of signal wires extend along a first direction and are arranged along a second direction, and the first direction and the second direction are intersected;

the driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is positioned in the active layer, at least one pixel driving circuit is characterized in that the active areas of at least two thin film transistors are connected through the first connecting wire, and the orthographic projection of the first connecting wire on the first surface is at least partially overlapped with the orthographic projection of the signal wire on the first surface.

2. The drive backplate of claim 1, wherein the plurality of signal wires comprises a first power wire, an orthographic projection of the first connection wire on the first surface being within an orthographic projection of the first power wire on the first surface; or,

the plurality of signal lines include data lines, and the orthographic projection of the first connecting line on the first surface is positioned in the orthographic projection of the data line on the first surface.

3. The drive backplate of claim 1, wherein the plurality of signal lines comprise a first power line and a data line;

the pixel driving circuit further comprises a second connecting line, wherein the second connecting line is connected with the active areas of at least two thin film transistors, and the at least two thin film transistors connected with the second connecting line are different from the at least two thin film transistors connected with the first connecting line;

the front projection of the first connecting line on the first surface is positioned in the front projection of the first power line on the first surface, and the front projection of the second connecting line on the first surface is positioned in the front projection of the data line on the first surface.

4. The drive backplate of claim 1, wherein the plurality of signal lines comprise a first power line and a data line;

the front projection of the first connecting line on the first surface is positioned in the front projection of the first power line on the first surface, and the front projection of the second connecting line on the first surface is positioned outside the front projection of the data line on the first surface.

5. The drive backplate of claim 4, wherein the orthographic projection of the second connection line on the first surface is between the orthographic projection of the data line on the first surface and the orthographic projection of the first power supply line on the first surface.

6. The driving back panel according to any one of claims 3 to 5, wherein the pixel driving circuit further includes a third connection line which is located in the active layer and is connected between the first connection line and the second connection line;

the at least two thin film transistors comprise driving transistors, and active areas of the driving transistors are located in the third connecting line.

7. The driving backplate of claim 6, wherein an orthographic projection of the active region of the driving transistor on the first surface is elongated and extends along the second direction.

8. The driving backplate of claim 6, wherein the front projection of the active region of the driving transistor on the first surface comprises a first portion, a second portion, and a third portion that are sequentially connected, the first portion and the third portion extending in the second direction, the second portion extending in the first direction.

9. The drive back plate according to claim 7 or 8, wherein the drive circuit layer further includes a light shielding layer between the substrate base plate and the active layer, the light shielding layer including a plurality of light shielding structures;

the orthographic projection of the active region of the driving transistor on the first surface is positioned in the orthographic projection of the shading structure on the first surface;

the source electrode of the driving transistor is electrically connected with the shading structure.

10. The driving back panel according to claim 9, wherein the pixel driving circuit includes a storage capacitor, a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor, the fifth thin film transistor being the driving transistor;

The active region of the first thin film transistor, the active region of the third thin film transistor and the active region of the fourth thin film transistor are located in the first connection line;

the active region of the second thin film transistor, the active region of the sixth thin film transistor and the active region of the seventh thin film transistor are located in the second connecting line;

the driving backboard further comprises a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line and an initial signal line, wherein the control electrode of the first thin film transistor is connected with the third scanning signal line, the control electrode of the second thin film transistor is connected with the first scanning signal line, the control electrode of the third thin film transistor is connected with the second scanning signal line, the control electrode of the fourth thin film transistor is connected with the light-emitting signal line, the control electrode of the sixth thin film transistor is connected with the light-emitting signal line, and the control electrode of the seventh thin film transistor is connected with the second scanning signal line;

the first electrode of the first thin film transistor is electrically connected to the first power line, the second electrode of the first thin film transistor, the first electrode of the third thin film transistor, the control electrode of the fifth thin film transistor and the first end of the storage capacitor are electrically connected, the second electrode of the third thin film transistor, the fourth thin film transistor and the second electrode of the first electrode of the fifth thin film transistor are electrically connected, the second end of the storage capacitor, the first electrode of the second thin film transistor and the second electrode of the sixth thin film transistor are electrically connected, the second electrode of the fifth thin film transistor, the first electrode of the sixth thin film transistor and the first electrode of the seventh thin film transistor are electrically connected, the second electrode of the second thin film transistor is electrically connected to the initial signal line, the first electrode of the fourth thin film transistor is electrically connected to the first power line, and the second electrode of the seventh thin film transistor is electrically connected to the data line.

11. The driving back plate of claim 10, wherein the storage capacitor comprises a first electrode plate located on the light shielding layer, a second electrode plate located on the gate layer, and a third electrode plate located on the source-drain layer, the orthographic projection of the first electrode plate on the first surface is at least partially overlapped with the orthographic projection of the second electrode plate on the first surface, the orthographic projection of the third electrode plate on the first surface is at least partially overlapped with the orthographic projection of the second electrode plate on the first surface, and the first electrode plate is electrically connected with the third electrode plate.

12. The driving back plate according to claim 10 or 11, further comprising a transfer via, the transfer via comprising a first portion and a second portion, the first portion and the second portion being connected in a direction parallel to the first surface, the first portion being for connecting a first transfer structure and a second transfer structure, the second portion being for connecting the first transfer structure and a third transfer structure, wherein the first transfer structure is located at the source-drain layer, the second transfer structure is located at the active layer or the gate layer, and the third transfer structure is located at the light shielding layer;

The first switching structure is the first power line, the second switching structure is the first pole of the first thin film transistor, and the third switching structure is a wiring positioned on the shading layer; or,

the first transfer structure is a transfer part positioned on the source drain electrode layer, the second transfer structure is a second pole of the second thin film transistor, and the third transfer structure is the initial signal line.

13. A method of manufacturing a drive backplate, the method comprising:

providing a substrate;

manufacturing a driving circuit layer on the surface of the substrate;

the driving circuit layer comprises an active layer, a grid layer and a source drain layer which are sequentially laminated on the first surface of the substrate, the source drain layer comprises a plurality of signal wires, the plurality of signal wires extend along a first direction and are arranged along a second direction, the first direction and the second direction are intersected, the driving circuit layer comprises a plurality of pixel driving circuits, each pixel driving circuit comprises at least two thin film transistors and a first connecting wire, the first connecting wire is located in the active layer, at least one pixel driving circuit is arranged, active areas of at least two thin film transistors are connected through the first connecting wire, and orthographic projection of the first connecting wire on the first surface and orthographic projection of the signal wire on the first surface are at least partially overlapped.

14. A display panel comprising a stacked light-emitting functional layer and the driving back sheet according to any one of claims 1 to 12 for driving the light-emitting functional layer to emit light.

15. A display device comprising a power supply circuit and the display panel of claim 14, the power supply circuit supplying power to the display panel.