CN117855198A - Packaging structure and preparation method thereof - Google Patents
Packaging structure and preparation method thereof Download PDFInfo
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- CN117855198A CN117855198A CN202311589404.4A CN202311589404A CN117855198A CN 117855198 A CN117855198 A CN 117855198A CN 202311589404 A CN202311589404 A CN 202311589404A CN 117855198 A CN117855198 A CN 117855198A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 238000000465 moulding Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000010354 integration Effects 0.000 abstract description 5
- 238000012858 packaging process Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 25
- 230000004888 barrier function Effects 0.000 description 13
- 239000010949 copper Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Abstract
The application relates to a packaging structure and a preparation method thereof, comprising the following steps: a first wiring structure layer including a capacitor and a first inductor bar; the inductance conducting column is positioned on the first inductance strip; the insulating layer covers the first wiring structure layer and the inductance conducting columns and exposes the top ends of the inductance conducting columns; the second wiring structure layer covers the insulating layer and the top end of the inductance conducting column and comprises a second inductance strip, the second inductance strip is positioned at the top end of the inductance conducting column, and the second inductance strip, the inductance conducting column and the first inductance strip form an inductance; a chip mounted on the second wiring structure layer; and the first plastic layer covers the chip. The capacitor and the first inductance strip are formed while the first wiring structure layer is formed, the capacitor, the first inductance strip and the inductance conducting column are located in the previous process, the inductance conducting column is formed in the subsequent packaging process, the first wiring structure layer formed with the capacitor and the insulating layer formed with the inductance are used as substrates together, secondary integration is conducted, and process steps are effectively shortened.
Description
Technical Field
The present disclosure relates to semiconductor packaging technology, and in particular, to a packaging structure and a method for manufacturing the same.
Background
With the development of semiconductor technology, passive devices (such as capacitors) are formed in a conventional package structure, and the passive devices are assembled in the package structure through processes such as grinding, cutting, taping, and pasting.
However, due to the small size of the passive device, the conventional packaging structure has a problem that the packaging process of the passive device is too much and the packaging cost is too high.
Disclosure of Invention
Based on this, it is necessary to provide a packaging structure and a method for manufacturing the same for solving the problems of excessive passive device packaging processes and excessive packaging cost in the conventional technology.
To achieve the above object, in one aspect, the present application provides a package structure, including:
a first wiring structure layer including a capacitor and a first inductor bar;
the inductance conducting column is positioned on the first inductance strip;
an insulating layer covering the first wiring structure layer and the inductance conductive column, and exposing the top end of the inductance conductive column;
the second wiring structure layer covers the insulating layer and the top end of the inductance conducting column and comprises a second inductance strip, the second inductance strip is positioned at the top end of the inductance conducting column, and the second inductance strip, the inductance conducting column and the first inductance strip form an inductance;
a chip mounted on the second wiring structure layer;
and the first plastic layer covers the chip.
In one embodiment, the first wiring structure layer includes an upper wiring layer and a lower wiring layer below the upper sub-wiring layer, the upper wiring layer including the first inductor bar, the lower wiring layer including the capacitor; the lower wiring layer further comprises a sub-wiring layer, the lower electrode plate of the capacitor is positioned in the sub-wiring layer, and the upper electrode plate of the capacitor is positioned above the sub-wiring layer.
In one embodiment, the capacitor further comprises a capacitor dielectric layer, the capacitor dielectric layer is located between the capacitor upper plate and the capacitor lower plate, and the capacitor dielectric layer is located above the sub-wiring layer.
In one embodiment, the package structure further includes:
and the solder ball is positioned on one side of the first wiring structure layer, which is far away from the inductance conductive column.
In one embodiment, the insulating layer includes a second plastic layer.
The application also provides a preparation method of the packaging structure, which comprises the following steps:
providing a substrate;
forming a first wiring structure layer on the substrate, and forming a capacitor and a first inductance strip in the process of forming the first wiring structure layer;
forming an inductance conductive column on the first inductance strip;
forming an insulating layer covering the first wiring structure layer and the inductance conductive column and exposing the top end of the inductance conductive column;
forming a second wiring structure layer covering the insulating layer and the top end of the inductance conducting column, and forming a second inductance strip in the process of forming the second wiring structure layer, wherein the second inductance strip is positioned at the top end of the inductance conducting column, and the second inductance strip, the inductance conducting column and the first inductance strip form an inductance;
mounting a chip on the second wiring structure layer;
a first plastic layer is formed overlying the chip.
According to the preparation method of the packaging structure, the first wiring structure layer is formed and the capacitor is formed at the same time, and the first wiring structure layer and the capacitor are both positioned in the previous process, so that the process steps are effectively shortened, the wafer-level process is used for integration, and the process cost is remarkably reduced. Simultaneously, the first inductance strip and the first wiring structure layer of the three-dimensional inductor are formed together, and the inductance conducting column is formed in the subsequent packaging process, so that the first wiring structure layer formed with the capacitor and the insulating layer formed with the inductor are used as substrates together for secondary integration, and the process steps are effectively shortened.
In addition, the packaging structure of the embodiment avoids the independent packaging of the capacitor and the inductor, thereby reducing the packaging cost.
In one embodiment, the forming a first wiring structure layer on the substrate and forming a capacitor in the process of forming the first wiring structure layer includes:
forming a lower wiring layer, wherein the lower wiring layer comprises a sub-wiring layer, a capacitor lower polar plate is formed in the sub-wiring layer, and a capacitor upper polar plate is formed above the sub-wiring layer; forming an upper wiring layer on the lower wiring layer, wherein the first inductance strip is formed on the upper wiring layer; the upper wiring layer and the lower wiring layer constitute the first wiring structure layer.
In one embodiment, the forming a first wiring structure layer on the substrate, and forming a capacitor and a first inductor bar in the process of forming the first wiring structure layer, further includes:
and forming a capacitance dielectric layer between the capacitance upper polar plate and the capacitance lower polar plate, wherein the capacitance dielectric layer is positioned above the sub-wiring layer.
In one embodiment, after the forming of the first plastic layer covering the chip, the method includes:
removing the substrate;
and forming a solder ball on one side of the first wiring structure layer far away from the inductance conductive column.
In one of the embodiments of the present invention,
the forming an insulating layer covering the first wiring structure layer and the inductor conductive pillar and exposing a top end of the inductor conductive pillar includes:
and forming a second plastic layer which covers the first wiring structure layer and the inductance conductive column and exposes the top end of the inductance conductive column.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for manufacturing a package structure according to an embodiment;
fig. 2 to 5 are schematic cross-sectional structures of structures obtained in the method for manufacturing a package structure according to an embodiment.
Reference numerals illustrate: 100-substrate, 200-first wiring structure layer, 201-upper wiring layer, 202-lower wiring layer, 220-sub-wiring layer, 300-capacitor, 310-capacitor lower plate, 320-capacitor dielectric layer, 330-capacitor upper plate, 410-first molding layer, 420-second molding layer, 500-second wiring structure layer, 600-chip, 710-first inductance strip, 720-inductance conductive column, 730-second inductance strip, 800-solder ball.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
In one embodiment, referring to fig. 1, a method for manufacturing a package structure is provided, including:
step S100, providing a substrate 100;
step S200, forming a first wiring structure layer 200 on the substrate 100, and forming a capacitor 300 and a first inductor strip 710 during the process of forming the first wiring structure layer 200;
step S300, forming an inductance conductive pillar 720 on the first inductance strip 710;
step S400, forming an insulating layer covering the first wiring structure layer and the inductance conductive column 720 and exposing the top end of the inductance conductive column 720;
step S500, forming a second wiring structure layer covering the insulating layer to form the top end of the inductance conductive column 720, and forming a second inductance strip 730 in the process of forming the second wiring structure layer, wherein the second inductance strip 730 is positioned at the top end of the inductance conductive column 720, and the second inductance strip 730, the inductance conductive column 720 and the first inductance strip 710 form an inductance;
step S600, attaching a chip 600 on the second wiring structure layer 500;
in step S700, a first molding layer 410 is formed to cover the chip 600.
In step S100, the substrate 100 may be, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V or II/VI semiconductor substrate. Alternatively, the substrate may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 100 should not limit the scope of the present disclosure.
In step S200, referring to fig. 2, a first wiring structure layer 200 is formed on the substrate 100, and simultaneously, a capacitor 300 and a first inductor strip 710 are formed during the formation of the first wiring structure layer 200.
As an example, the first wiring structure layer 200 includes an upper wiring layer 201 and a lower wiring layer 202, the upper wiring layer 201 being located above the lower wiring layer 202, and the upper wiring layer 201 and the lower wiring layer 202 may each include a multi-layer wiring and a multi-layer dielectric layer.
A dielectric layer may be first formed on the substrate 100, then the dielectric layer is etched to form a via hole, the via hole exposes the surface of the substrate 100, and finally a metal material is filled in the via hole to form a wiring. Alternatively, a wiring material layer may be formed on the substrate 100 first, wiring may be formed by etching the wiring material layer, and then a dielectric layer may be deposited on the wiring, thereby forming a wiring layer. The above description is given taking the lowest wiring layer as an example.
In addition, a resistor may be formed during the formation of the first wiring structure layer 200.
In step S300, referring to fig. 3, as an example, the inductor conductive pillar 720 is formed on the first inductor strip 710, and at this time, the first inductor strip 710 may be located in the uppermost wiring layer of the upper wiring layer 201, and the first inductor strip 710 is directly connected to the inductor conductive pillar 720. Alternatively, the first inductor 710 may be located in another wiring layer of the upper wiring layer 201, and when the first inductor 710 is connected to the inductor conductive pillar 720, another wiring layer located on the wiring layer where the first inductor 710 is located may be etched.
The number of the inductance conductive posts 720 is not limited herein, and may be specifically set according to actual needs.
In step S400, referring to fig. 3, as an example, the insulating layer includes a second molding layer 420. A second molding layer 420 is formed on the first wiring structure layer 200. Specifically, the second molding material layer may be filled on the first wiring structure layer 200 and then heated to be cured and hardened, thereby forming the second molding layer 420.
Alternatively, in other examples, the insulating layer further comprises a dielectric layer. A dielectric layer may be first formed by deposition, the dielectric layer covering the first wiring structure layer 200 and the inductance conductive posts 720. The dielectric layer surface is then planarized and the top ends of the inductive conductive posts 720 are exposed.
In step S500, referring to fig. 4, a second wiring structure layer 500 is formed on the insulating layer.
As an example, the second wiring structure layer 500 may include a plurality of wiring layers, each including a wiring and a dielectric layer. A dielectric layer may be first formed on the substrate 100, then the dielectric layer is etched to form a via hole, the via hole exposes the surface of the second molding layer 420, and finally a metal material is filled in the via hole to form a wiring. Alternatively, the wiring layer may be formed by first forming a wiring material layer on the second molding layer 420, etching the wiring material layer to form a wiring, and then depositing a dielectric layer on the wiring. The above description is given taking the lowest wiring layer as an example.
The second inductor bar 730 may be located in the lowermost wiring layer of the second wiring structure layer 500, and also located at the top end of the inductor conductive pillar 720, where the second inductor bar 730, the inductor conductive pillar 720 and the first inductor bar 710 together form a three-dimensional inductor.
In addition, a planar inductance may be formed in the upper wiring layer 201 of the first wiring structure layer 200.
In step S600, the chip 600 is mounted on the second wiring structure layer 500, and in particular, the chip 600 may be quickly and accurately mounted on a predetermined position of the second wiring structure layer 500 using a high-speed surface mount technology (Surface Mounted Technology, SMT). The preset position can be selected according to actual needs. Chip 600 includes a variety of chips such as switches, low noise amplifiers, surface acoustic wave filters, power amplifiers, and the like.
In step S700, referring to fig. 4, a first molding layer 410 is formed to cover the chip 600. Specifically, a first molding material layer covering the chip 600 may be filled on the first wiring structure layer 200 and then heated to be cured and hardened, thereby forming the first molding layer 410.
In this embodiment, the capacitor 300 is formed while the first wiring structure layer 200 is formed, both of which are located in the previous process, so that the process steps are effectively shortened, and the integration is performed by the wafer-level process, thereby significantly reducing the process cost. Meanwhile, the first inductor strip 710 of the three-dimensional inductor is formed together with the first wiring structure layer 200, and the inductance conductive column 720 is formed in the subsequent packaging process, so that the first wiring structure layer 200 formed with the capacitor 300 and the insulating layer formed with the inductor are used as substrates together for secondary integration, and the process steps are effectively shortened.
In addition, the packaging structure of the present embodiment avoids the separate packaging of the capacitor 300 and the inductor, thereby reducing packaging costs.
In one embodiment, referring to fig. 2, step S200 includes:
step S210, forming a lower wiring layer 202, wherein the lower wiring layer 202 includes a sub-wiring layer 220, a capacitor lower plate 310 is formed in the sub-wiring layer 220, and a capacitor upper plate 330 is formed above the sub-wiring layer 220;
in step S220, the upper wiring layer 201 is formed on the lower wiring layer 202, and the first inductor strip 710 is formed on the upper wiring layer 202.
The upper wiring layer 201 and the lower wiring layer 202 constitute the first wiring structure layer 200.
In step S210, the lower wiring layer 202 is formed, and the lower wiring layer 202 includes the sub-wiring layer 220, and the number of wiring layers included in the lower wiring layer 202 is not limited here.
In step S220, the upper wiring layer 201 is formed on the lower wiring layer 202, and the first inductance strip 710 is formed on the upper wiring layer 201. The number of wiring layers included in the upper wiring layer 202 is not limited herein. As an example, a capacitor dielectric layer 320 is formed between the capacitor bottom plate 310 and the capacitor top plate 330, which together form the capacitor 300. In addition, a barrier layer may be formed between the capacitor bottom plate 310 and the capacitor dielectric layer 320 and between the capacitor dielectric layer 320 and the capacitor top plate 330, where the barrier layer isolates the capacitor 300 plate from the capacitor dielectric layer 320, so as to improve the performance of the capacitor device, and the material of the barrier layer includes but is not limited to titanium nitride.
As an example, the barrier layer between the capacitor lower plate 310 and the capacitor dielectric layer 320 is referred to as a first barrier layer, and the barrier layer between the capacitor dielectric layer 320 and the capacitor upper plate 330 is referred to as a second barrier layer. When forming the capacitor 300, a sub-wiring material layer, a first barrier material layer, a dielectric material layer, a second barrier material layer, and an upper plate material layer may be sequentially deposited, and then the upper plate material layer, the second barrier material layer, the dielectric material layer, the first barrier material layer, and the sub-wiring material layer are sequentially etched to form a capacitor upper plate 330, a second barrier layer, a capacitor dielectric layer 320, a first barrier layer, and a capacitor lower plate 310, which together form the capacitor 300. Wherein the dielectric material layer is etched to form a capacitor dielectric layer 320, and the sub-wiring material layer is etched to form a capacitor bottom plate 310 and a sub-wiring layer 220.
The material of the capacitor upper plate 330 may be the same as the material of the capacitor lower plate 310, for example, both may be metallic aluminum (Al) or metallic copper (Cu). The material of the upper capacitor plate 330 may be different from the material of the lower capacitor plate 310, and in particular, when the lower capacitor plate 310 is made of metal copper (Cu), the upper capacitor plate 330 may be made of metal aluminum (Al), and the metal copper (Cu) is easier to generate electromigration than the metal aluminum (Al), so that the performance of the capacitor 300 device may be improved.
In one embodiment, referring to fig. 5, after step S700, the method includes:
step S800, removing the substrate 100;
in step S900, solder balls 800 are formed on the side of the first wiring structure layer 200 away from the conductive pillars 720.
In step S800, the supporting substrate 100 is removed, exposing the wiring layer of the lowermost layer of the first wiring structure layer 200, which is understood to be a pad.
In step S900, a solder ball 800 is formed on a side of the first wiring structure layer 200 away from the inductance conductive pillar 720, specifically, a solder ball 800 is formed under the wiring layer of the lowest layer, and the solder ball 800 is electrically connected with the pad. At the same time, the solder balls 800 cover the pads, thereby preventing oxidation of the pads. Solder balls 800 may be fabricated from a tin material.
In this embodiment, the substrate 100 is removed and the solder balls 800 are formed, and the solder balls 800 may connect the package structure with an external device.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, please continue to refer to fig. 5, a package structure is further provided, which includes: the first wiring structure layer 200, the capacitor 300, the first inductor strip 710, the inductor conductive pillar 720, the insulating layer, the second wiring structure layer 500, the chip 600, and the first molding layer 410.
The first wiring structure layer 200 includes a capacitor 300 and a first inductor strip 710.
As an example, the first wiring structure layer 200 includes an upper wiring layer 201 and a lower wiring layer 202, and the upper wiring layer 201 and the lower wiring layer 202 may each include a multi-layer wiring and a multi-layer dielectric layer; the upper wiring layer 201 is located above the lower wiring layer 202; the upper wiring layer 201 may include a first inductance strip 710; the lower wiring layer 202 further includes a sub-wiring layer 220; a capacitor lower plate 310 is located within the sub-wiring layer 220 and a capacitor upper plate 320 is located above the sub-wiring layer 220.
Meanwhile, the capacitor 300 further includes a capacitor dielectric layer 320, the capacitor dielectric layer 320 is located between the capacitor upper plate 330 and the capacitor lower plate 310, and the capacitor dielectric layer 320 is located above the sub-wiring layer 220.
The material of the capacitor upper plate 330 may be the same as the material of the capacitor lower plate 310, for example, both may be metallic aluminum (Al) or metallic copper (Cu); the material of the upper capacitor plate 330 may be different from the material of the lower capacitor plate 310, and in particular, when the lower capacitor plate 310 is made of metal copper (Cu), the upper capacitor plate 330 may be made of metal aluminum (Al), and the metal copper (Cu) is easier to generate electromigration than the metal aluminum (Al), so that the performance of the capacitor 300 device may be improved.
The upper wiring layer 201 includes the sub-wiring layer 220, and the number of wiring layers included in the sub-wiring layer 220 is not limited herein.
The inductance conductive pillar 720 is located on the first inductance strip 710 and electrically connected to the first inductance strip 710. The number of the inductance conductive posts 720 is not limited herein, and may be specifically set according to actual needs.
The insulating layer covers the first wiring structure layer and the inductance conductive pillars 720 and exposes the top ends of the inductance conductive pillars 720. As an example, the insulating layer includes a second plastic layer 420.
The second wiring structure layer 500 covers the insulating layer and the top ends of the inductance conductive pillars 720, and includes a second inductance bar 730, the second inductance bar 730 is located at the top end of the inductance conductive pillar 720, and the second inductance bar 730, the inductance conductive pillar 720 and the first inductance bar 710 form an inductance.
As an example, the second wiring structure layer 500 may include a plurality of wiring layers each including a wiring and a dielectric layer, and the wiring of the lowermost wiring layer of the second wiring structure layer 500 may form the second inductor bar 730.
The chip 600 is mounted on the second wiring structure layer 500. The chip 600 includes a variety of chips 600 such as switches, low noise amplifiers, surface acoustic wave filters, power amplifiers, and the like.
The first plastic layer 410 covers the chip 600, which may protect the chip 600. In one embodiment, the first wiring structure layer 200 includes: a first sub-wiring layer, a second sub-wiring layer 220, and a third sub-wiring layer 230.
In one embodiment, the package structure further includes solder balls 800.
The solder balls 800 may be located on a side of the first wiring structure layer 200 remote from the inductive conductive pillars 720. Specifically, the solder ball 800 may be located under the lowermost wiring layer of the first wiring structure layer 200, and the solder ball 800 is electrically connected to the pad. At the same time, the solder balls 800 cover the pads, thereby preventing oxidation of the pads. Solder balls 800 may be fabricated from a tin material.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "ideal embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the foregoing embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A package structure, comprising:
a first wiring structure layer including a capacitor and a first inductor bar;
the inductance conducting column is positioned on the first inductance strip;
an insulating layer covering the first wiring structure layer and the inductance conductive column, and exposing the top end of the inductance conductive column;
the second wiring structure layer covers the insulating layer and the top end of the inductance conducting column and comprises a second inductance strip, the second inductance strip is positioned at the top end of the inductance conducting column, and the second inductance strip, the inductance conducting column and the first inductance strip form an inductance;
a chip mounted on the second wiring structure layer;
and the first plastic layer covers the chip.
2. The package structure of claim 1, wherein the first wiring structure layer comprises an upper wiring layer and a lower wiring layer located below the upper sub-wiring layer, the upper wiring layer comprising the first inductor bar, the lower wiring layer comprising the capacitor; the lower wiring layer further comprises a sub-wiring layer, the lower electrode plate of the capacitor is positioned in the sub-wiring layer, and the upper electrode plate of the capacitor is positioned above the sub-wiring layer.
3. The package structure of claim 2, wherein the capacitor further comprises a capacitor dielectric layer between the capacitor upper plate and the capacitor lower plate, the capacitor dielectric layer being over the sub-wiring layer.
4. The package structure of claim 1, further comprising:
and the solder ball is positioned on one side of the first wiring structure layer, which is far away from the inductance conductive column.
5. The package structure of claim 1, wherein the insulating layer comprises a second plastic layer.
6. The preparation method of the packaging structure is characterized by comprising the following steps:
providing a substrate;
forming a first wiring structure layer on the substrate, and forming a capacitor and a first inductance strip in the process of forming the first wiring structure layer;
forming an inductance conductive column on the first inductance strip;
forming an insulating layer covering the first wiring structure layer and the inductance conductive column and exposing the top end of the inductance conductive column;
forming a second wiring structure layer covering the insulating layer and the top end of the inductance conducting column, and forming a second inductance strip in the process of forming the second wiring structure layer, wherein the second inductance strip is positioned at the top end of the inductance conducting column, and the second inductance strip, the inductance conducting column and the first inductance strip form an inductance;
mounting a chip on the second wiring structure layer;
a first plastic layer is formed overlying the chip.
7. The method of manufacturing a package structure according to claim 6, wherein forming a first wiring structure layer on the substrate, and forming a capacitor and a first inductor bar during forming the first wiring structure layer, comprises:
forming a lower wiring layer, wherein the lower wiring layer comprises a sub-wiring layer, a capacitor lower polar plate is formed in the sub-wiring layer, and a capacitor upper polar plate is formed above the sub-wiring layer;
forming an upper wiring layer on the lower wiring layer, wherein the first inductance strip is formed on the upper wiring layer;
the upper wiring layer and the lower wiring layer constitute the first wiring structure layer.
8. The method of manufacturing a package structure according to claim 7, wherein forming a first wiring structure layer on the substrate, and forming a capacitor and a first inductor bar during forming the first wiring structure layer, further comprises:
and forming a capacitance dielectric layer between the capacitance upper polar plate and the capacitance lower polar plate, wherein the capacitance dielectric layer is positioned above the sub-wiring layer.
9. The method of manufacturing a package structure according to claim 6, wherein after forming the first molding layer covering the chip, the method comprises:
removing the substrate;
and forming a solder ball on one side of the first wiring structure layer far away from the inductance conductive column.
10. The method of manufacturing a package structure according to claim 6, wherein,
the forming an insulating layer covering the first wiring structure layer and the inductor conductive pillar and exposing a top end of the inductor conductive pillar includes:
and forming a second plastic layer which covers the first wiring structure layer and the inductance conductive column and exposes the top end of the inductance conductive column.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311589404.4A CN117855198A (en) | 2023-11-27 | 2023-11-27 | Packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311589404.4A CN117855198A (en) | 2023-11-27 | 2023-11-27 | Packaging structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117855198A true CN117855198A (en) | 2024-04-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311589404.4A Pending CN117855198A (en) | 2023-11-27 | 2023-11-27 | Packaging structure and preparation method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN117855198A (en) |
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2023
- 2023-11-27 CN CN202311589404.4A patent/CN117855198A/en active Pending
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