CN117855186A - Metal interconnection structure and semiconductor device - Google Patents
Metal interconnection structure and semiconductor device Download PDFInfo
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- CN117855186A CN117855186A CN202410121446.3A CN202410121446A CN117855186A CN 117855186 A CN117855186 A CN 117855186A CN 202410121446 A CN202410121446 A CN 202410121446A CN 117855186 A CN117855186 A CN 117855186A
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- contact hole
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- stop layer
- interconnect structure
- diffusion barrier
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 67
- 239000002184 metal Substances 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 256
- 238000005530 etching Methods 0.000 claims abstract description 78
- 230000004888 barrier function Effects 0.000 claims abstract description 65
- 238000009792 diffusion process Methods 0.000 claims abstract description 58
- 239000011241 protective layer Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000000149 penetrating effect Effects 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 33
- 238000002955 isolation Methods 0.000 claims description 22
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- -1 tungsten nitride Chemical class 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- 230000007704 transition Effects 0.000 abstract description 14
- 238000000034 method Methods 0.000 description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 239000011148 porous material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229940104869 fluorosilicate Drugs 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a metal interconnection structure and a semiconductor device, wherein the metal interconnection structure comprises a substrate, an etching stop layer and a protective layer which are sequentially laminated; a contact hole penetrating the protective layer and the etch stop layer; wherein the contact hole comprises a first part penetrating the protective layer and extending into the etching stop layer, and a second part arranged in the etching stop layer and connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole; and a diffusion barrier layer covering the side wall and the bottom of the contact hole. The junction of the first part and the second part of the contact hole is positioned at the etching stop layer, the transition is gentle, a sharp angle cannot be formed, the coverage of the diffusion barrier layer is good, and the short circuit problem between interconnection structures is greatly reduced.
Description
The present application is a divisional application of chinese patent application (application number: 2021108194927, title of invention: metal interconnect structure, method of manufacturing the same, semiconductor device) filed at 7/20 of 2021.
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a metal interconnection structure and a semiconductor device.
Background
In the Back End of line (BEOL) process of the semiconductor device, a plurality of metal interconnect layers and contact plugs connecting the metal interconnect layers of different layers are required to be formed on the semiconductor device layer to lead out the electrodes of the semiconductor device. With the continuous shrinking of chip feature sizes, the subsequent interconnect technology is becoming more important; via tungsten plug deposition is one of the key interconnect technologies. At 0.25 microns or above, the order of fabrication of the via tungsten plugs is typically as follows: a contact hole is first formed in the dielectric layer, a barrier metal (e.g., tiN) is deposited in the contact hole, then tungsten is deposited, and finally, the excess W and TiN are removed by etching back or chemical mechanical polishing (Chemical Mechanical Polishing, CMP), leaving only the W and TiN in the via hole. The barrier metal acts primarily to prevent etching of the dielectric contacting the sidewall of the via by the source gas (e.g., WF 6) during tungsten deposition.
Because of the forming process of the contact hole, the contact hole has the characteristics of large aperture of the upper part and small aperture of the lower part, if the turning part of the upper part and the lower part of the contact hole is positioned at the junction of two dielectric film layers or at the position of a thinner dielectric layer, the difference of dielectric layer materials leads to sharper shoulders formed at the turning part, and the coverage rate of barrier layer metal at the turning part is lower, so when metal tungsten is deposited, due to serious etching effect of source gases such as WF6 and the like on the dielectric layer, the shoulders formed at the turning part are etched by source gases such as WF6 and the like, the contact hole resistance is higher, and short circuit or other side effects among interconnection parts can be caused when serious.
Disclosure of Invention
Aiming at the problems, the application provides a metal interconnection structure and a semiconductor device, which solve the technical problem of poor coverage rate of a barrier layer at a contact hole turning part of the interconnection structure in the prior art.
In a first aspect, the present application provides a metal interconnect structure comprising:
sequentially laminating a substrate, an etching stop layer and a protective layer;
a contact hole penetrating the protective layer and the etch stop layer; wherein the contact hole comprises a first part penetrating the protective layer and extending into the etching stop layer, and a second part arranged in the etching stop layer and connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole;
a diffusion barrier layer covering the side wall and the bottom of the contact hole;
and the conductive layer is filled in the contact hole.
According to an embodiment of the present application, optionally, in the metal interconnection structure, the etching stop layer includes a plurality of stop layers sequentially stacked in a direction away from the substrate.
According to an embodiment of the present application, optionally, in the metal interconnection structure, a shoulder is formed at a connection between the first portion of the contact hole and the second portion of the contact hole;
wherein the shoulder is located within the second or third layer of the etch stop layer.
According to an embodiment of the present application, optionally, in the metal interconnection structure, a distance between the shoulder and a surface of the etching stop layer away from the substrate is greater than a preset distance.
According to an embodiment of the present application, optionally, in the foregoing metal interconnection structure, a thickness of the diffusion barrier layer at a connection between the first portion and the second portion of the contact hole is smaller than a thickness of the diffusion barrier layer at a sidewall of the first portion of the contact hole and a sidewall of the second portion of the contact hole.
According to an embodiment of the present application, optionally, in the metal interconnection structure, a thickness of the diffusion barrier layer at a bottom of the contact hole is greater than a thickness of the diffusion barrier layer at a sidewall of the contact hole.
According to an embodiment of the present application, optionally, in the metal interconnection structure, the method further includes: an isolation layer between the etch stop layer and the protection layer;
the thickness of the etching stop layer and the thickness of the protection layer are larger than those of the isolation layer, and the first part of the contact hole penetrates through the isolation layer.
According to an embodiment of the present application, optionally, in the metal interconnection structure, the density of the etching stop layer is higher than that of the isolation layer and the protection layer.
Optionally, in the foregoing metal interconnection structure, a material of the etching stop layer includes carbon doped silicon nitride.
In an embodiment of the present application, optionally, in the metal interconnection structure, a material of the protection layer includes a low-k material.
In a second aspect, the present application provides a method for preparing a metal interconnect structure, including:
providing a substrate;
sequentially forming an etching stop layer and a protective layer above the substrate;
forming a contact hole penetrating through the protective layer and the etching stop layer; wherein the contact hole comprises a first part penetrating the protective layer and extending into the etching stop layer, and a second part arranged in the etching stop layer and connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole;
forming a diffusion barrier layer covering the side wall and the bottom of the contact hole;
and forming a conductive layer filled in the contact hole.
In a third aspect, the present application provides a semiconductor device comprising at least one metal interconnect structure as claimed in any one of the first aspects or prepared using a preparation method as claimed in the second aspect.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
the application provides a metal interconnection structure and a semiconductor device, wherein the metal interconnection structure comprises a substrate, an etching stop layer and a protective layer which are sequentially laminated; a contact hole penetrating the protective layer and the etch stop layer; wherein the contact hole comprises a first part penetrating the protective layer and extending into the etching stop layer, and a second part arranged in the etching stop layer and connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole; a diffusion barrier layer covering the side wall and the bottom of the contact hole; and the conductive layer is filled in the contact hole. Because the contact hole comprises the first part penetrating through the protective layer and extending into the etching stop layer, and the second part arranged in the etching stop layer and connected with the first part of the contact hole, namely the connection part of the first part and the second part of the contact hole is positioned at the etching stop layer, transition is gentle, a sharp angle cannot be formed, the coverage of the diffusion barrier layer is good, and the short circuit problem between interconnection structures is greatly reduced.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and, together with the description, do not limit the application. In the drawings:
FIG. 1 is a schematic cross-sectional view of a metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of another metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of another metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of another metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 5 is a schematic flow diagram of a method for fabricating a metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a first intermediate structure formed by related steps of a method for fabricating a metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a second intermediate structure formed by related steps of a method for fabricating a metal interconnect structure according to an exemplary embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a third intermediate structure formed by related steps of a method for fabricating a metal interconnect structure according to an exemplary embodiment of the present application;
in the drawings, wherein like parts are designated by like reference numerals throughout, the drawings are not to scale;
wherein, the reference numerals are as follows:
101-a substrate; 102-etching a stop layer; 103-a protective layer; 104-contact holes; 1041-a first portion of the contact hole; 1042-a first portion of the contact hole; 105-a diffusion barrier; 106 a conductive layer; 201-a substrate; 202-an etch stop layer; 203-isolating layer; 204-a protective layer; 205-contact holes; 2051-a first portion of a contact hole; 2052-a second portion of a contact hole; 206-a diffusion barrier; 207-conductive layer.
Detailed Description
The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby how to apply technical means to the present application to solve technical problems, and realizing processes achieving corresponding technical effects can be fully understood and implemented accordingly. The embodiments and the features in the embodiments can be combined with each other under the condition of no conflict, and the formed technical schemes are all within the protection scope of the application. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatially relative terms, such as "above," "located above," "below," "located below," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as connected with another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but include deviations in shapes that result, for example, from manufacturing.
For a thorough understanding of the present application, detailed structures and steps are set forth in the following description in order to illustrate the technical solutions set forth herein. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.
Example 1
As shown in fig. 1, an embodiment of the present application provides a metal interconnection structure, including: a substrate 101, an etch stop layer 102, a protective layer 103, a contact hole 104, a diffusion barrier layer 105, and a conductive layer 106.
An etch stop layer 102 is located over the substrate 101. The etch stop layer 102 is used to prevent over etching during etching of the contact hole 104, and to prevent damage to components below the contact hole 104 from over etching.
The material of the etch stop layer 102 comprises carbon doped silicon Nitride (NDC).
The etching stop layer 102 includes a plurality of stop layers stacked in this order in a direction away from the substrate 101.
In addition, the etch stop layer 102 has a barrier function for preventing unwanted elements (e.g., copper, tungsten, etc.) from diffusing into the protective layer 103 thereon.
A protective layer 103 is located over the etch stop layer 102, the material of the protective layer 103 comprising a low-k material. Wherein the low-k material comprises fluorosilicate glass (FSG). The low-k material is a dielectric material with a dielectric constant less than or equal to 3, and the protective layer 103 formed by the low-k material can achieve the purposes of reducing parasitic capacitance and power consumption.
The contact hole 104 penetrates the protective layer 103 and the etching stop layer 102; wherein the contact hole 104 includes a first portion 1041 penetrating the protective layer 103 and extending into the etching stop layer 102, and a second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104; the sidewall of the first portion 1041 of the contact hole 104 has a smaller inclination angle with respect to the bottom of the contact hole 104 than the sidewall of the second portion 1042 of the contact hole 104.
It is understood that the average pore size of the first portion 1041 of the contact hole 104 is greater than the average pore size of the second portion 1042 of the contact hole 104.
The contact holes 104 may extend down into the substrate 101 according to actual requirements.
The junction of the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a shoulder (turning point of the contact hole 104), and the shoulder is located in the second layer (as shown in fig. 1) or the third layer (as shown in fig. 2) of the etching stop layer 102.
The shoulder is spaced from the surface of the etch stop layer 102 away from the substrate 101 by a distance greater than a predetermined distance.
In this embodiment, the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 is located deep in the etching stop layer 102, far away from the junction between the two dielectric layers, and the transition is gentle, so that no sharp angle is formed.
The diffusion barrier layer 105 covers the sidewalls and bottom of the contact hole 104. The diffusion barrier layer 105 is used to prevent metal atoms from diffusing into other layers, and the material of the diffusion barrier layer 105 includes, but is not limited to, at least one of tantalum, tantalum nitride, titanium nitride, ruthenium, cobalt, nickel boron (NiB), and tungsten nitride.
Since the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a gentle transition, the diffusion barrier layer 105 has a better coverage at the junction, and the etching stop layer 102 below the diffusion barrier layer is not exposed, so that the source gas does not etch the etching stop layer 102 in the subsequent formation process of the conductive layer 106, and the problem of short circuit between the interconnection structures is greatly reduced.
The diffusion barrier 105 has a thickness at the junction of the first portion 1041 and the second portion 1042 of the contact hole 104 that is smaller than a thickness at the sidewall of the first portion 1041 of the contact hole 104 and the sidewall of the second portion 1042 of the contact hole 104.
In this embodiment, although the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a gentle transition and does not form a sharp angle, the diffusion barrier layer 105 formed at the junction between the first portion 1041 and the second portion is thinner than other locations due to the deposition process such as PECVD, but is sufficient to cover the junction (shoulder) and does not expose the etching stop layer 102 thereunder.
The thickness of the diffusion barrier layer 105 at the bottom of the contact hole 104 is greater than the thickness of the diffusion barrier layer 105 at the sidewall of the contact hole 104.
Also, the diffusion barrier layer 105 at the bottom of the contact hole 104 is thicker than at other locations due to a deposition process such as PECVD.
A conductive layer 106 is filled in the contact hole 104, the conductive layer 106 is used as a main conductive component of the metal interconnection structure, and a material of the conductive layer 106 includes tungsten (W).
The application provides a metal interconnection structure, which comprises a substrate 101, an etching stop layer 102 and a protective layer 103 which are sequentially laminated; a contact hole 104 penetrating the protective layer 103 and the etching stopper layer 102; wherein the contact hole 104 includes a first portion 1041 penetrating the protective layer 103 and extending into the etching stop layer 102, and a second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104; the inclination angle of the sidewall of the first portion 1041 of the contact hole 104 with respect to the bottom of the contact hole 104 is smaller than the inclination angle of the sidewall of the second portion 1042 of the contact hole 104 with respect to the bottom of the contact hole 104; a diffusion barrier layer 105 covering sidewalls and bottom of the contact hole 104; and a conductive layer 106 filled in the contact hole 104. Since the contact hole 104 includes the first portion 1041 penetrating the protection layer 103 and the second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104, that is, the connection between the first portion 1041 and the second portion 1042 of the contact hole 104 is located at the etching stop layer 102, the transition is gentle, no sharp angle is formed, the coverage of the diffusion barrier layer 105 is better, and the short circuit problem between the interconnection structures is greatly reduced.
Example two
As shown in fig. 3, an embodiment of the present application provides a metal interconnection structure, including: substrate 201, etch stop layer 202, isolation layer 203, protective layer 204, contact hole 205, diffusion barrier 206, and conductive layer 207.
An etch stop layer 202 is located above the substrate 201, and the etch stop layer 202 is used to prevent over etching during etching of the contact hole 205, so as to avoid damage to components below the contact hole 205 caused by over etching.
The material of the etch stop layer 202 includes carbon doped silicon Nitride (NDC).
The etching stop layer 202 includes a plurality of stop layers stacked in order in a direction away from the substrate 201.
In addition, the etch stop layer 202 also provides a barrier to prevent unwanted elements (e.g., copper, tungsten, etc.) from diffusing into the protective layer 204 above it.
An isolation layer 203 is located over the etch stop layer 202.
The material of the isolation layer 203 includes tetraethyl orthosilicate (TEOS).
TEOS has high surface mobility, can avoid the generation of low density and or voids, and can cover the space between interconnection structures with larger height and width.
A protective layer 204 is located over the isolation layer 203, the material of the protective layer 204 comprising a low-k material. Wherein the low-k material comprises fluorosilicate glass (FSG). The low-k material is a dielectric material with a dielectric constant less than or equal to 3, and the protective layer 204 formed by the low-k material can achieve the purposes of reducing parasitic capacitance and power consumption.
Wherein the thickness of the etching stop layer 202 and the protective layer 204 is greater than the thickness of the isolation layer 203.
The contact hole 205 penetrates the protective layer 204 and the etching stop layer 202; wherein the contact hole 205 includes a first portion 2051 penetrating the protective layer 204 and the isolation layer 203 into the etch stop layer 202, and a second portion 2052 disposed in the etch stop layer 202 and connected to the first portion 2051 of the contact hole 205; the sidewall of the first portion 2051 of the contact hole 205 has a smaller inclination angle relative to the bottom of the contact hole 205 than the sidewall of the second portion 2052 of the contact hole 205.
It is understood that the aperture of the first portion 2051 of the contact hole 205 is greater than the aperture of the second portion 2052 of the contact hole 205.
The contact hole 205 may extend down into the substrate 201 according to actual requirements.
The etch stop layer 202 is denser than the isolation layer 203 and the protective layer 204, so if the junction of the first portion 2051 of the contact hole 205 and the second portion 2052 of the contact hole 205 is located at the location of the etch stop layer 202, the junction may be extremely sharp.
In this embodiment, a shoulder (turning point of the contact hole 205) is formed at the connection between the first portion 2051 of the contact hole 205 and the second portion 2052 of the contact hole 205, and the shoulder is located in the second layer (as shown in fig. 3) or the third layer (as shown in fig. 4) of the etching stop layer 202.
The shoulder is a distance greater than a predetermined distance from the surface of the etch stop layer 202 away from the substrate 201.
The junction of the first portion 2051 of the contact hole 205 and the second portion 2052 of the contact hole 205 is located deep in the etch stop layer 202, away from the junction of the two dielectric layers and in principle the isolation layer 203, and the transition is relatively gentle and does not form a sharp angle.
The diffusion barrier 206 covers the sidewalls and bottom of the contact hole 205. The diffusion barrier layer 206 is used to prevent metal atoms from diffusing into other layers, and the material of the diffusion barrier layer 206 includes, but is not limited to, at least one of tantalum, tantalum nitride, titanium nitride, ruthenium, cobalt, nickel boron (NiB), and tungsten nitride.
Since the transition between the first portion 2051 of the contact hole 205 and the second portion 2052 of the contact hole 205 is relatively smooth, the diffusion barrier layer 206 has relatively good coverage at the connection, and the etching stop layer 202 below the diffusion barrier layer is not exposed, so that the source gas does not etch the etching stop layer 202 in the subsequent formation of the conductive layer 207, and the short circuit problem between the interconnection structures is greatly reduced.
The diffusion barrier 206 has a thickness at the junction of the first portion 2051 and the second portion 2052 of the contact hole 205 that is less than the thickness of the diffusion barrier at the sidewall of the first portion 2051 of the contact hole 205 and the sidewall of the second portion 2052 of the contact hole 205.
Although the junction between the first portion 2051 of the contact hole 205 and the second portion 2052 of the contact hole 205 has a gentle transition and does not form a sharp angle, the diffusion barrier layer 206 formed at the junction between the first portion 2051 and the second portion 2052 is thinner than at other locations due to a deposition process such as PECVD, but is also sufficient to cover the junction (shoulder) without exposing the etch stop layer 202 thereunder.
The thickness of the diffusion barrier layer 206 at the bottom of the contact hole 205 is greater than the thickness of the diffusion barrier layer 206 at the sidewalls of the contact hole 205.
Also, the diffusion barrier layer 206 at the bottom of the contact hole 205 is thicker than at other locations due to a deposition process such as PECVD.
A conductive layer 207 is filled in the contact hole 205, the conductive layer 207 being the main conductive component of the metal interconnect structure, the material of the conductive layer 207 comprising tungsten (W).
The application provides a metal interconnection structure, which comprises a substrate 201, an etching stop layer 202, an isolation layer 203 and a protection layer 204 which are sequentially laminated; a contact hole 205 penetrating the protective layer 204, the isolation layer 203, and the etch stop layer 202; wherein the contact hole 205 includes a first portion 2051 penetrating the protective layer 204 and the isolation layer 203 and extending into the etch stop layer 202, and a second portion 2052 disposed in the etch stop layer 202 and connected to the first portion 2051 of the contact hole 205; the inclination angle of the sidewall of the first portion 2051 of the contact hole 205 with respect to the bottom of the contact hole 205 is smaller than the inclination angle of the sidewall of the second portion 2052 of the contact hole 205 with respect to the bottom of the contact hole 205; a diffusion barrier layer 206 covering sidewalls and bottom of the contact hole 205; and a conductive layer 207 filled in the contact hole 205. Since the contact hole 205 includes the first portion 2051 penetrating the protective layer 204 and the isolation layer 203 and extending into the etch stop layer 202, and the second portion 2052 disposed in the etch stop layer 202 and connected to the first portion 2051 of the contact hole 205, that is, the connection between the first portion 2051 and the second portion 2052 of the contact hole 205 is located at the etch stop layer 202, the transition is gentle, no sharp angle is formed, the coverage of the diffusion barrier layer 206 is better, and the short circuit problem between the interconnection structures is greatly reduced.
Example III
On the basis of the first embodiment or the second embodiment, the present embodiment provides a method for manufacturing a metal interconnection structure. Fig. 5 is a schematic flow chart of a preparation method of a metal interconnection structure according to an embodiment of the present application. Fig. 6 to 8 are schematic cross-sectional structures formed by relevant steps of a method for manufacturing a metal interconnection structure according to an embodiment of the present application. The following describes detailed steps of an exemplary method for preparing a metal interconnect structure according to an embodiment of the present application with reference to fig. 5 and fig. 6 to 8.
As shown in fig. 5, the method for preparing the metal interconnection structure of the embodiment includes the following steps:
step S110: a substrate 101 is provided.
Step S120: as shown in fig. 6, an etching stop layer 102 and a protective layer 103 are sequentially formed over a substrate 101.
An etch stop layer 102 is located over the substrate 101. The etch stop layer 102 is used to prevent over etching during subsequent contact hole etching, and to avoid damage to components below the contact hole caused by over etching.
The material of the etch stop layer 102 comprises carbon doped silicon Nitride (NDC).
The etching stop layer 102 includes a plurality of stop layers stacked in this order in a direction away from the substrate 101.
In addition, the etch stop layer 102 has a barrier function for preventing unwanted elements (e.g., copper, tungsten, etc.) from diffusing into the protective layer 103 thereon.
A protective layer 103 is located over the etch stop layer 102, the material of the protective layer 103 comprising a low-k material. Wherein the low-k material comprises fluorosilicate glass (FSG). The low-k material is a dielectric material with a dielectric constant less than or equal to 3, and the protective layer 103 formed by the low-k material can achieve the purposes of reducing parasitic capacitance and power consumption.
In addition, an isolation layer can be formed between the etching stop layer 102 and the protection layer 103, the surface mobility of the isolation layer is high, the generation of low density and or voids can be avoided, and the space between the interconnection structures with high aspect ratio can be covered.
Step S130: as shown in fig. 7, a contact hole 104 penetrating the protective layer 103 and the etching stopper layer 102 is formed; wherein the contact hole 104 includes a first portion 1041 penetrating the protective layer 103 and extending into the etching stop layer 102, and a second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104; the sidewall of the first portion 1041 of the contact hole 104 has a smaller inclination angle with respect to the bottom of the contact hole 104 than the sidewall of the second portion 1042 of the contact hole 104.
It is understood that the average pore size of the first portion 1041 of the contact hole 104 is greater than the average pore size of the second portion 1042 of the contact hole 104.
The contact holes 104 may extend down into the substrate 101 according to actual requirements.
The junction of the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a shoulder (turning point of the contact hole 104), and the shoulder is located in the second layer or the third layer of the etching stop layer 102.
The shoulder is spaced from the surface of the etch stop layer 102 away from the substrate 101 by a distance greater than a predetermined distance.
In this embodiment, the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 is located deep in the etching stop layer 102, far away from the junction between the two dielectric layers, and the transition is gentle, so that no sharp angle is formed.
Step S140: as shown in fig. 8, a diffusion barrier layer 105 is formed to cover the sidewalls and bottom of the contact hole 104.
The diffusion barrier layer 105 covers the sidewalls and bottom of the contact hole 104. The diffusion barrier layer 105 is used to prevent metal atoms from diffusing into other layers, and the material of the diffusion barrier layer 105 includes, but is not limited to, at least one of tantalum, tantalum nitride, titanium nitride, ruthenium, cobalt, nickel boron (NiB), and tungsten nitride.
Since the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a gentle transition, the diffusion barrier layer 105 has a better coverage at the junction, and the etching stop layer 102 below the diffusion barrier layer is not exposed, so that the source gas does not etch the etching stop layer 102 in the subsequent formation process of the conductive layer 106, and the problem of short circuit between the interconnection structures is greatly reduced.
The thickness of the diffusion barrier layer 105 at the junction of the first portion 1041 and the second portion 1042 of the contact hole 104 is smaller than the thickness thereof at the side wall of the first portion 1041 of the contact hole 104 and the side wall of the second portion 1042 of the contact hole 104, i.e. the thickness of the diffusion barrier layer 105 at the junction of the first portion 1041 and the second portion 1042 is thinnest.
In this embodiment, although the junction between the first portion 1041 of the contact hole 104 and the second portion 1042 of the contact hole 104 has a gentle transition and does not form a sharp angle, the diffusion barrier layer 105 formed at the junction between the first portion 1041 and the second portion is thinner than other locations due to the deposition process such as PECVD, but is sufficient to cover the junction (shoulder) and does not expose the etching stop layer 102 thereunder.
The thickness of the diffusion barrier layer 105 at the bottom of the contact hole 104 is greater than the thickness of the diffusion barrier layer 105 at the sidewall of the contact hole 104.
Also, the diffusion barrier layer 105 at the bottom of the contact hole 104 is thicker than at other locations due to a deposition process such as PECVD.
Step S150: a conductive layer 106 is formed to fill the contact hole 104.
A conductive layer 106 is filled in the contact hole 104, the conductive layer 106 is used as a main conductive component of the metal interconnection structure, and a material of the conductive layer 106 includes tungsten (W).
The application provides a method for preparing a metal interconnection structure, which comprises the steps of providing a substrate 101; forming an etching stop layer 102 and a protective layer 103 in sequence over the substrate 101; forming a contact hole 104 penetrating the protective layer 103 and the etching stop layer 102; wherein the contact hole 104 includes a first portion 1041 penetrating the protective layer 103 and extending into the etching stop layer 102, and a second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104; the inclination angle of the sidewall of the first portion 1041 of the contact hole 104 with respect to the bottom of the contact hole 104 is smaller than the inclination angle of the sidewall of the second portion 1042 of the contact hole 104 with respect to the bottom of the contact hole 104; forming a diffusion barrier layer 105 covering the sidewalls and bottom of the contact hole 104; a conductive layer 106 is formed to fill the contact hole 104. Since the contact hole 104 includes the first portion 1041 penetrating the protection layer 103 and the second portion 1042 disposed in the etching stop layer 102 and connected to the first portion 1041 of the contact hole 104, that is, the connection between the first portion 1041 and the second portion 1042 of the contact hole 104 is located at the etching stop layer 102, the transition is gentle, no sharp angle is formed, the coverage of the diffusion barrier layer 105 is better, and the short circuit problem between the interconnection structures is greatly reduced.
Example IV
On the basis of the first embodiment or the second embodiment, the present embodiment provides a semiconductor device including at least one metal interconnection structure as described in the first embodiment or the second embodiment.
The semiconductor device further comprises an active structure such as a transistor arranged in the substrate, and the metal interconnection structure is contacted with a source electrode and a drain electrode of the transistor.
While the embodiments disclosed herein are described above, the descriptions are presented only to facilitate an understanding of the present application and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of protection of this application shall be subject to the scope of the claims that follow.
Claims (12)
1. A metal interconnect structure, comprising:
sequentially laminating a substrate, an etching stop layer and a protective layer;
a contact hole penetrating the protective layer and the etch stop layer; wherein the contact hole comprises a first part penetrating the protective layer and extending into the etching stop layer, and a second part arranged in the etching stop layer and connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole;
a diffusion barrier layer covering the side wall and the bottom of the contact hole, wherein the diffusion barrier layer comprises the following materials: a metal nitride;
and the conductive layer is filled in the contact hole.
2. The metal interconnect structure of claim 1, wherein the etch stop layer comprises a plurality of stop layers disposed sequentially stacked in a direction away from the substrate.
3. The metal interconnect structure of claim 2, wherein the junction of the first portion of the contact hole and the second portion of the contact hole has a shoulder;
wherein the shoulder is located within the second or third layer of the etch stop layer.
4. The metal interconnect structure of claim 3, wherein the shoulder is a distance greater than a predetermined distance from a surface of the etch stop layer remote from the substrate.
5. The metal interconnect structure of claim 1, wherein a thickness of the diffusion barrier layer at a junction of the first portion and the second portion of the contact hole is less than a thickness of a sidewall of the first portion of the contact hole and a sidewall of the second portion of the contact hole.
6. The metal interconnect structure of claim 1, wherein a thickness of the diffusion barrier layer at a bottom of the contact hole is greater than a thickness of the diffusion barrier layer at a sidewall of the contact hole.
7. The metal interconnect structure of claim 1, further comprising: an isolation layer between the etch stop layer and the protection layer;
the thickness of the etching stop layer and the thickness of the protection layer are larger than those of the isolation layer, and the first part of the contact hole penetrates through the isolation layer.
8. The metal interconnect structure of claim 7, wherein the etch stop layer is more dense than the isolation layer and the protective layer.
9. The metal interconnect structure of claim 1, wherein the material of the etch stop layer comprises carbon doped silicon nitride.
10. The metal interconnect structure of claim 1, wherein the material of the protective layer comprises a low-k material.
11. The metal interconnect structure of any of claims 1 to 10, wherein the metal nitride comprises at least one of: tantalum nitride, titanium nitride, tungsten nitride.
12. A semiconductor device comprising at least one metal interconnect structure as claimed in any one of claims 1 to 11.
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| KR20030000118A (en) * | 2001-06-22 | 2003-01-06 | 주식회사 하이닉스반도체 | Forming method for metal line of semiconductor device |
| KR20050009936A (en) * | 2003-07-18 | 2005-01-26 | 매그나칩 반도체 유한회사 | Method for forming metal-line of the semiconductor device |
| KR100655774B1 (en) * | 2004-10-14 | 2006-12-11 | 삼성전자주식회사 | Etching stop structure, method of manufacturing the etching stop structure, semiconductor device having the etching stop structure and method of manufacturing the semiconductor device |
| KR20090128900A (en) * | 2008-06-11 | 2009-12-16 | 크로스텍 캐피탈, 엘엘씨 | Method for manufacturing cmos image sensor |
| US11088020B2 (en) * | 2017-08-30 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of interconnection structure of semiconductor device |
| CN110634801B (en) * | 2019-10-18 | 2022-04-22 | 中国科学院微电子研究所 | Contact hole preparation method |
| CN215183937U (en) * | 2021-07-20 | 2021-12-14 | 福建省晋华集成电路有限公司 | Metal interconnection structure and semiconductor device |
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