CN117851293A

CN117851293A - Address translation module, display controller, processing system, electronic component, electronic device, and page table prefetching method

Info

Publication number: CN117851293A
Application number: CN202410257135.XA
Authority: CN
Inventors: 余德君; 唐志敏
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2024-03-07
Filing date: 2024-03-07
Publication date: 2024-04-09

Abstract

The disclosure provides an address translation module, a display controller, a processing system, an electronic component, electronic equipment and a page table prefetching method, which are applicable to multimedia playing scenes and aim to improve the memory access efficiency and performance in the multimedia playing process. The page table prefetching method comprises the following steps: the display controller sends a page table prefetching request to the address translation module; the address translation module is used for responding to the page table prefetching request and prefetching page tables corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal. The page table reading operation does not occupy the validity period of the digital image signal, does not influence the reading of pixel data, and can improve the memory access efficiency and the memory access performance. In addition, the page table is prefetched intensively as required, so that the situation that the memory address accessed next is not in the coverage range of the prefetched page table can be avoided to a certain extent, and the memory access efficiency is further improved.

Description

Address translation module, display controller, processing system, electronic component, electronic device, and page table prefetching method

Technical Field

The disclosure relates to the technical field of page table prefetching, and in particular relates to an address translation module, a display controller, a processing system, an electronic component, electronic equipment and a page table prefetching method.

Background

In a computer system, devices access memory using virtual addresses that need to be translated to physical addresses on the memory. The mapping relation between the virtual address and the physical address is stored in a page table. To improve address translation efficiency, page table prefetching may be performed. The traditional page table prefetching scheme is: triggering page table prefetching when a virtual address carried by a memory access request crosses page tables, and particularly calculating the number of prefetchable page tables according to the cache capacity for storing the prefetched page tables; and determining the address of the page table to be prefetched according to the currently accessed virtual address and the prefetchable page table number N, wherein the address is the address offset corresponding to the currently accessed virtual address +N Zhang Yebiao, and prefetching N page tables from the address. The page table prefetching mode can effectively reduce the probability of page table miss (page miss), and improves the address translation efficiency, thereby improving the memory access efficiency. However, in some extreme cases of the multimedia playing scenario, the memory address of the next access is not within the coverage of the prefetched page table, meaning that the prefetching is not effective, and in this case, the purpose of improving the memory access efficiency is not achieved through the prefetching of the page table.

In addition, page table prefetching is also an operation of reading the memory, and the read operation of page table prefetching occurs when the virtual address crosses the page table, and at this time, the device itself is reading the memory, and the efficiency of reading the memory is affected in the command queue of the memory regardless of the priority of page table prefetching, so that the bandwidth of the device reading the memory may be affected.

Disclosure of Invention

The disclosure aims to provide an address translation module, a display controller, a processing system, an electronic component, electronic equipment and a page table prefetching method, so as to improve the memory access efficiency and performance in the multimedia playing process.

According to one aspect of the present disclosure, there is provided an address translation module configured to: and in response to the page table prefetching request, prefetching a page table corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal.

The address translation module may be implemented by, but not limited to, MMU (Memory Management Unit ).

In one possible implementation, the page table prefetch request carries the address of at least one row of pixel data to be displayed. Correspondingly, the address translation module receives a page table prefetching request, and prefetches the page table in the blanking period of the digital image signal according to the address in the page table prefetching request.

In another possible implementation, the page table prefetch request carries the start address of the image frame, and then the address of at least one row of pixel data to be displayed may be expressed as the start address of the image frame+the address offset of the pixel data relative to the start address of the image frame. In order to prefetch the page table, the address translation module also needs to acquire the address offset of at least one row of pixel data to be displayed in the image frame relative to the starting address of the image frame, and further prefetch the page table in the blanking period of the digital image signal according to the starting address and the address offset.

Based on any of the address translation module embodiments described above, the page table prefetch request may be sent during a blanking period of the digital image signal.

On the basis of any one of the above embodiments of the address translation module, the address translation module is configured to: and prefetching a page table corresponding to the pixel data of the next row to be displayed in the blanking period of the digital image signal.

On the basis of any of the above address translation module embodiments, the address translation module is further configured to: before a first image frame of the multimedia is displayed, a page table corresponding to at least a first row of pixel data of the first image frame is prefetched in response to a page table prefetch request.

On the basis of any one of the address translation module embodiments, for the multi-stage page table, the page table corresponding to at least one row of pixel data at least includes a last-stage page table corresponding to the at least one row of pixel data.

On the basis, optionally, the address translation module prefetches a last stage page table corresponding to at least one row of pixel data to be displayed in a row blanking period; and prefetching each stage of page table corresponding to at least one row of pixel data to be displayed in the vertical blanking period.

According to another aspect of the present disclosure, there is provided a display controller configured to: and sending a page table prefetching request to the address translation module, so that the address translation module prefetches a page table corresponding to at least one row of pixel data to be displayed in a blanking period of the digital image signal in response to the page table prefetching request.

In one possible implementation, the page table prefetch request carries the address of at least one row of pixel data to be displayed.

In another possible implementation, the page table prefetch request carries the start address of the image frame.

In accordance with any of the above display controller embodiments, the display controller is configured to send the page table prefetch request during a blanking period of the digital image signal.

On the basis of any of the above display controller embodiments, a page table prefetch request is sent before the first image frame of the multimedia is sent.

On the basis of any one of the above embodiments of the display controller, for the multi-stage page table, the page table corresponding to at least one row of pixel data includes at least a last-stage page table corresponding to the at least one row of pixel data.

According to another aspect of the present disclosure, a processing system is provided, including an address translation module as described in any one of the embodiments above and a display controller as described in any one of the embodiments above.

According to another aspect of the present disclosure, there is provided an electronic assembly comprising a processing system according to any of the embodiments described above.

According to another aspect of the present disclosure, there is provided an electronic device including the electronic assembly according to any one of the above embodiments.

According to another aspect of the present disclosure, there is provided a page table prefetching method including the steps of:

the display controller sends a page table prefetching request to the address translation module; the address translation module is used for responding to the page table prefetching request and prefetching page tables corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal.

In one possible implementation, the page table prefetch request carries an address of at least one row of pixel data to be displayed, and the address translation module prefetches the page table in a blanking period of the digital image signal according to the address.

In another possible implementation manner, the page table prefetching request carries a start address of an image frame, the address translation module obtains an address offset of at least one line of pixel data to be displayed in the image frame relative to the start address of the image frame, and prefetches the page table in a blanking period of the digital image signal according to the start address and the address offset.

On the basis of any of the method embodiments described above, the display controller sends a page table prefetch request to the address translation module during a blanking period of the digital image signal.

On the basis of any of the above method embodiments, the address translation module, in response to a page table prefetch request, prefetches a page table corresponding to pixel data of a next line to be displayed in a blanking period of the digital image signal.

On the basis of any of the above method embodiments, the display controller may further send a page table prefetch request to the address translation module before the first image frame of the multimedia is sent to display; accordingly, the address translation module is used for prefetching the page table corresponding to at least the first row of pixel data of the first image frame before the first image frame of the multimedia is sent to display in response to the page table prefetching request.

On the basis of any one of the above method embodiments, for the multi-stage page table, the page table corresponding to at least one row of pixel data includes at least a last-stage page table corresponding to the at least one row of pixel data.

On the basis, prefetching a page table corresponding to at least one row of pixel data to be displayed in a blanking period of the digital image signal, the method can comprise the following steps: pre-fetching a last stage page table corresponding to at least one row of pixel data to be displayed in a row blanking period; and prefetching each stage of page table corresponding to at least one row of pixel data to be displayed in the vertical blanking period.

Drawings

FIG. 1 is a schematic diagram of the operating principle of a processing system according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a graphics processing system according to one embodiment of the present disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

The purpose of the present disclosure is to provide a scheme for prefetching page tables as required, which is suitable for multimedia playing scenes, and aims to improve the memory access efficiency and performance in the multimedia playing process. Specifically, the address translation module is used for responding to a page table prefetching request and prefetching page tables corresponding to at least one row of pixel data to be displayed in a blanking period of the digital image signal. The read memory operation for reading the pixel data to be displayed occurs during the validity period of the digital image signal, and according to the scheme provided by the embodiment of the disclosure, the read memory operation for prefetching the page table occurs during the blanking period of the digital image signal. Therefore, the page table reading operation does not occupy the valid period of the digital image signal, on one hand, the page table reading operation does not need to wait for the pixel data reading operation with high priority, and the page table reading operation cannot be interrupted due to the pixel data reading request with high priority, so that when the page table is required to be utilized for address translation, the page table prefetching can be completed, and therefore, higher address translation efficiency can be maintained, namely, the efficiency of memory access is improved; on the other hand, the page table reading operation does not influence the pixel data reading, so that the reading memory efficiency of the pixel data is prevented from being influenced by the existence of the related command for prefetching the page table in the command queue, namely, the memory access efficiency is improved, and the reading memory bandwidth of the pixel data is prevented from being influenced by the existence of the related command for prefetching the page table in the command queue, namely, the memory access performance is improved. In addition, the page table corresponding to at least one row of pixel data to be displayed is prefetched, which belongs to a prefetching mode according to the need, so that the situation that the memory address accessed next time is not in the coverage range of the prefetched page table can be avoided to a certain extent, and the memory access efficiency is further improved.

The multimedia in the embodiments of the present disclosure at least includes an image (such as a video image, a still image, a moving image, etc.), and the display timing of the image at least includes a blanking period of a digital image signal and an effective period of the digital image signal. In general, pixel data of an image is transmitted during the validity period of a digital image signal, and a multimedia playback related signal, such as multimedia audio data, multimedia subtitle data, or the like, is transmitted during the blanking period of the digital image signal. In the disclosed embodiment, the page table prefetched relevant signals are also transmitted during the digital image signal blanking period.

In the embodiment of the present disclosure, the page table corresponding to one line of pixel data refers to a page table covering an address space of one line of pixel data.

In the embodiment of the disclosure, one effective period of the digital image signal transmits one line of pixel data, and the blanking period of the digital image signal includes a line blanking period and a field blanking period. For a line blanking period, the end of the active period of one digital image signal is taken as the beginning of a line blanking period, and the beginning of the active period of the next digital image signal is taken as the end of the line blanking period. For the vertical blanking period, the end of the last digital image signal active period of one image frame serves as the start of a vertical blanking period, and the start of the first digital image signal active period of the next image frame serves as the end of the vertical blanking period.

Typical line blanking periods include three phases, front blanking Porch, line synchronization (H-Sync), back blanking Porch, and page table prefetching may occur in any of these three phases, or across phases, as provided by embodiments of the present disclosure. As long as the predetermined page table prefetch is completed in one line blanking period.

Typical vertical blanking periods include three phases, a blanking front-shoulder, a vertical synchronization (V-Sync), and a blanking back-shoulder, and page table prefetching may occur in any of these three phases, or across phases, as provided by embodiments of the present disclosure. As long as the predetermined page table prefetch is completed in one vertical blanking period.

The scheme for prefetching the page table according to the embodiment of the disclosure is applicable to the case of a single-stage page table and is also applicable to the case of a multi-stage page table. In display applications where the size of a row of pixels is small relative to the page table, e.g., in an 8K display scenario where the address space of a row of pixels is 32KB, the probability of an advanced page table miss is small and the impact of the miss is almost negligible. Thus, for multi-level page tables, the scheme provided by embodiments of the present disclosure may be employed to prefetch the last level page table. Of course, in pursuit of better performance, advanced page tables other than the last stage page table may also be prefetched using the scheme provided by embodiments of the present disclosure. Since the high-level page table is shared by multiple rows of pixel data, the prefetch frequency of the high-level page table may be lower than that of the last-level page table. The specific pre-fetching frequency of the high-level page table is determined according to the actual application scene, and the disclosure is not limited. Further, an advanced page table corresponding to one frame of pixel data may be prefetched during the vertical blanking period.

Furthermore, for multi-level page tables, each level of page tables may be cached separately, that is, each level of page tables corresponds to a different page table cache space.

Specifically, one embodiment of the present disclosure provides an address translation module configured to: and in response to the page table prefetching request, prefetching a page table corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal.

Wherein the address translation module may be implemented by, but is not limited to, an MMU.

The page tables are stored in a continuous space in the memory, and the number of page tables which can be prefetched by the address translation module at a time depends on the cache capacity for storing the prefetched page tables and the size of the page tables. Taking a single-level page table as an example, assuming that the cache capacity of storing the prefetch page table is 64KB, 16 page tables can be prefetched for a page table with a size of 4KB, and only 2 page tables can be prefetched for a page table with a size of 32 KB. In the embodiment of the disclosure, the buffer capacity can be designed by combining the page table size and the image line size, so that the address translation module can prefetch the page table corresponding to at least one line of pixel data at a time, and therefore the page table corresponding to at least one line of pixel data is prefetched in the digital image signal blanking period set. Assuming that the size of the page table in the system is 4KB, and the memory size occupied by a line of pixel data in the image is 16KB, for a single-level page table, address translation of a line of pixel data read operation needs 4 page tables, and the above-mentioned cache capacity is designed to store N Zhang Yebiao, where N is an integer multiple of 4. For a multi-stage page table, 4 last-stage page tables are needed for address translation of a row of pixel data read operation, and the buffer capacity corresponding to the last-stage page tables is designed to be capable of storing N Zhang Yebiao, wherein N is an integer multiple of 4; correspondingly, for a multi-stage page table, the page table corresponding to one row of pixel data at least comprises a last stage page table.

As described above, prefetching the page table during the blanking period of the digital image signal does not affect the image data read operation, and the page table prefetching corresponding to one line of pixel data is sufficient during the blanking period of the digital image signal. The cache capacity can be designed to support page table prefetching for a row of pixel data without requiring a larger cache capacity to be designed. In this case, the page table corresponding to the next line of pixel data may be prefetched in each digital image signal blanking period. That is, for a single-stage page table, the page table is prefetched as needed according to the order in which the frames are displayed, the page table where the next row address is located is prefetched in the line blanking period, and the page table where the first row address of the next frame is located is prefetched in the line blanking period. For a multi-stage page table, pre-fetching the page table according to the sequence of frame display as required, pre-fetching a high-stage page table (relative to a last-stage page table) where each row address of a next frame is located in a vertical blanking period, and pre-fetching a last-stage page table where a first row address of the next frame is located; the last stage page table where the next row address is located is prefetched in the row blanking period. Of course, the corresponding high-level page table may be prefetched in the digital image signal blanking period (may be the line blanking period or the field blanking period) at a specific frequency according to the number of lines covered by each high-level page table. By this prefetching approach, a page miss during the multimedia presentation can be avoided. In addition, the page table where the concentrated continuous prefetching one row address is located can effectively improve the efficiency of reading the memory.

The next line of pixel data refers to a line of pixel data read and displayed after the blanking period of the current digital image signal is ended.

It should be noted that if different page table sizes exist in the system, the cache capacity is designed based on the largest page table size. If the system supports images of different sizes, the buffer capacity is designed based on the size of the largest image line.

Of course, if the cache capacity supports, page tables corresponding to two or more lines of pixel data may be prefetched at a time. For example, if the cache capacity designed based on the page table with the size of 4KB and the image line with the size of 16KB is 16KB and the currently displayed image line size is 8KB, then the page tables corresponding to the two lines of pixel data can be prefetched in one digital image signal blanking period, and the page table prefetching can be performed in the interval digital image signal blanking period, without performing the page table prefetching in each digital image signal blanking period.

No matter how many lines of page tables corresponding to pixel data are prefetched in a blanking period of a digital image signal, an address translation module needs to determine the address of a page table to be prefetched according to a page table prefetching request.

In one possible implementation, the page table prefetch request carries the address of at least one row of pixel data to be displayed. Correspondingly, the address translation module receives a page table prefetching request, and prefetches the page table in the blanking period of the digital image signal according to the address carried in the page table prefetching request.

More specifically, the address carried in the page table prefetch request may include a start address and an end address of the at least one row of pixel data, and the address translation module performs page table prefetch according to an address space determined by the start address and the end address, so that the prefetched page table covers the address space. The present disclosure is not limited to the specific form of a start address and an end address, which may be represented by an offset from the start address by way of example and not limitation. In addition, the address carried in the page table prefetch request may only include the start address of the at least one row of pixel data, and the address translation module determines the span of the at least one row of pixel data in other manners, so as to prefetch the address space that needs to be covered by the page table. By way of example, and not limitation, the image resolution may be pre-stored in a register corresponding to the address translation module during the display initialization stage, and the address translation module determines the span of the at least one line of pixel data from the image resolution.

On this basis, if the above-mentioned buffer capacity only supports the page table storage corresponding to a line of pixel data of the current multimedia play, then the page table corresponding to the next line of pixel data needs to be prefetched in each digital image signal blanking period of each image frame of the current multimedia play, and accordingly, each prefetching is triggered by a corresponding page table prefetching request. If the buffer capacity supports the storage of page tables corresponding to two lines of pixel data of the current multimedia play, then the page tables corresponding to the two lines of pixel data can be prefetched in a digital image signal blanking period, then the page tables are prefetched again in an interval digital image signal blanking period, and the prefetching is triggered by a corresponding page table prefetching request. If the above-mentioned buffer capacity supports the storage of page tables corresponding to more lines of pixel data of the current multimedia play, the implementation manner of prefetching two lines of page tables may be referred to, which is not described herein again.

The embodiments of the present disclosure do not define how the address translation module obtains an address offset of at least one row of pixel data to be displayed in an image frame relative to a start address of the image frame. By way of example and not limitation, the address translation module may determine the address offset in combination with the prefetch count and the stride described above.

On the basis, if the cache capacity only supports the storage of a page table corresponding to one line of pixel data of the current multimedia playing, the page table corresponding to the next line of pixel data needs to be prefetched in each digital image signal blanking period of each image frame of the current multimedia playing; accordingly, each prefetch may be triggered by a corresponding page table prefetch request, or alternatively, only one page table prefetch request may be sent for one image frame. If the buffer capacity supports the storage of page tables corresponding to two lines of pixel data of the current multimedia play, then the page tables corresponding to the two lines of pixel data can be prefetched in a blanking period of a digital image signal, then the page tables are prefetched again in an interval of the blanking period of the digital image signal, and likewise, each prefetching can be triggered by a corresponding page table prefetching request, and also can send the page table prefetching request only once for one image frame. If the above-mentioned buffer capacity supports the storage of page tables corresponding to more lines of pixel data of the current multimedia play, the implementation manner of prefetching two lines of page tables may be referred to, which is not described herein again.

In order to further reduce the impact on pixel data read operations, page table prefetch requests may be sent during the blanking period of the digital image signal, based on any of the address translation module embodiments described above. In the solution provided by the embodiments of the present disclosure, the page table prefetch request may be sent during any one of the phases of the line blanking period (or the vertical blanking period).

Further, when the display device is registered and started, the address translation module is used for responding to a page table prefetching request to prefetch a page table corresponding to at least first row of pixel data of the first image frame.

Based on the same inventive concept, the disclosed embodiments also provide a display controller (Display Controller, DC) configured to: and sending a page table prefetching request to the address translation module, so that the address translation module prefetches a page table corresponding to at least one row of pixel data to be displayed in a blanking period of the digital image signal in response to the page table prefetching request.

Referring to the description of the embodiment of the address translation module, the page table prefetch request sent by the display controller may carry an address of at least one row of pixel data to be displayed, and may also carry a start address of an image frame.

By way of example and not limitation, the display controller may calculate the address of the next line from the frame buffer start address and the image line size issued by the software, carrying the address in the page table prefetch request. And the address translation module calculates a corresponding page table address according to the changed address, thereby completing page table prefetching.

Referring to the description of the address translation module embodiment above, the display controller may send a page table prefetch request during the digital image signal blanking period.

With reference to the description of the address translation module embodiment above, the display controller may also send a page table prefetch request prior to the first image frame of the multimedia being displayed.

Still further, the display controller may send a page table prefetch request when the display device is registered for startup.

The embodiment of the disclosure also provides a processing system, which comprises the address translation module and the display controller.

By way of example and not limitation, as shown in FIG. 1, the processing system includes a display controller and an MMU. The display controller is used for driving the display device to output image frame contents according to time sequence, the MMU is used for translating virtual addresses and physical addresses and prefetching page tables, and the MMU is provided with a page table cache for storing the prefetched page tables.

The display controller may obtain timing information for driving the display device, including information of a valid period of a digital image signal (also called (Active video) valid video period if a display object is video), information of a blanking period (blanking), information of line-field synchronization, information of display lines and columns, and the like. The display controller may also obtain information about the image frame to be read, including the start address of the image frame, the size of the image frame, and the span (stride) of the image lines in memory.

When the display device is registered and started, the display controller initiates a memory access request before the validity period of the digital image signal corresponding to the first line of the first image frame, wherein the memory access request carries the starting address of the first image frame, and the memory access request is of a type of 'prefetch', namely a page table prefetch request.

It should be noted that once the information required for the page table prefetch request is obtained, the display controller may send the page table prefetch request.

After receiving the access request, the MMU analyzes the type of the access request, definitely refers to a page table prefetching request, and initiates a reading operation to an area storing a page table in the memory according to the setting of the address of the MMU page table. In this embodiment, the MMU defaults to prefetching page tables for a row address space covered. For multi-level page tables, the MMU defaults to pre-fetch the last level page table of a row address space covered.

The display controller then initiates a memory request of type "normal" to read the image content of a row normally and drive the display. In the reading of this line of image content, there is no page miss because the prefetched page table already covers the virtual address range of the line of content. Each time a normal request issued by the controller is displayed, the MMU can look up the corresponding physical address from the TLB. When the validity period of the digital image signal of one line is over, the display controller initiates a page table prefetch request again in the following blanking period of the digital image signal, and the MMU prefetches the page table of the next line according to the request. In this loop, until the end of the frame. During the vertical blanking period, the display controller initiates a page table prefetching request again according to the setting of the frame buffer of the next frame of the loading (loading), and prefetches the page table of the first row of the next frame. And so on.

Assuming that the resolution of the video to be displayed is 4K, the system page table is 4KB, the frame start address is a, the input format is RGB 10-bit, the memory size occupied by one line is 4096×4, i.e. 16KB, so the page table cache of the MMU is designed to support the storage of 4 page tables. The first prefetching is carried out before the effective period of the first digital image signal of the first image frame of the video, the address carried in the access request sent by the display controller is A, the access request type is page table prefetching, and the MMU prefetches 4KB page tables according to the address A. In the line blanking period of the first line, the address carried in the access request sent by the display controller is A+16KB, the type of the access request is page table prefetching, and the MMU prefetches 4KB page tables. For the display controller, the page table prefetch request only requires a request response (request response), and no data response (data response) is required. The page table prefetched by the MMU performs page table walk according to the page table format, and the translated physical address is stored in the TLB. When the display controller issues a normal request, the MMU may obtain the corresponding physical address through a TLB lookup.

The processing system provided by the embodiment of the disclosure can be a graphic processing system or other computer systems supporting multimedia playing output.

Taking a graphics processing System as an example, the graphics processing System may be a SOC (System on Chip). More specifically, the SOC may be one die, one SOC with multiple die interconnects, multiple SOCs with inter-chip interconnects, or other organization.

The page table prefetching scheme provided in the present disclosure is described below using SOC of one die as an example.

In one embodiment shown in FIG. 2, the processing system includes a plurality of GPU COREs (GPU COREs), a network on chip, a MMU corresponding to a DMA, a video encoder, a video decoder, a display controller, a memory controller, a PCIe controller, and an application processor.

Each GPU core is used for processing drawing commands, executing Pipeline of image rendering according to the drawing commands, and executing other operation commands; the multiple GPU cores as a whole perform drawing or other computing tasks.

The network on chip is used for data exchange between the various IP cores on the graphics processing system.

And the application processor is used for scheduling tasks of each module on the graphic processing system, for example, the GPU core informs the application processor after rendering a frame of image, and the application processor starts the display controller again to display the image drawn by the GPU on a screen.

And the display controller is used for controlling the frame buffer in the system memory to be output to a display through a display interface (HDMI, DP and the like).

And the MMU corresponding to the display controller is used for performing address translation on the access request of the display controller and realizing page table prefetching in cooperation with the display controller.

A general purpose DMA (Direct Memory Access ) for performing data movement between a host side to a graphics processing system memory (e.g., graphics card memory), such as moving vertex (vertex) data of a 3D drawing from the host side to the graphics processing system memory via DMA.

And the PCIe controller is used for communicating with the host computer, realizing PCIe protocol, enabling the graphics processing system to be connected to the host computer through the PCIe interface, and running programs such as graphics API, driver of the display card and the like on the host computer.

And the memory controller is used for connecting the system memory and storing data on the SOC.

Video decoding, the coded video on the host hard disk can be decoded into pictures that can be displayed.

The original video code stream on the hard disk of the host can be coded into a specified format and returned to the host.

Based on the graphics processing system shown in fig. 2, in one embodiment of the video display, the GPU core notifies the application processor after rendering a frame of image, and the application processor triggers the display controller to operate. The display controller, in response to a trigger by the application processor, sends a page table prefetch request to the corresponding MMU for page table prefetching. The MMU prefetches page tables from memory in the manner described in the previous embodiments. Then, the display controller sends out an image data reading request, and the MMU performs address translation on the reading request according to the prefetched page table, so as to obtain the image data to be displayed from the memory.

It should be noted that, only the specific structure shown in fig. 2 is taken as an example, and an implementation manner of the address translation module and the display controller in cooperation with implementing the on-demand prefetching of the page table according to the embodiment of the disclosure is described as an example. In practical applications, the scheme of prefetching page tables on demand provided in the embodiments of the present disclosure may also be applied to display processing systems with other structures, which will not be described herein.

Based on the same inventive concept, embodiments of the present disclosure also provide an electronic assembly comprising a processing system as described in any of the embodiments above. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, a television, or the like.

Based on the same inventive concept, the embodiments of the present disclosure also provide a graphic processing method including the operations of:

According to the page table prefetching method provided by the embodiment of the disclosure, the display controller sends out a page table prefetching request to trigger an address translation module (such as an MMU) to prefetch the page table. The address translation module is combined with a page table prefetching function and a multimedia display time sequence, prefetches the page table covering at least one row of address space to be displayed according to the display row size and the page table size, avoids page miss in the display process, improves the efficiency of page table prefetching, and effectively improves the efficiency of accessing the memory.

If the conventional page table prefetching mechanism is adopted, the page table prefetching can occur in the validity period of the digital image signal, and the page table prefetching is mixed with the reading operation of the digital image valid signal, so that the efficiency of reading the memory is reduced. And the display of the current frame is completed, and the page table prefetched during the display of the current frame can be invalid, belonging to invalid prefetching. According to the on-demand prefetch page table mechanism provided by the embodiment of the disclosure, prefetching occurs in a line blanking period and a field blanking period, reading of effective signals of digital images is not affected, on-demand prefetching is not carried out, and prefetching invalidation is not caused.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. An address translation module configured to:

and in response to the page table prefetching request, prefetching a page table corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal.

2. The address translation module of claim 1, the address translation module configured to: and receiving a page table prefetching request, wherein the page table prefetching request carries the address of at least one row of pixel data to be displayed, and prefetching the page table in the blanking period of the digital image signal according to the address.

3. The address translation module of claim 1, the address translation module configured to: and receiving a page table prefetching request, wherein the page table prefetching request carries a starting address of an image frame, and the page table is prefetched in a blanking period of a digital image signal according to the starting address and the address offset, wherein the address offset of at least one row of pixel data to be displayed in the image frame relative to the starting address of the image frame is obtained.

4. A address translation module according to any one of claims 1 to 3, the page table prefetch request being sent during a blanking period of a digital image signal.

5. The address translation module of any of claims 1 to 3, configured to: and prefetching a page table corresponding to the pixel data of the next row to be displayed in the blanking period of the digital image signal.

6. The address translation module of any of claims 1 to 3, further configured to: before a first image frame of multimedia is sent to display, a page table corresponding to at least a first row of pixel data of the first image frame is prefetched in response to a page table prefetch request.

7. A address translation module according to any one of claims 1 to 3, wherein for a multi-level page table, the page table corresponding to the at least one line of pixel data comprises at least a last-level page table corresponding to the at least one line of pixel data.

8. The address translation module of claim 7, the address translation module configured to: pre-fetching a last stage page table corresponding to at least one row of pixel data to be displayed in a row blanking period; and prefetching each stage of page table corresponding to at least one row of pixel data to be displayed in the vertical blanking period.

9. A display controller configured to:

and sending a page table prefetching request to an address translation module, so that the address translation module prefetches page tables corresponding to at least one row of pixel data to be displayed in a blanking period of the digital image signal in response to the page table prefetching request.

10. The display controller of claim 9, the page table prefetch request carrying an address of at least one row of pixel data to be displayed.

11. The display controller of claim 9, the page table prefetch request carrying a starting address of an image frame.

12. A display controller according to any one of claims 9 to 11, configured to send the page table prefetch request during a digital image signal blanking period.

13. A display controller according to any one of claims 9 to 11, wherein the page table prefetch request is sent before the first image frame of the multimedia is presented.

14. A display controller according to any one of claims 9 to 11, wherein for a multi-level page table, the page table for which the at least one line of pixel data corresponds comprises at least a last level page table for which the at least one line of pixel data corresponds.

15. A processing system comprising the address translation module of claims 1 to 8 and the display controller of any of claims 9 to 14.

16. An electronic assembly comprising the processing system of claim 15.

17. An electronic device comprising the electronic assembly of claim 16.

18. A page table prefetching method, comprising:

the display controller sends a page table prefetching request to the address translation module;

and the address translation module is used for responding to the page table prefetching request and prefetching page tables corresponding to at least one row of pixel data to be displayed in the blanking period of the digital image signal.

19. The method of claim 18, wherein the page table prefetch request carries an address of at least one row of pixel data to be displayed, and the address translation module, in response to the page table prefetch request, prefetches a page table corresponding to the at least one row of pixel data to be displayed during a blanking period of the digital image signal, comprising:

the address translation module prefetches the page table in the blanking period of the digital image signal according to the address.

20. The method of claim 18, wherein the page table prefetch request carries a start address of an image frame, and the address translation module, in response to the page table prefetch request, prefetches a page table corresponding to at least one line of pixel data to be displayed in a blanking period of a digital image signal, including:

the address translation module obtains the address offset of at least one row of pixel data to be displayed in the image frame relative to the starting address of the image frame, and prefetches the page table in the blanking period of the digital image signal according to the starting address and the address offset.

21. The method of any of claims 18 to 20, the display controller sending a page table prefetch request to an address translation module, comprising:

the display controller sends a page table prefetch request to the address translation module during a blanking period of the digital image signal.

22. The method of any of claims 18 to 20, the address translation module, in response to the page table prefetch request, prefetching a page table corresponding to at least one row of pixel data to be displayed during a digital image signal blanking period, comprising:

and the address translation module is used for responding to the page table prefetching request and prefetching a page table corresponding to the pixel data of the next line to be displayed in the blanking period of the digital image signal.

23. The method of any one of claims 18 to 20, further comprising:

the display controller sends a page table prefetching request to the address translation module before the first image frame of the multimedia is sent to display;

the address translation module is used for responding to a page table prefetching request and prefetching a page table corresponding to at least first row of pixel data of a first image frame of the multimedia before the first image frame is sent to display.

24. A method as claimed in any one of claims 18 to 20, wherein for a multi-level page table, the page table corresponding to the at least one row of pixel data comprises at least a last-level page table corresponding to the at least one row of pixel data.

25. The method of claim 24, wherein prefetching page tables corresponding to at least one row of pixel data to be displayed during a blanking period of the digital image signal, comprises: pre-fetching a last stage page table corresponding to at least one row of pixel data to be displayed in a row blanking period; and prefetching each stage of page table corresponding to at least one row of pixel data to be displayed in the vertical blanking period.