CN117851254A - MC/DC coverage use case generation method based on symbol execution and path number reduction - Google Patents
MC/DC coverage use case generation method based on symbol execution and path number reduction Download PDFInfo
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Abstract
The invention discloses an MC/DC coverage use case generation method based on symbol execution and path number reduction. Analyzing source codes of a program to be tested, and collecting each judgment expression to be covered and each condition in the judgment expression; secondly, inserting a pile into the source code, and modifying the source code of the judging statement to enable the program to record MC/DC coverage rate information in the executing process, wherein the executing logic is kept unchanged; then, performing static analysis on the program, and obtaining an reachable judgment set of each basic block of the program according to a program control flow diagram; and finally, performing symbol execution on the program after pile insertion, and merging and pruning paths of symbol execution according to coverage rate information and a static analysis result. The invention combines the static program analysis and the dynamic path merging method by inserting the program, reduces the number of paths by path merging and pruning in the symbol execution process, and aims to improve the generation speed of the test case and simplify the scale of the test case.
Description
Technical Field
The invention relates to the field of computer information processing and software engineering test automation, in particular to a test case generation method for reducing redundant cases to reduce the case scale based on MC/DC coverage rate, symbol execution and dynamic path number reduction in the symbol execution process.
Background
The software test is an important link for guaranteeing the quality and reliability of the software, and the vulnerability is found and repaired through the software test, so that the quality of the software is improved, and the software test becomes an indispensable important link in the software development process. Especially in important fields related to rail transit, aerospace and the like, complete unit testing is required to ensure high reliability and safety of software, and test cases are required to meet MC/DC (Modified Condition/Decision Coverage) coverage rate. MC/DC is an overlay criterion in software testing, typically used to ensure comprehensive testing for decision logic. Each condition in each decision expression is required to independently influence the decision result.
At present, a great deal of software testing work is still done manually. Writing test cases requires a lot of manpower and time investment, and especially aiming at complex standards such as MC/DC, the data meeting the coverage rate is very difficult to construct manually. Therefore, use case automatic generation techniques are widely studied. The symbol execution technology is a more common use case automatic generation method.
Symbol execution is a technique that uses a symbol variable instead of a specific value as a program input to run a program, where the symbol variable can represent a variable whose value is uncertain, and when encountering a program branch structure, an execution engine can derive multiple paths, each path respectively collects a corresponding path constraint, and the constraint solution is used to generate a value satisfying a condition for the symbol variable.
Symbol execution can explore various branching conditions and generate test cases meeting high coverage. However, for a program containing complex conditions, symbol execution is easy to explode, a large number of paths are generated, a large number of redundant test cases are generated aiming at MC/DC coverage rate standards, the generation rate is not ideal, and maintenance of the test cases is inconvenient.
Disclosure of Invention
Aiming at the problems of excessive redundant cases and easy path explosion in the test case generation process of the current method based on symbol execution, the invention provides a MC/DC coverage case generation method based on symbol execution and path number reduction.
The invention comprises the following steps:
s1, analyzing source codes of a program to be tested, and collecting each judgment expression to be covered and each condition in the judgment expression;
s2, inserting a source code, modifying the source code of the judging statement, so that MC/DC coverage rate information can be recorded in the execution process of the program, and the execution logic is kept unchanged;
s3, performing static analysis on the program operation, and obtaining an reachable judgment set of each basic block of the program according to a program control flow diagram;
s4, performing symbol execution on the program after pile insertion, merging and pruning paths of symbol execution according to coverage rate information and a static analysis result, reducing the number of paths and simplifying the scale of use cases.
The invention combines the static program analysis and the dynamic path merging method by inserting the program, reduces the number of paths by path merging and pruning in the symbol execution process, and aims to improve the generation speed of the test case and simplify the scale of the test case.
Drawings
FIG. 1 is a flowchart of a test case generation algorithm;
FIG. 2 is an example program and control flow diagram;
FIG. 3 is a control flow diagram before and after a decision statement instrumentation;
fig. 4 is a static analysis result of an example program.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
First, the concept involved in the present invention will be explained:
and (3) accessibility judgment: at a certain position of the program, a path reaching a certain judgment statement to be covered exists on the control flow graph, and the judgment statement is called as the reachable judgment of the program node.
True value sequence: for a certain predicate expression, the value of each conditional expression is called a truth sequence of the predicate.
Pruning paths: the path is executed for a symbol, its execution is aborted, and it is deleted from the pool of paths searched.
Path merging: different paths executed by symbols running to the same program position are combined into one path, and the state space (path constraint, variable value) contained in the combined path is the union of the state spaces of a plurality of original paths and contains all possible states and behaviors existing on the original paths. The path merging can reduce the number of paths for symbol execution exploration and the number of test cases.
The flow of test case generation is shown in FIG. 1. An example program and a program control flow diagram thereof are shown in fig. 2, wherein variables a to g are symbol variables, and the values are uncertain. For intuitiveness, the control flow graph incorporates basic blocks generated by various conditions within the predicate expression.
S1, analyzing source codes of a program to be tested to an abstract syntax tree, and collecting each judgment expression to be covered and each condition in the judgment expressions.
The Condition (Condition) in this embodiment refers to a portion of the logical expression that does not include an and, or, non-equal boolean operator. Decision (precision) refers to an expression where a plurality of conditions are combined with a nor operation.
In the C language, predicate and conditional expressions need to be extracted from If, for, while, do-while, switch and three-order operation statements. Analyzing the program to an abstract syntax tree, traversing the syntax tree from top to bottom, and collecting judgment sentences needing to be processed. For the example program, this step would collect the decisions in two if statements: (a & b & c & d) and (e & f & g). The first decision contains four conditions a, b, c, d and the second contains three conditions e, f, g.
S2, inserting the source codes of the judging sentences, and modifying the source codes of the judging sentences so that MC/DC coverage rate information can be recorded in the execution process of the program, and the execution logic is kept unchanged.
The instrumentation will introduce three stake functions:
INIT function: the number of the judgment is input, and the start of the program execution judgment statement is marked for initialization.
CHOOK function (Condition Hook): inputting the number of the conditional expression, and returning the true value of the expression.
DHOOK function (precision Hook): the number of the judgment expression is input, the judgment expression is returned to the true value of the judgment expression.
When the program runs to the judging statement, firstly, an INIT function is called, one bit vector is initialized, then a CHOOK function and a DHOOK function are called, and the bit vector is rewritten according to the conditions and the true value of the judging expression to obtain the coverage information.
Taking a judgment statement if (e & f|g) in a sample program as an example, after instrumentation processing, the code of the judgment statement is modified to if ((INIT (1), DHOOK (1, CHOOK (0, e) |CHOOK (1, f) |CHOOK (2, g))) wherein the INIT function marks the starting position of the judgment expression, the number starts from 0, the judgment is used as the second judgment, the numbers 1.CHOOK and DHOOK record the condition and the true value of the judgment expression respectively, and return the value of the input expression.
Further describing, in connection with the embodiments, the manner in which the program dynamically gathers coverage information: the control flows before and after the instrumentation of the decision statement (e & & f ||g) are shown in fig. 3. When the program runs to the judging statement, firstly calling the INIT function, initializing a bit vector BV with a fixed length to record a truth value sequence, initializing BV to 0, enabling binary digits of each two digits to correspond to the truth value of a condition, if the condition is true, assigning the binary digit to be 10, and if the condition is false, assigning the binary digit to be 01. If the condition is shorted, the corresponding bit is not rewritten, i.e., binary 00. Then, the program calls the CHOOK function every time the value of the condition is calculated, inputs the number of the condition, the conditional expression, and rewrites BV according to the above rule. After the judgment expression is calculated, a DHOOK function is called, the judgment number and the judgment expression value are input, if the judgment result is true, BV is at the highest position 1, and otherwise, 0 is set.
Specifically, for the determination expression e & & f ||g in the embodiment, assuming that e=0, f=1, g=1, the program calculates e as false by a key function, sets bits 1, 2 as binary 01, and shorts f, calculates the value of g as true, and sets bits 5, 6 as binary 10.BV gives a binary 10 00 01 value. Finally, the DHOOK function is called, and the highest bit of BV is set to 1 because the decision is true.
S3, performing static analysis on program operation, and analyzing and judging the execution accessibility relation of the statement according to the control flow diagram. The reachability determination set is the basis for path merging and pruning in step S4. The analysis is based on the following facts: the basic block B is also accessible to the decision statement that a certain subsequent basic block S of the basic block B may access.
Thus, the steps of static program analysis are as follows:
1. the definition IN [ B ], OUT [ B ] respectively represents the reachable judging sets at the entry and the exit of the basic block B, and the definition BR [ B ] represents the judging sequence number corresponding to a certain basic block of the program.
2. For any basic block B, IN [ B ] is initialized and OUT [ B ] is an empty set. If the basic block contains a call statement of the DHOOK function, the first parameter is the number of the decision expression. BR [ B ] is the number, otherwise BR [ B ] is null.
3. Starting from the exit basic block of the program, merging the IN sets of all the subsequent nodes of the basic block to obtain the OUT [ B ] set of the current basic block B. And merging OUT [ B ] with BR [ B ] to obtain IN [ B ] set. The rules of delivery are as follows.
OUT[B]＝∪ S IN[S]Successor node with S being B
IN[B]＝OUT[B]∪BR[B]
4. After a certain basic block B is processed, if P is not accessed or the IN and OUT sets of B are changed, the IN and OUT sets of the basic block P need to be processed according to the same rule. The above process is repeated until the IN and OUT sets of any basic block are not changed any more, and the static analysis is finished.
The static analysis described above was run on an example program, the results of which are shown in fig. 4. The basic block corresponding to the False branch of predicate 0, IN set to 1, indicates that there is a path on the control flow graph that enables the program to execute from the False branch of predicate 0 to predicate 1, so the reachable predicate of the False branch of predicate 0 is predicate 1. Further, true branch of predicate 0, any branch of predicate 1, may reach predicate set empty.
S4, performing symbol execution on the program after pile insertion, and dynamically merging and pruning paths of the symbol execution according to coverage rate information and static analysis results. On the premise of ensuring that the coverage rate is not reduced, the number of paths is reduced, the scale of the use case is simplified, the generation speed of the use case is increased, and the maintenance of the use case is facilitated.
When one path is executed to the decision statement, the symbol execution engine derives several paths, each exploring a different program branch. The derived paths are copies of the original paths, but with the addition of path constraints corresponding to the different branches, i.e., each path corresponds to a truth sequence of the predicate. The symbol execution engine stores the paths in a path pool and selects a path to continue execution. When the symbol execution engine selects a path derived from a certain decision expression from the path pool, there are the following cases:
case 1: the decision statement does not complete MC/DC coverage, and the truth sequence corresponding to the path does not cover other paths. The path is said to contribute to the determination of coverage, and execution of the path is continued.
Case 2: the truth sequence corresponding to the path has been accessed by the other paths. But satisfies any of the following conditions: 1. paths have contributed to coverage of one or more decisions during execution. 2. There is an uncovered decision among the reachable decisions of the path. All paths derived from this determination that meet the above conditions are merged.
Case 3: the path does not contribute coverage on accessed predicate statements and it can reach that the predicate has all completed MC/DC coverage. It is understood that the path must not increase coverage and may be terminated.
The program can calculate a truth sequence in the execution process through the instrumentation, and the symbol execution engine can monitor the MC/DC coverage rate achieved in the current exploration process and dynamically prune paths and merge paths according to coverage rate information and static analysis results.
Taking the execution flow of the example program as an example, for a determination, a truth sequence is recorded in the order in which conditions appear, with T representing true, F representing false, and X representing shorted. Possible values for the truth sequence of two decisions for the example procedure are shown in Table 1:
table 1 illustrates possible values of the program predicate statement truth sequence
If the use case is generated for the embodiment by adopting the naive symbol execution algorithm, the engine generates 7 paths at the decision 0, wherein 4 paths are executed to else if, namely the decision 1, and 4 paths are derived again for each path, so that 19 use cases are generated in total. Although 100% coverage of MC/DC is achieved, there are many redundancies in use cases. If the embodiment generating use case is adopted in the application, the flow is as follows:
scenario satisfying case 1: at the beginning of the symbol execution, the program creates an initial path to execute to decision 0. Since it is determined that MC/DC coverage is not complete at 0, the execution engine solves through constraint, solving 7 possible truth sequences: (TTXX, FXTT, TFTT, FXFX, TFTF, TFFX, FXTF) then 7 paths are derived to join the path pool. The engine takes a path out of the path pool to continue execution, which satisfies case 1 in step S4, since it is determined that the corresponding truth sequence is not covered. The symbol execution engine continues the path search, when a path first accesses decision 1 (fxfxx), decision 1 has 4 possible truth sequences (TTX, FXT, FXF, TFF), so the path derives 4 paths, and the truth sequences corresponding to each path are not covered, so case 1 is satisfied as well, and at this time decision 1 completes MC/DC coverage.
Scenario satisfying case 2: after decision 1 has completed coverage, another path derived from decision 0 is executed to decision 1. At this point decision 1 has completed MC/DC coverage, but this path contributes to decision 0 coverage to satisfy case 2 in step S4, so path merging is required. The 4 paths are derived and combined into 2 paths, and Block1 and Block2 are searched for.
Scenario satisfying case 3: when 5 paths (TTXX, FXFX, FXTT, FXTF, TFFX) derived from decision 0 are executed, and decision 0 completes MC/DC coverage, the symbol execution engine fetches the 6 th and 7 th paths derived from decision 0 from the path pool, and since decision 0 has completed coverage, these two paths do not contribute to coverage of decision 0, and subsequently reachable decision statements (decision 1) have also completed MC/DC coverage. Case 3 in step S4 is satisfied at this time. The MC/DC coverage rate of the two paths is not necessarily improved, and the engine performs path pruning and deletes the two paths.
The path constraints of the use cases generated by the method are shown in table 2. To increase intuitiveness, a truth sequence of decisions and a path constraint that the decision result represents the path collected in the decision statement are used, where T represents true, F represents false, and X represents an arbitrary value. Because the paths corresponding to use cases 7-10 are merged, the truth sequence can have multiple values, connected by an OR. When the use case is generated, the use case only needs to meet one possible value. The MC/DC Pair for each condition collected by the algorithm is shown in Table 3. The final algorithm realizes 100% coverage rate of MC/DC, and only 10 use cases are generated. The embodiment simplifies the use case scale generated by the symbol execution and reduces the redundant use cases when the symbol execution technology is used for generating the use cases meeting the MC/DC coverage rate.
TABLE 2 Path constraints for generating test cases
TABLE 3 MC/DC Pair for judging conditions of sentence
While the invention has been described with respect to the preferred embodiments, the scope of the invention is not limited thereto, and any changes or substitutions can be easily made by those skilled in the art within the scope of the present disclosure, which is also intended to be encompassed by the present invention.
Claims (7)
1. A method for generating MC/DC coverage cases based on symbol execution and path number reduction, characterized in that the method comprises the steps of:
s1, analyzing source codes of a program to be tested, and collecting each judgment expression to be covered and each condition in the judgment expression;
s2, inserting a source code, modifying the source code of the judging statement, so that MC/DC coverage rate information can be recorded in the execution process of the program, and the execution logic is kept unchanged;
s3, performing static analysis on the program operation, and obtaining an reachable judgment set of each basic block of the program according to a program control flow diagram;
s4, performing symbol execution on the program after pile insertion, merging and pruning paths of symbol execution according to coverage rate information and a static analysis result, reducing the number of paths and simplifying the scale of use cases.
2. The MC/DC coverage use case generation method based on symbol execution and path number reduction according to claim 1, characterized in that: the condition in step S1 means that the portion of the logical expression does not contain boolean operators; the determination refers to an expression in which a plurality of conditions are combined with a nor operation.
3. The MC/DC coverage use case generation method based on symbol execution and path number reduction according to claim 1, characterized in that: the pile-inserting process in step S2 introduces three pile functions:
INIT function: inputting a number of the judgment, marking the start of a program execution judgment statement, and initializing;
CHOOK function: inputting the number of the conditional expression, and returning the true value of the expression;
DHOOK function: the number of the judgment expression is input, the judgment expression is returned to the true value of the judgment expression.
4. A MC/DC coverage use case generation method based on symbol execution and path number reduction according to claim 3, characterized in that: when the program runs to the judging statement, firstly, an INIT function is called, one bit vector is initialized, then a CHOOK function and a DHOOK function are called, and the bit vector is rewritten according to the conditions and the true value of the judging expression to obtain the coverage information.
5. The MC/DC coverage use case generation method based on symbol execution and path number reduction according to claim 1, characterized in that: in step S4, when one path is executed to the judging statement, the symbol execution engine derives a plurality of paths to respectively explore different program branches; the symbol execution engine stores the paths in a path pool and selects a path to continue execution.
6. The MC/DC coverage use case generation method based on symbol execution and path number reduction according to claim 5, characterized in that: the derived paths are copies of the original paths, but with the addition of path constraints corresponding to the different branches, i.e., each path corresponds to a truth sequence of the predicate.
7. A method for generating MC/DC coverage cases based on symbol execution and path number reduction according to claim 5 or 6, characterized by: when the symbol execution engine selects a path derived from a certain decision expression from the path pool, there are three cases:
case 1: the judging statement does not complete MC/DC coverage, and the truth sequence corresponding to the path does not cover other paths, namely the path has coverage rate contribution to the judgment, and the path is continuously executed;
case 2: the truth sequence corresponding to the path has been accessed by other paths, but any of the following conditions is satisfied:
condition 1. Paths have contributed to coverage of one or some decisions during execution;
condition 2. There is uncovered decision in the reachable decision of the route;
merging all paths derived from the determination that satisfy the above condition;
case 3: the path has no coverage contribution on the accessed predicate statement and it can reach a decision that MC/DC coverage has been completed, the path is terminated.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150363305A1 (en) * | 2013-10-14 | 2015-12-17 | Xi'an Jiaotong University | Method for test case reduction based on program behavior slices |
| JP2016021163A (en) * | 2014-07-15 | 2016-02-04 | 富士通株式会社 | Test case generation program, test case generation method, and test case generation apparatus |
| JP2016115287A (en) * | 2014-12-17 | 2016-06-23 | 富士通株式会社 | Test case generation program, test case generation method and test case generator |
| US20210209008A1 (en) * | 2018-05-23 | 2021-07-08 | South China University Of Technology | Unit testing method based on automatic generation of path coverage test cases |
| CN114676035A (en) * | 2021-02-25 | 2022-06-28 | 北京新能源汽车股份有限公司 | Test case generation method and device and electronic equipment |
| KR20230053313A (en) * | 2021-10-14 | 2023-04-21 | 아피아엔지니어링(주) | System and method for automating software code coverage for artificial intelligence-based embedded |
| CN116541286A (en) * | 2023-05-09 | 2023-08-04 | 杭州金衡昇科技有限公司 | High coverage rate test data generation method based on pile insertion and symbol execution |
-
2024
- 2024-01-09 CN CN202410031065.6A patent/CN117851254A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150363305A1 (en) * | 2013-10-14 | 2015-12-17 | Xi'an Jiaotong University | Method for test case reduction based on program behavior slices |
| JP2016021163A (en) * | 2014-07-15 | 2016-02-04 | 富士通株式会社 | Test case generation program, test case generation method, and test case generation apparatus |
| JP2016115287A (en) * | 2014-12-17 | 2016-06-23 | 富士通株式会社 | Test case generation program, test case generation method and test case generator |
| US20210209008A1 (en) * | 2018-05-23 | 2021-07-08 | South China University Of Technology | Unit testing method based on automatic generation of path coverage test cases |
| CN114676035A (en) * | 2021-02-25 | 2022-06-28 | 北京新能源汽车股份有限公司 | Test case generation method and device and electronic equipment |
| KR20230053313A (en) * | 2021-10-14 | 2023-04-21 | 아피아엔지니어링(주) | System and method for automating software code coverage for artificial intelligence-based embedded |
| CN116541286A (en) * | 2023-05-09 | 2023-08-04 | 杭州金衡昇科技有限公司 | High coverage rate test data generation method based on pile insertion and symbol execution |
Non-Patent Citations (2)
| Title |
|---|
| CHEN小M: "软件测试-修正判定条件覆盖（MCDC）的一些认识", pages 1 - 5, Retrieved from the Internet <URL:https://www.cnblogs.com/ChenM666/p/16137844.html> * |
| 谭莉娟等: "面向适航标准的机载软件测试验证方法综述", 《计算机工程与应用》, 31 December 2021 (2021-12-31), pages 1 - 14 * |
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