CN117851070B - Computing chip architecture and computing method applied to detection task - Google Patents
Computing chip architecture and computing method applied to detection task Download PDFInfo
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Abstract
The application relates to a computing chip architecture and a computing method applied to detection tasks. Wherein, the chip architecture includes: the plurality of minimum reconstruction processing modules each comprise: the device comprises a control unit, a calculation unit and a storage unit; the control module is used for allocating a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module so as to execute calculation tasks with different granularities, receiving upper-layer information and generating calculation task aggregation requirements, calling the corresponding-level aggregation reconstruction processing module based on the calculation task aggregation requirements, and carrying out corresponding calculation task allocation and calculation in the aggregation reconstruction processing module, wherein the calculation tasks comprise artificial intelligent calculation and/or communication calculation. The novel chip architecture provided by the application has a more flexible reconfigurable multi-layer mapping mechanism of the computing task, and finally realizes a high-efficiency reconfigurable post-computation integrated chip.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a computing chip architecture and a method applied to a detection task.
Background
In the traditional computing chip application scene, the artificial neural network computation and the communication algorithm computation are often two relatively independent modules and functions, so that two mutually independent chip modules are required to be configured on a hardware terminal which needs the artificial neural network computation and the signal processing computation, the terminal has larger size and higher power consumption, and the terminal cannot be well suitable for flexible application of multiple scenes.
With further development and fusion of technology, in some specific application scenarios, the artificial neural network calculation and the signal processing function need to be fused deeply, so as to further improve the chip calculation performance and the application scenarios. Therefore, how to further promote the fusion and collaboration capabilities of chip artificial intelligence computing and communication computing becomes an important challenge for the design of a novel computing chip architecture.
Disclosure of Invention
To overcome the problems in the related art, embodiments of the present invention provide a computing chip architecture and method for detecting tasks. The technical proposal is as follows:
According to a first aspect of embodiments of the present invention, there is provided a computing chip architecture for detection tasks, comprising:
the plurality of minimum reconstruction processing modules each comprise: the device comprises a control unit, a calculation unit and a storage unit;
The control module is used for allocating a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module so as to execute calculation tasks with different granularities, receiving upper-layer information and generating calculation task aggregation requirements, calling the corresponding-level aggregation reconstruction processing module based on the calculation task aggregation requirements, and carrying out corresponding calculation task allocation and calculation in the aggregation reconstruction processing module, wherein the calculation tasks comprise artificial intelligent calculation and/or communication calculation.
In an embodiment of the application, the control module is further configured to: and allocating the plurality of minimum reconstruction processing modules to form a plurality of aggregation reconstruction processing modules of the same and/or different levels at the same time so that the multi-tasks are executed in parallel through the aggregation reconstruction processing modules of different aggregation granularities.
In an embodiment of the application, the control module is further configured to: and in the execution process of the computing task, dynamically adjusting the aggregation level of the aggregation reconstruction processing module according to the computing process.
In an embodiment of the present application, the control unit in the aggregate reconstruction processing module is further configured to: and recognizing the error rate and the calculation power distribution of the current aggregation reconfiguration processing module, actively and spontaneously carrying out calculation resource distribution adjustment, and informing the adjustment result to the control module.
In an embodiment of the present application, a control unit in an aggregate reconstruction processing module actively and spontaneously performs computing resource allocation adjustment, including: if the current calculation task is smaller than the aggregation reconfiguration calculation unit for calculation and distribution, the aggregation reconfiguration calculation unit releases the redundant reconfiguration calculation unit and informs the release result to the control module; if the current calculation task is larger than the calculation-allocated aggregation reconfiguration calculation unit, the aggregation reconfiguration calculation unit adds the missing minimum reconfiguration processing module from the remaining minimum reconfiguration processing modules, and informs the control module of the addition result.
According to a second aspect of the embodiments of the present invention, there is provided a computing method of a computing chip applied to a detection task, applied to the above-mentioned chip architecture, including:
Before executing a calculation task, the control module allocates a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module;
when the control module executes a computing task, receiving upper-layer information and generating a computing task aggregation requirement;
The control module calls an aggregation reconstruction processing module of a corresponding level based on the calculation task aggregation requirement, and performs corresponding calculation task allocation and calculation in the aggregation reconstruction processing module; the computing tasks include artificial intelligence computing and/or communication computing.
In an embodiment of the present application, the method further includes: and the control module dynamically adjusts the aggregation level of the aggregation reconstruction processing module according to the calculation process in the calculation task execution process.
In an embodiment of the present application, the method further includes: the control unit in the aggregation reconfiguration processing module recognizes the error rate and the calculation power distribution of the current aggregation reconfiguration processing module, actively and spontaneously adjusts the calculation resource distribution, and informs the control module of the adjustment result.
In an embodiment of the present application, a control unit in an aggregate reconstruction processing module actively and spontaneously performs computing resource allocation adjustment, including: if the current calculation task is smaller than the aggregation reconfiguration calculation unit for calculation and distribution, the aggregation reconfiguration calculation unit releases the redundant reconfiguration calculation unit and informs the release result to the control module; if the current calculation task is larger than the calculation-allocated aggregation reconfiguration calculation unit, the aggregation reconfiguration calculation unit adds the missing minimum reconfiguration processing module from the remaining minimum reconfiguration processing modules, and informs the control module of the addition result.
According to the technical scheme provided by the embodiment of the invention, the plurality of minimum reconstruction processing modules can form a multi-level aggregation reconstruction processing module under the allocation of the top-level control module, the aggregation reconstruction processing module can respectively execute calculation tasks with different granularities according to different artificial intelligence and signal processing applications, and the different aggregation reconstruction processing modules bear the calculation tasks with different complexity degrees, so that the multi-layer mapping mechanism is a more flexible calculation task reconfigurable multi-layer mapping mechanism, and finally, a high-efficiency reconfigurable post-calculation integrated chip is realized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram illustrating a computing chip architecture applied to a detection task, according to an example embodiment.
FIG. 2 is a flowchart illustrating a computing method of a computing chip applied to a detection task, according to an example embodiment.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as detailed in the accompanying claims.
The embodiment of the application provides a novel chip architecture, and constructs a multi-level computing unit reconstruction aggregation mechanism. As illustrated in fig. 1, the computing chip architecture for detection tasks includes:
A plurality of minimum reconstruction processing modules 101, each of which includes: the device comprises a control unit, a calculation unit and a storage unit;
The control module 102 is configured to allocate a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module to execute computing tasks with different granularities, receive upper-layer information and generate computing task aggregation requirements, call the corresponding-level aggregation reconstruction processing module based on the computing task aggregation requirements, and perform corresponding computing task allocation and computation inside the aggregation reconstruction processing module, where the computing tasks include artificial intelligent computing and/or communication computing.
The minimum reconstruction processing module itself supports the reconstruction calculation of multiple operations, that is, the control unit can complete the reconstruction implementation of the artificial intelligence algorithm and the communication algorithm through the scheduling calculation unit and the storage unit, and the multiple minimum reconstruction processing modules can form a multi-level aggregation reconstruction processing module with multiple specifications under the allocation of the top-level control module, as shown in fig. 1, the M minimum reconstruction processing modules can form an aggregation reconstruction processing module A1, and the N minimum reconstruction processing modules can form an aggregation reconstruction processing module A2. The aggregation reconfiguration processing module can respectively execute calculation tasks with different granularities according to different artificial intelligence and signal processing applications, and different aggregation reconfiguration processing modules bear calculation tasks with different complexity degrees, so that the aggregation reconfiguration processing module is a more flexible calculation task reconfigurable multi-layer mapping mechanism, and finally a high-efficiency reconfigurable post-calculation integrated chip is realized.
In an embodiment of the application, the control module is further configured to: and allocating the plurality of minimum reconstruction processing modules to form a plurality of aggregation reconstruction processing modules of the same and/or different levels at the same time so that the multi-tasks are executed in parallel through the aggregation reconstruction processing modules of different aggregation granularities.
In this embodiment, parallel execution of multiple tasks with different aggregation granularities is supported, and a function of synchronously performing computation by multiple tasks according to different aggregation settings is realized. Since the types and sizes of the tasks may be different, the aggregate reconfiguration processing modules of the tasks may have different granularities. The invention supports the combination of aggregation reconfiguration processing modules with various granularities to form aggregation reconfiguration processing modules with different forms so as to be respectively applicable to different artificial intelligence calculation models or signal processing calculation algorithms and support diversified artificial intelligence application and signal processing application.
In an embodiment of the application, the control module is further configured to: and in the execution process of the computing task, dynamically adjusting the aggregation level of the aggregation reconstruction processing module according to the computing process.
In this embodiment, the computing process supporting the minimum aggregation reconfiguration processing module with different dimensions is dynamically and flexibly aggregated, so as to implement adjustment of different aggregation granularities in the executing process of the computing task. In order to improve the flexibility of calculation, the invention supports the adjustment of the aggregation degree and performance of the self-aggregation reconstruction processing module in the calculation process of the chip. The dynamic adjustment means that aggregation levels and aggregation reconstruction processing modules adopted by the same computing task at different computing times are different. For artificial intelligence, different aggregation degrees correspond to different artificial neural network mappings and different operator implementations, the network itself has dynamic adjustment and dynamic clipping characteristics in the calculation process, and the dynamic aggregation of the invention can well support dynamic modification in the calculation process of the artificial neural network. For signal processing, different aggregation levels may correspond to different signal resources to perform different numbers of corresponding scrambling and decoding, channel coding and decoding, source coding and decoding, resource mapping, demapping, FFT/IFFT (Fast Fourier Transform/INVERSE FAST Fourier Transform ), MIMO (Multiple-Input Multiple-Output), and other computing operations, where different signal resources include REs (Resource elements), REGs (Resource Element Group, resource particle groups), RBs (Resource blocks), PRBs (Physical Resource Block, physical Resource blocks), BWP (Band WIDTH PART ), BW (Band Width), so as to support different related operations in the signal processing system, so that different computing amounts perform closed loop computation inside the aggregation reconfiguration processing module, and reduce information interaction between the aggregation reconfiguration processing modules. The dynamic adjustment in the calculation process can effectively realize the optimal allocation of the calculation tasks and the more flexible calculation.
In an embodiment of the present application, the control unit in the aggregate reconstruction processing module is further configured to: and recognizing the error rate and the calculation power distribution of the current aggregation reconfiguration processing module, actively and spontaneously carrying out calculation resource distribution adjustment, and informing the adjustment result to the control module.
The error rate is obtained by comparing all or part of the calculated result with the preset result by the control unit, wherein the difference is error, and the difference rate is error rate. The autonomous, i.e. adjusted, computing resource allocation operation is initiated by the control unit, and not by instruction mobilization of the control module.
In an embodiment of the present application, a control unit in an aggregate reconstruction processing module actively and spontaneously performs computing resource allocation adjustment, including: if the current calculation task is smaller than the aggregation reconfiguration calculation unit for calculation and distribution, the aggregation reconfiguration calculation unit releases the redundant reconfiguration calculation unit and informs the release result to the control module; if the current calculation task is larger than the calculation-allocated aggregation reconfiguration calculation unit, the aggregation reconfiguration calculation unit adds the missing minimum reconfiguration processing module from the remaining minimum reconfiguration processing modules, and informs the control module of the addition result.
The embodiment supports spontaneous dynamic aggregation adjustment, and achieves the functions of spontaneous feedback and integral calculation adjustment of an aggregation reconstruction processing module according to calculation conditions. Because the control module is arranged in the aggregation reconfiguration processing module, the error rate and the calculation power distribution of the current aggregation reconfiguration processing module can be identified, calculation resource distribution adjustment is actively and spontaneously carried out, and the adjustment result is informed to the control module, so that the chip master control can carry out more accurate follow-up mobilization.
The embodiment of the invention also provides a computing method of the computing chip applied to the detection task, which is applied to the computing chip architecture applied to the detection task, as shown in fig. 2, and comprises the following steps of S201-S203:
In step S201, the control module deploys a plurality of minimum reconstruction processing modules to form a multi-level aggregate reconstruction processing module before executing the computing task.
In step S202, the control module receives upper layer information and generates a computing task aggregate requirement when executing a computing task.
In step S203, the control module invokes the aggregation reconfiguration processing module of the corresponding hierarchy based on the calculation task aggregation requirement, and performs corresponding calculation task allocation and calculation inside the aggregation reconfiguration processing module; the computing tasks include artificial intelligence computing and/or communication computing.
In an embodiment of the present application, the method further includes step a:
step A: and the control module dynamically adjusts the aggregation level of the aggregation reconstruction processing module according to the calculation process in the calculation task execution process.
In an embodiment of the present application, the method further includes step B:
And (B) step (B): the control unit in the aggregation reconfiguration processing module recognizes the error rate and the calculation power distribution of the current aggregation reconfiguration processing module, actively and spontaneously adjusts the calculation resource distribution, and informs the control module of the adjustment result.
In an embodiment of the present application, a control unit in an aggregate reconstruction processing module actively and spontaneously performs computing resource allocation adjustment, including: if the current calculation task is smaller than the aggregation reconfiguration calculation unit for calculation and distribution, the aggregation reconfiguration calculation unit releases the redundant reconfiguration calculation unit and informs the release result to the control module; if the current calculation task is larger than the calculation-allocated aggregation reconfiguration calculation unit, the aggregation reconfiguration calculation unit adds the missing minimum reconfiguration processing module from the remaining minimum reconfiguration processing modules, and informs the control module of the addition result.
The implementation is described in detail below by way of examples.
The following is a calculation method of a calculation chip applied to a detection task according to an exemplary embodiment, the method including the steps of:
In step S301, a multi-level reconstruction processing module is disposed in a computing chip applied to a detection task, and a control unit, a computing unit and a storage unit are included in a minimum reconstruction processing module, where the computing unit itself supports reconfigurable computation of multiple operations, and thus, the reconstruction implementation of an artificial intelligence algorithm and a communication algorithm can be completed. The modules and arrays are in an idle state before the chip performs the computational tasks.
In step S302, before the computing chip applied to the detection task performs computation, the multiple minimum reconstruction computing units may form a multi-level aggregate reconstruction processing module under the allocation of the top control module, where the aggregate reconstruction processing module may perform computing tasks with different granularity according to different artificial intelligence and signal processing applications, and the different aggregate reconstruction processing modules bear computing tasks with different complexity. The aggregation degree of the aggregation reconfiguration processing module needs to be determined and solidified before calculation by the control module, and configuration adjustment is not needed in the execution process of the calculation task, so that a single calculation task can be efficiently completed.
In step S303, when the computing chip applied to the detection task starts to execute the computing task, the control module converts the upper layer information into an aggregate demand, schedules the aggregate reconstruction processing modules of different levels, and performs corresponding task allocation and computation inside the respective aggregate reconstruction processing modules. Related tasks include artificial intelligence computing tasks and/or signal processing computing tasks.
The scheme supports parallel execution of different aggregation granularities of the multitasks, and realizes the function of synchronously carrying out calculation according to different aggregation settings of the multitasks. The scheme supports parallel operation of multiple tasks, and the aggregated reconstruction processing modules have different granularities because the types and the sizes of the tasks may be different.
In step S304, during the execution of the computing task, the computing process of the aggregate reconstruction processing module dynamically and flexibly aggregates, so as to adjust different aggregate granularities during the execution of the computing task, so as to adapt to the computing requirement of the real task, so that different computing quantities perform closed-loop computation inside the aggregate reconstruction processing module, and reduce the information interaction between the aggregate reconstruction processing modules. The dynamic adjustment in the calculation process can effectively realize the optimal allocation of the calculation tasks and the more flexible calculation.
In step S305, spontaneous dynamic aggregation adjustment is implemented to implement the function of spontaneous feedback and overall adjustment calculation by the aggregation reconfiguration processing module according to the calculation condition. Because the aggregation reconfiguration processing module is internally provided with the control unit, the control unit can identify the error rate and calculation power distribution of the current module, actively and spontaneously perform calculation resource distribution adjustment, and inform the control module of an adjustment result, so that the chip master control can perform more accurate follow-up adjustment.
In step S306, after the chip calculation task is completed, the calculation is exited, the data of each module is emptied, and the final result and the output completion indication are output.
The module reconfigurable computing integrated chip architecture and the method provided by the invention construct a multi-level computing unit reconfiguration aggregation mechanism, realize the dynamic and flexible aggregation working modes of the computing process of the reconfiguration processing module with different dimensions, realize the adjustment of different aggregation granularities in the execution process of computing tasks, and also have a spontaneous dynamic aggregation adjustment mechanism to realize the functions of spontaneous feedback and integral calculation adjustment of the reconfiguration processing module according to the computing condition; and the function of synchronously performing the calculation of the multitasking according to different aggregation settings is realized.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (5)
1. A computing chip architecture for detection tasks, comprising:
the plurality of minimum reconstruction processing modules each comprise: the device comprises a control unit, a calculation unit and a storage unit;
The control module is used for allocating a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module so as to execute calculation tasks with different granularities, receiving upper-layer information and generating calculation task aggregation requirements, calling the corresponding-level aggregation reconstruction processing module based on the calculation task aggregation requirements, and carrying out corresponding calculation task allocation and calculation in the aggregation reconstruction processing module, wherein the calculation tasks comprise artificial intelligent calculation and/or communication calculation;
The control unit in the aggregate reconstruction processing module is further configured to: the error rate and calculation power distribution of the current aggregation reconstruction processing module are identified, calculation resource distribution adjustment is actively and spontaneously carried out, and an adjustment result is informed to a control module;
The control unit in the aggregation reconfiguration processing module actively and spontaneously performs calculation resource allocation adjustment, which comprises the following steps: if the current calculation task is smaller than the aggregation reconstruction calculation unit for calculation and distribution, releasing the redundant reconstruction calculation unit, and informing a release result to a control module; if the current calculation task is larger than the calculation distribution aggregation reconstruction calculation unit, adding the missing minimum reconstruction processing module from the rest minimum reconstruction processing modules, and informing the addition result to the control module.
2. The chip architecture of claim 1, wherein the control module is further configured to: and allocating the plurality of minimum reconstruction processing modules to form a plurality of aggregation reconstruction processing modules of the same and/or different levels at the same time so that the multi-tasks are executed in parallel through the aggregation reconstruction processing modules of different aggregation granularities.
3. The chip architecture of claim 1, wherein the control module is further configured to: and in the execution process of the computing task, dynamically adjusting the aggregation level of the aggregation reconstruction processing module according to the computing process.
4. A computing method of a computing chip applied to a detection task, applied to the chip architecture of any one of claims 1 to 3, characterized in that the method comprises:
Before executing a calculation task, the control module allocates a plurality of minimum reconstruction processing modules to form a multi-level aggregation reconstruction processing module;
when the control module executes a computing task, receiving upper-layer information and generating a computing task aggregation requirement;
The control module calls an aggregation reconstruction processing module of a corresponding level based on the calculation task aggregation requirement, and performs corresponding calculation task allocation and calculation in the aggregation reconstruction processing module; the computing tasks include artificial intelligence computing and/or communication computing;
The control unit in the aggregation reconfiguration processing module recognizes the error rate and the calculation power distribution of the current aggregation reconfiguration processing module, actively and spontaneously adjusts the calculation resource distribution, and informs the adjustment result to the control module;
The control unit in the aggregation reconfiguration processing module actively and spontaneously performs calculation resource allocation adjustment, which comprises the following steps: if the current calculation task is smaller than the aggregation reconstruction calculation unit for calculation and distribution, releasing the redundant reconstruction calculation unit, and informing a release result to a control module; if the current calculation task is larger than the calculation distribution aggregation reconstruction calculation unit, adding the missing minimum reconstruction processing module from the rest minimum reconstruction processing modules, and informing the addition result to the control module.
5. The method according to claim 4, wherein the method further comprises:
And the control module dynamically adjusts the aggregation level of the aggregation reconstruction processing module according to the calculation process in the calculation task execution process.
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| CN112463709A (en) * | 2019-09-09 | 2021-03-09 | 上海登临科技有限公司 | Configurable heterogeneous artificial intelligence processor |
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