CN117850923A - State machine simulation method for complex system - Google Patents
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Abstract
The invention discloses a state machine simulation method for a complex system, which comprises the following steps: s1, constructing a system state machine diagram based on a SysML state machine primitive model; s2, developing behavior codes; s3, simulating and compiling by a state machine; s4, simulation configuration; s5, simulation execution; s6, obtaining a simulation result; s7, verifying the model to complete simulation. The invention can describe and develop the system behavior code aiming at the specific field, and can develop the system behavior code on the basis of the template by importing the existing behavior code template, thereby reducing the workload.
Description
Technical Field
The invention belongs to the technical field of simulation, and particularly relates to a state machine simulation method for a complex system.
Background
With the rapid development of new generation information technologies such as the Internet of things, cloud computing, big data, digital twinning and the like and artificial intelligence technologies, continuous fusion and landing application of the new generation information technologies and the artificial intelligence technologies with the manufacturing industry, transformation and upgrading to intelligent manufacturing have become the necessary trend of the development of the manufacturing industry. MBSE supports normalized modeling applications that start with a conceptual design phase and continue throughout the system requirements, design, analysis, validation, and validation activities of the development and later lifecycle phases.
Based on the behavior definition in the system, the state of the behavior needed to be contained in the behavior and the changed model of the whole system after the completion, the state machine simulation is carried out to obtain a simulation result, so that the simulation result is evaluated and verified according to the simulation information obtained by the simulation, and the system model is verified and confirmed.
The existing method is based on SysML, UML, UPDM and other graphical modeling language specifications, and model elements in each language specification behavior diagram are defined, so that when behavior modeling is carried out by using a corresponding graphical language, state machine simulation can be directly carried out on the constructed behavior diagram. However, for specific fields, when the system behavior description is performed, the graphical model element behaviors of the generalized modeling language cannot be effectively expanded, so that the problems of low modeling efficiency, poor expandability, low flexibility and the like exist.
Disclosure of Invention
Aiming at the problems that the behavior of the existing graphical modeling language element cannot be expanded for a specific field and the described behavior element codes cannot be stored and reused, the invention provides a state machine simulation method for a complex system.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
a state machine simulation method for a complex system comprises the following steps:
s1, constructing a system state machine diagram based on a SysML state machine primitive model;
s2, developing behavior codes;
s3, simulating and compiling by a state machine;
s4, simulation configuration;
s5, simulation execution;
s6, obtaining a simulation result;
s7, verifying the model to complete simulation.
Further, constructing a system state machine diagram based on the SysML graphical modeling language specification, and describing system behaviors by state-to-state conversion;
the system state machine diagram includes elements of:
area: the state machine comprises one or more regions that collectively describe state-related behavior of the state machine, and initialization and completion of one region is described using an initial pseudo-state and a final state, respectively;
status: the states are represented by a rounded rectangle representing important conditions, representing changes in response to events and changes in execution behavior, each state may contain the respective execution of ingress and egress behavior upon entering and exiting the state;
conversion: transitions dictate when state changes are developed in the state machine.
Further, developing behavior codes by combining the development behavior codes with a graphical model, selecting a certain state machine model element, then developing the behavior codes, and storing the behavior codes into a system state machine model file;
the developed code type description includes:
region code development: the developed region behavior code may contain one region behavior code or a plurality of region behavior codes;
developing state codes: simple state code development includes defining whether a state is initialized or not and equation setting at the time of the state, and group code development includes attribute code development and function code development;
development of conversion codes: including event code development, condition code development, assignment code development, and state jump code development;
SVG code development: including SVG file binding code development and basic property code development.
Further, the state machine simulation compiling is to compile the developed codes to form CIF codes used by a CIF solver;
the state machine simulation compiling comprises single-region compiling and multi-region compiling;
single region compilation: compiling behavior codes in a state machine model file of a region to form a single-region CIF code file for a CIF solver;
multi-region compilation: firstly defining the names of multi-region CIF code files, then respectively compiling the behavior codes in the state machine model files of the multiple regions in a single region, and merging the obtained single-region CIF code files to form a multi-region CIF code file for a CIF solver.
Further, the simulation configuration is a series of configuration needed before the simulation is executed, so that the simulation is set;
the simulation configuration comprises input mode setting, simulation setting, compiling setting, input setting, output setting and ODE solver setting;
input mode setting: including error, warning, normal, and debug options;
simulation setting: the method comprises the steps of simulation file format setting, simulation format initialization setting, simulation ending time setting, maximum delay setting, random distribution initial seed setting, complete mode setting, external function asynchronous execution setting, analysis setting, request confirmation simulator termination setting, maximum time tolerance setting and loading debugging code setting;
compiling and setting: the method comprises the steps of compiling only settings, compiling code file settings and Java compiler settings;
input settings: the method comprises the steps of setting an input mode, setting an automatic mode selection algorithm, setting an automatic mode time conversion duration, setting a tracking input file, setting an interactive mode automatic conversion selection, setting an environmental event, setting a history and setting a history capacity;
output setting: the method comprises the steps of general output setting, SVG visual setting, track data setting, graph visual setting and state visual setting;
ODE solver settings: the method comprises the steps of setting a fixed output step length of an ODE solver, setting an ODE integrator, setting an ODE root finder and the like.
Further, the simulation execution is to call a CIF solver to perform state machine simulation after the simulation configuration is completed;
there are two cases of simulation execution: simulation execution success and simulation execution failure;
simulation execution succeeds: if the simulation is successfully executed, outputting simulation process information on a control console and a state visualization corresponding window according to simulation configuration;
simulation execution fails: if the simulation execution fails, an error is output, after the developed behavior code is required to be modified based on the output error, the simulation compiling and the simulation configuration steps of the state machine are carried out, and then the simulation execution is carried out.
Further, the simulation result is mainly obtained by checking corresponding output information when the simulation is executed and storing simulation data after the simulation is finished, and the obtained simulation result is used for verifying the model.
Further, the verification model is based on the obtained simulation result and the system demand and functional model for comparison verification; if the verification model is correct, the simulation is ended, if the verification model is wrong, the error source is searched, the system state machine diagram is possibly modified according to actual conditions, and then development behavior codes, state machine simulation compiling and simulation configuration operations are executed.
Compared with the prior art, the invention has the following beneficial effects:
the system engineering based on the model describes the system behavior in a model mode, and develops a system behavior code on the basis of the system behavior code to simulate a state machine. Therefore, early in the development and design of the system, system designers are helped to find out design defects, so that the system design cost is reduced, the development period is shortened, and the reliability of the system is improved.
The system behavior description and the development of the system behavior code can be performed aiming at a specific field, and meanwhile, the system behavior code can be developed on the basis of the existing behavior code template by importing the template, so that the workload is reduced.
Drawings
FIG. 1 is a flow chart of a state machine simulation method for a complex system in an embodiment of the invention;
FIG. 2 is a flow chart of multi-region compiling in an embodiment of the invention.
Detailed Description
The invention will be further described with reference to examples and drawings, to which reference is made, but which are not intended to limit the scope of the invention.
As shown in fig. 1, the present embodiment provides a state machine simulation method for a complex system, including the steps of: s1, constructing a system state machine diagram based on a SysML state machine primitive model; s2, developing behavior codes; s3, simulating and compiling by a state machine; s4, simulation configuration; s5, simulation execution; s6, obtaining a simulation result; s7, verifying the model to complete simulation.
SysML is a generic graphical modeling language for describing, analyzing, designing and verifying complex systems that contain hardware, software, equipment, personnel and information that provides a semantic basis for graphically representing modeling system requirements, behaviors, structures and parameters. In SysML, a state machine is typically used to describe the behavior of a block in dependence upon states throughout its lifecycle, the state machine being defined by states and transitions between states.
The behavior of a state machine is specified by a set of regions, each region containing its own state. The state within any one region is unique, i.e., when a region is activated, one of the sub-states is activated, the region typically has an initial state, which is where the region begins to execute when it is first activated. When a state is entered, an entry behavior is performed. Similarly, optional exit behavior is performed when the state is pushed out. In the state, the state machine may perform an action. An area is also typically indicated by a final state indicating that the area has been completed. The state change is achieved by a transition from the connection source state to the target state. The transition is defined by triggers, daemons and effects. The trigger represents an event that may cause a transition from the source state; evaluating daemons to test whether the conversion is valid; the effect is an action performed after the transition is triggered. The trigger may be based on various events such as expiration of a timer or receipt of a signal issued by an owning object of the state machine.
The system behavior can be described only by performing a large amount of state definitions when describing a specific field, and the behavior codes of model elements cannot be checked and simultaneously acquired and multiplexed when aiming at the specific field.
Constructing a system state machine diagram based on the SysML graphical modeling language specification, and describing system behaviors by state-to-state conversion;
the system state machine diagram includes elements of:
area: the state machine comprises one or more regions that collectively describe state-related behavior of the state machine, and initialization and completion of one region is described using an initial pseudo-state and a final state, respectively; the initial state is an initial state used to determine the region, and transitions from the initial state may include an effect. Such effects are typically used to set the initial value of the state machine usage attribute. When the active state of the region is the final manuscript state, the region is terminated and no more conversion occurs inside it.
Status: the states are represented by a rounded rectangle representing important conditions, representing changes in response to events and changes in execution behavior, each state may contain the respective execution of ingress and egress behavior upon entering and exiting the state; furthermore, when the entry behavior is complete, the state may contain an execution behavior. The execution behavior will continue execution until it is complete or the state exits.
Conversion: transitions dictate when state changes are developed in the state machine. Once the transition is made, the state machines always run to completion, meaning that they cannot consume another trigger event before the state machines complete the processing of the current event. One transition may include one or more triggers, daemons, and effects.
Development behavior code is primarily the behavior that defines the state machine diagram of the system for state machine simulation. The simulation solver used in the invention is a CIF solver, so the developed behavior code is a CIF code. The state machine behavior codes of the present invention are mainly development region codes, state codes, conversion codes and SVG codes.
Developing behavior codes in a mode of combining the graphical model, selecting a certain state machine model element, then developing the behavior codes, and storing the behavior codes into a system state machine model file; the development behavior code can be imported into the existing behavior code template, so that the workload is reduced by developing the behavior code on the basis, the behavior code can be developed from scratch, the development can be completed, and the development can be saved, so that the behavior code can be developed and multiplexed for different scenes.
The developed code type description includes:
region code development: the developed region behavior code may contain one region behavior code or a plurality of region behavior codes; mainly comprises event code development and parameter code development.
Developing state codes: simple state code development includes defining whether a state is initialized or not and equation setting at the time of the state, and group code development includes attribute code development and function code development;
development of conversion codes: including event code development, condition code development, assignment code development, and state jump code development;
SVG code development: including SVG file binding code development and basic property code development.
The state machine simulation compiling is to compile the developed codes to form CIF codes used by a CIF solver;
the state machine simulation compiling comprises single-region compiling and multi-region compiling;
single region compilation: compiling behavior codes in a state machine model file of a region to form a single-region CIF code file for a CIF solver;
as shown in fig. 2, multi-region compilation: firstly defining the names of multi-region CIF code files, then respectively compiling the behavior codes in the state machine model files of the multiple regions in a single region, and merging the obtained single-region CIF code files to form a multi-region CIF code file for a CIF solver.
The simulation configuration is a series of configuration needed before the simulation is executed, so that the simulation is set;
the simulation configuration comprises input mode setting, simulation setting, compiling setting, input setting, output setting and ODE solver setting;
input mode setting: including error, warning, normal, and debug options;
1) Errors: only the erroneous output is generated. It is recommended not to use this mode. The alert mode may be changed if it is desired to limit console output.
2) Warning: an error and warning output is generated. Using this mode, potential problems can be notified while keeping console output to a minimum.
3) Normal: error, warning and normal outputs are generated, being the default output mode. The information printed to the console for normal output may be configured using normal output options.
4) Debugging: error, alert, normal, and debug outputs are generated. This mode may be used to print other debug information to the console. The "debug output" option may be used to configure information printed to the console for normal output.
Simulation setting: the method comprises the steps of simulation file format setting, simulation format initialization setting, simulation ending time setting, maximum delay setting, random distribution initial seed setting, complete mode setting, external function asynchronous execution setting, analysis setting, request confirmation simulator termination setting, maximum time tolerance setting and loading debugging code setting;
1) Simulation file format setting: designating an absolute path or a relative path of the simulation file in the computer, and default inputting the selected file;
2) Simulation format initialization setting: an initial value for specifying a single discrete variable or initial position automaton in the simulation file;
3) Setting simulation ending time: selecting a simulation total duration in seconds;
4) Maximum delay setting: setting the maximum interval of each simulation statement output not to exceed the maximum delay
5) Randomly distributed initial seed settings: the randomness in the CIF model can be modeled using random seeds, the CIF simulator using mersene twist to specify a pseudo-randomness, the random numbers generated by the same seeds being the same;
6) Complete mode setting: specifying whether the CIF solver computes its complete set of transitions for each state, which would increase performance consumption if the complete mode was turned on;
7) The external function asynchronously executes the setting: the functions defined outside in the default are executed in an asynchronous mode, but the asynchronous execution causes certain performance loss, and the loss can be eliminated by adopting a synchronous execution mode;
8) Analysis settings: enabling analysis to output the conversion times per second in the simulation process at a control console;
9) Request confirmation simulator termination settings: the simulator decides to terminate or automatically decides to terminate by the user;
10 Maximum time tolerance setting): because the floating point number operation causes calculation error accumulation, once the calculation error exceeds the set maximum time tolerance, the simulator compensates the error to improve the calculation accuracy;
11 Loading debug code settings: disk locations may be specified to save the generated code to a hard disk instead of memory for use in improving simulation speed and saving simulation output.
Compiling and setting: the method comprises the steps of compiling only settings, compiling code file settings and Java compiler settings;
compiling only the settings: the emulator may be used to generate the code and compile it only once. By enabling the "compile only" option (compiler class), the emulator will perform all the steps required to generate and compile the code, and then save the compiled code to the file. After saving the file, the emulator will terminate instead of emulating the model.
Compiled code file settings: compiling path of simulation file for storing model and Java code, if not specified, using inputted file path
Java compiler settings: using the Java compiler option (compiler class), the Java compiler implementation to be used can be configured.
Input settings: the method comprises the steps of setting an input mode, setting an automatic mode selection algorithm, setting an automatic mode time conversion duration, setting a tracking input file, setting an interactive mode automatic conversion selection, setting an environmental event, setting a history and setting a history capacity;
1) Input mode setting: the input components for the simulation are dependent on the input mode and can be configured by input mode options.
2) Automatic mode selection algorithm settings: in the automatic input mode, the simulator automatically selects the transition and the duration of the time transition. However, the manner in which the simulator is selected may be affected by the options.
In the automatic input mode, the simulator will automatically select the transition to be made without any user interaction.
3) Automatic mode time transition duration setting: in the automatic input mode, the simulator will automatically select the duration of the time transition without any user interaction. However, the use of an automatic mode time transition duration option may affect the selection made.
4) Tracking input file settings: in the trace input mode, the simulator automatically selects transitions and time transition durations based on the trace file provided by the user. If a trace input mode is used, a trace input file option may be used to specify a path of the trace file. If the path is not explicitly specified, then the input CIF file path is used, where the file extension (if present) will be deleted and added.
5) Interaction mode automatic switching selection setting: by default, in the interactive console and GUI input mode, the user is required to make a selection, even though there is only one possible transition, for example. Having to make a selection for each transition can become tedious. To reduce the need for input, a semi-automatic mode may be used. The semi-automatic mode allows the simulator to automatically select certain transitions while leaving the remaining selections to the user.
6) Environmental event setting: by default, the CIF simulator treats all events as emergency events. That is, time may not progress as long as any event is likely to transition. In other words, the event takes precedence over the time lapse. However, not all events should be urgent. Thus, the simulator has environmental event options (input categories) that allow the simulator to learn about environmental events
(non-emergency event). One example of an environmental event (non-emergency event) is a button that can be pressed. The button can be pressed at any time, whether now or in the future. Thus, the corresponding event is always in an enabled state, but the time should still be able to proceed, as the event may not actually occur at this time.
7) History setting: may be used to enable or disable the history. By default, the history is in an enabled state. Using this option, it can be disabled. Disabling the history disables the reset and undo functions, thereby ensuring that no time or memory is consumed to track early status.
8) Historical capacity setting: for long simulations, many states need to be remembered. Each state that needs to be remembered consumes a certain amount of memory. To limit the number of states to be remembered, a history size option may be used.
Output setting: the method comprises the steps of general output setting, SVG visual setting, track data setting, graph visual setting and state visual setting;
general output setting: including normal output, normal output status filter, debug output, frame rate, emulation speed, and test mode settings.
SVG visualization settings: the CIF solver outputs SVG visual results when the SVG visual results are checked;
setting track data: the CIF solver outputs a track visualization result when the trace is checked;
graph visualization settings: the CIF solver outputs a graph visualization result when the graph is checked;
status visualization settings: the CIF solver outputs a state visualization result when the state is checked.
ODE solver settings: the method comprises the steps of setting a fixed output step length of an ODE solver, setting an ODE integrator, setting an ODE root finder and the like.
The ODE solver fixes the output step size: the integrator determines the point in time of the calculated value. By default, these points are contained in the track. Meaning that they are also outputs of the trajectory data output component. The integrator determines the point in time of the calculated value based on the complexity of the ordinary differential equation. The integrator may be affected using an integrator option. However, it may sometimes be more convenient to perform the integrated output at more regular intervals. Using the ODE solver fixed output step option, a fixed output step may be configured. This value must be an integer greater than zero or a real number.
ODE integrator settings: the method comprises the steps of an ODE solving integrator algorithm, an absolute tolerance of the ODE solving integrator, a relative tolerance of the ODE solving integrator, a minimum step length of the ODE solving integrator, a maximum step length of the ODE solving integrator, the number of steps of the ODE solving integrator and the like.
ODE root finder settings: the method comprises the steps of setting the maximum checking interval of the ODE solving root finder, the root finding algorithm of the ODE solving root finder, the absolute tolerance of the ODE solving root finder, the relative tolerance of the ODE solving root finder, the maximum iteration number of the ODE solving root finder and the like.
The simulation execution is to call the CIF solver to simulate a state machine after the simulation configuration is completed;
there are two cases of simulation execution: simulation execution success and simulation execution failure;
simulation execution succeeds: if the simulation is successfully executed, outputting simulation process information on a control console and a state visualization corresponding window according to simulation configuration;
simulation execution fails: if the simulation execution fails, an error is output, after the developed behavior code is required to be modified based on the output error, the simulation compiling and the simulation configuration steps of the state machine are carried out, and then the simulation execution is carried out.
The simulation result is mainly obtained by checking corresponding output information when the simulation is executed and storing simulation data after the simulation is finished, and the obtained simulation result is used for verifying the model.
The verification model is based on the obtained simulation result and the system demand and function model for comparison verification; if the verification model is correct, the simulation is ended, if the verification model is wrong, the error source is searched, the system state machine diagram is possibly modified according to actual conditions, and then development behavior codes, state machine simulation compiling and simulation configuration operations are executed.
Compared with the prior art, the invention has the following beneficial effects:
the system engineering based on the model describes the system behavior in a model mode, and develops a system behavior code on the basis of the system behavior code to simulate a state machine. Therefore, early in the development and design of the system, system designers are helped to find out design defects, so that the system design cost is reduced, the development period is shortened, and the reliability of the system is improved.
The system behavior description and the development of the system behavior code can be performed aiming at a specific field, and meanwhile, the system behavior code can be developed on the basis of the existing behavior code template by importing the template, so that the workload is reduced.
The state machine simulation method for the complex system is described in detail. The description of the specific embodiments is only intended to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
Claims (8)
1. A state machine simulation method for a complex system is characterized by comprising the following steps:
s1, constructing a system state machine diagram based on a SysML state machine primitive model;
s2, developing behavior codes;
s3, simulating and compiling by a state machine;
s4, simulation configuration;
s5, simulation execution;
s6, obtaining a simulation result;
s7, verifying the model to complete simulation.
2. The state machine simulation method for a complex system according to claim 1, wherein constructing a system state machine graph is based on a SysML graphical modeling language specification, and describing system behavior in terms of states and transitions between states;
the system state machine diagram includes elements of:
area: the state machine comprises one or more regions that collectively describe state-related behavior of the state machine, and initialization and completion of one region is described using an initial pseudo-state and a final state, respectively;
status: the states are represented by a rounded rectangle representing important conditions, representing changes in response to events and changes in execution behavior, each state may contain the respective execution of ingress and egress behavior upon entering and exiting the state;
conversion: transitions dictate when state changes are developed in the state machine.
3. The state machine simulation method for the complex system according to claim 2, wherein the development behavior code is developed by selecting a certain state machine model element in a mode of combining with a graphical model, and storing the behavior code in a system state machine model file;
the developed code type description includes:
region code development: the developed region behavior code may contain one region behavior code or a plurality of region behavior codes;
developing state codes: simple state code development includes defining whether a state is initialized or not and equation setting at the time of the state, and group code development includes attribute code development and function code development;
development of conversion codes: including event code development, condition code development, assignment code development, and state jump code development;
SVG code development: including SVG file binding code development and basic property code development.
4. A state machine simulation method for a complex system according to claim 3, wherein the state machine simulation compilation is to compile developed codes to form CIF codes used by a CIF solver;
the state machine simulation compiling comprises single-region compiling and multi-region compiling;
single region compilation: compiling behavior codes in a state machine model file of a region to form a single-region CIF code file for a CIF solver;
multi-region compilation: firstly defining the names of multi-region CIF code files, then respectively compiling the behavior codes in the state machine model files of the multiple regions in a single region, and merging the obtained single-region CIF code files to form a multi-region CIF code file for a CIF solver.
5. The state machine simulation method for a complex system according to claim 4, wherein the simulation configuration is a series of configurations required before the simulation is performed, so as to implement the setting of the simulation;
the simulation configuration comprises input mode setting, simulation setting, compiling setting, input setting, output setting and ODE solver setting;
input mode setting: including error, warning, normal, and debug options;
simulation setting: the method comprises the steps of simulation file format setting, simulation format initialization setting, simulation ending time setting, maximum delay setting, random distribution initial seed setting, complete mode setting, external function asynchronous execution setting, analysis setting, request confirmation simulator termination setting, maximum time tolerance setting and loading debugging code setting;
compiling and setting: the method comprises the steps of compiling only settings, compiling code file settings and Java compiler settings;
input settings: the method comprises the steps of setting an input mode, setting an automatic mode selection algorithm, setting an automatic mode time conversion duration, setting a tracking input file, setting an interactive mode automatic conversion selection, setting an environmental event, setting a history and setting a history capacity;
output setting: the method comprises the steps of general output setting, SVG visual setting, track data setting, graph visual setting and state visual setting;
ODE solver settings: the method comprises the steps of setting a fixed output step length of an ODE solver, setting an ODE integrator, setting an ODE root finder and the like.
6. The method for simulating a state machine for a complex system according to claim 5, wherein the simulation execution is to call a CIF solver to perform state machine simulation after the completion of the simulation configuration;
there are two cases of simulation execution: simulation execution success and simulation execution failure;
simulation execution succeeds: if the simulation is successfully executed, outputting simulation process information on a control console and a state visualization corresponding window according to simulation configuration;
simulation execution fails: if the simulation execution fails, an error is output, after the developed behavior code is required to be modified based on the output error, the simulation compiling and the simulation configuration steps of the state machine are carried out, and then the simulation execution is carried out.
7. The method of claim 6, wherein the simulation result is obtained by checking corresponding output information when the simulation is performed and storing the simulation data after the simulation is completed, and the obtained simulation result is used for verifying the model.
8. The state machine simulation method for a complex system according to claim 7, wherein the verification model is based on comparison verification of the obtained simulation result with the system requirements and the functional model; if the verification model is correct, the simulation is ended, if the verification model is wrong, the error source is searched, the system state machine diagram is possibly modified according to actual conditions, and then development behavior codes, state machine simulation compiling and simulation configuration operations are executed.
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