CN117850570A - Singlechip system - Google Patents

Abstract

The application discloses singlechip system includes: a single chip Microcomputer (MCU) kernel, a dynamic power consumption control module and a first peripheral module; the MCU core is set as follows: when the executed instruction is judged to need to operate the first peripheral module, a first notification message is sent to the first peripheral module; the first peripheral module includes a request mechanism unit configured to: when receiving the first notification message, generating a request opening message; sending a request opening message to a dynamic power consumption control module; the dynamic power consumption control module is set as follows: according to the received request opening message, opening clock gating of the first peripheral module; the first peripheral module is one of peripheral modules with more than one clock gate controlled to be closed in the singlechip system. According to the embodiment of the disclosure, the first peripheral module which needs to be operated for executing the instruction executes the process of opening clock gating through the dynamic power consumption control module, so that the dynamic control of the singlechip system is realized, and the system power consumption is reduced.

Description

Singlechip system

Technical Field

The present application relates to, but is not limited to, single chip technology, and relates to a single chip system.

Background

Currently, a single chip Microcomputer (MCU) is mainly applied to the fields of consumer electronics, industrial control, communication, automotive electronics, and the like, and the power consumption control of the MCU adopts a static method, and a Clock Gate of a peripheral module is turned on or turned off at a user design end according to application requirements, so that the MCU is a popular power management technology for reducing dynamic power consumption in many synchronous circuits. It is achieved by turning off the clock signal of some parts of the digital design when not needed; among them, the peripheral modules involved include universal asynchronous receiver/transmitter (UART for serial communication, widely used in various devices including industrial control, medical device, remote control, office device, home appliance, toy and embedded system), timer (Timer, device for generating accurate time delay in microcontroller), watchDog (Timer for monitoring system operation status), I2C (Inter-Integrated Circuit, a serial communication bus protocol for connecting microcontroller and external device), SPI (Serial Peripheral Interface, an interface standard for serial communication, commonly used for connecting microcontroller and external device), SD (Secure Digital, a memory card standard for data storage and exchange between microcontroller and external device), general Purpose Input Output (GPIO), flash memory (Flash, nonvolatile memory for storing programs and data) and ethernet: ethernet (Ethernet) is a common local area network technology used to connect devices and communicate data, such as modules including an Ethernet interface to a microcontroller. And for the peripheral module to be used, opening Clock gating (Clock Gate) of the peripheral module at a user design end, and otherwise, closing the Clock gating of the peripheral module.

In the related art, after a user designs a peripheral module, when the peripheral module is operated in an MCU, clock gating of the peripheral module is kept in an open or closed state when the peripheral module is designed, power consumption of the whole system is fixed in the operation process, and how to dynamically adjust the power consumption of the MCU system and improve the utilization rate of resources becomes a problem to be solved.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a singlechip system, which can dynamically adjust the power consumption of an MCU system and improve the utilization rate of resources.

The embodiment of the disclosure provides a singlechip system, which comprises: the system comprises a singlechip MCU core, a dynamic power consumption control module and a first peripheral module; wherein,

the MCU core is set as follows: when the executed instruction is judged to need to operate the first peripheral module, a preset first notification message is sent to the first peripheral module;

the first peripheral module includes a request mechanism unit configured to: when receiving the first notification message, generating a request opening message according to a preset data structure; sending the generated request opening message to a dynamic power consumption control module, wherein the request opening message comprises the mapping address of the first peripheral module and the operation information of opening clock gating;

the dynamic power consumption control module is set as follows: according to the received request opening message, opening clock gating of the first peripheral module;

the first peripheral module is one of peripheral modules with more than one clock gating closed in the singlechip system.

In one illustrative example, the dynamic power consumption control module is configured to:

and analyzing the request opening message from the request mechanism unit, acquiring the mapping address and the operation information of the first peripheral module from the request opening message, and opening clock gating of the first peripheral module according to the mapping address.

In an exemplary embodiment, the one or more peripheral modules in the single-chip microcomputer system include one or any combination of the following:

universal asynchronous receiver/transmitter UART, timer, watchDog, I2C, serial bus interface SPI, SD, GPIO, flash, and Ethernet.

In one illustrative example, the request mechanism unit includes: an interrupt trigger detection subunit, a bus control request and response subunit and an enabling request subunit; wherein,

the interrupt trigger detection subunit is configured to: detecting whether the first notification message is received;

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, a bus for transmitting the request opening message is acquired;

the enabling request subunit is configured to: and sending the request opening message to the dynamic power consumption control module through the acquired bus.

In one illustrative example, the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, sending a request message for requesting a bus to the MCU kernel so as to acquire a bus for transmitting the request opening message;

the MCU core is further configured to: according to the received request message requesting the bus, notifying the dynamic power consumption control module to open the bus so as to receive the request opening message; sending a response message to the request mechanism unit;

the enabling request subunit is configured to: and when the response message is received, sending the request opening message to the dynamic power consumption control module through the acquired bus.

In one illustrative example, the dynamic power consumption control module is configured to:

after detecting the notification of the MCU kernel opening the bus, receiving the request opening message through the bus acquired by the bus control request and response subunit; and opening clock gating of the first peripheral module according to the request opening message.

In an exemplary embodiment, the MCU core is further configured to: judging that the instruction execution is completed, and sending a preset second notification message to the first peripheral module;

the request mechanism unit is further configured to: when receiving the second notification message, generating a request closing message according to a preset data structure; the generated request closing message is sent to a dynamic power consumption control module, wherein the request closing message comprises a mapping address of a first peripheral module and operation information for closing clock gating;

the dynamic power consumption control module is further configured to: and closing clock gating of the first peripheral module according to the received request closing message.

Compared with the related art, the application comprises the following steps: a single chip Microcomputer (MCU) kernel, a dynamic power consumption control module and a first peripheral module; the MCU core is set as follows: when the executed instruction is judged to need to operate the first peripheral module, a first notification message is sent to the first peripheral module; the first peripheral module includes a request mechanism unit configured to: when receiving the first notification message, generating a request opening message; sending a request opening message to a dynamic power consumption control module; the dynamic power consumption control module is set as follows: according to the received request opening message, opening clock gating of the first peripheral module; the first peripheral module is one of peripheral modules with more than one clock gate controlled to be closed in the singlechip system.

According to the embodiment of the disclosure, the first peripheral module which needs to be operated for executing the instruction executes the process of opening clock gating through the dynamic power consumption control module, so that the dynamic control of the singlechip system is realized, and the system power consumption is reduced.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

FIG. 1 is a block diagram of a singlechip system according to an embodiment of the disclosure;

fig. 2 is a process schematic of an embodiment of the present disclosure.

Detailed Description

The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.

Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Fig. 1 is a structural block diagram of a singlechip system according to an embodiment of the disclosure, as shown in fig. 1, including: a single chip Microcomputer (MCU) kernel, a dynamic power consumption control module and a first peripheral module; wherein,

the MCU core is set as follows: when the executed instruction is judged to need to operate the first peripheral module, a preset first notification message is sent to the first peripheral module;

the first peripheral module includes a request mechanism unit configured to: when receiving the first notification message, generating a request opening message according to a preset data structure; sending the generated request opening message to a dynamic power consumption control module, wherein the request opening message comprises the mapping address of the first peripheral module and the operation information of opening clock gating;

the dynamic power consumption control module is set as follows: according to the received request opening message, opening clock gating of the first peripheral module;

the first peripheral module is one of peripheral modules (in the figure, the peripheral modules 1 to n are closed peripheral modules except the first peripheral module) with more than one clock gate controlled to be closed in the singlechip system.

According to the embodiment of the disclosure, the clock gating of the peripheral module in the singlechip system is in the off state, and when the MCU kernel executes the instruction, the first peripheral module which needs to be operated for executing the instruction executes the process of opening the clock gating through the dynamic power consumption control module, so that the dynamic control of the singlechip system is realized, the clock gating of the unused peripheral module is in the off state, the MCU is always in the state with the lowest power consumption, and the power consumption of the MCU is reduced.

In one illustrative example, the instructions executed by the MCU core of the disclosed embodiments may be defined by its instruction set. The instruction set specifies the functions to be performed by the processor, including arithmetic operations, logical operations, and data transfers. The instruction set of an MCU is typically composed of a Reduced Instruction Set Computer (RISC) or Complex Instruction Set Computer (CISC) architecture, which uses some simple instructions to increase the execution rate and minimize the time required for instructions. The process of executing the program is actually the process of executing instructions one by one, and each time the computer executes an instruction, the computer can be divided into three stages of instruction fetching, analysis and execution; the instruction set of the MCU is the basis for the execution code of the CPU of the core unit, and determines the functions and the performance of the MCU.

In one illustrative example, the communication processing between the request mechanism unit and the dynamic power consumption control module of the disclosed embodiments may be implemented with reference to the principle of Direct Memory Access (DMA).

In one illustrative example, the dynamic power consumption control module of the disclosed embodiments is configured to:

and analyzing a request opening message from the request mechanism unit, acquiring the mapping address and the operation information of the first peripheral module from the request opening message, and opening clock gating of the first peripheral module according to the mapping address.

In an exemplary embodiment, the one or more peripheral modules in the singlechip system according to the embodiment of the disclosure include one or any combination of the following:

universal asynchronous receiver/transmitter (UART), timer (Timer), watchDog (WatchDog), I2C, serial bus interface (SPI), SD, general Purpose Input Output (GPIO), flash memory (Flash), and Ethernet (Ethernet).

In one illustrative example, a request mechanism unit of the disclosed embodiments includes: an interrupt trigger detection subunit, a bus control request and response subunit and an enabling request subunit; wherein,

the interrupt trigger detection subunit is configured to: detecting whether a first notification message is received;

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, a bus for transmitting a request opening message is acquired;

the enable request subunit is set to: and sending a request opening message to the dynamic power consumption control module through the acquired bus.

In one illustrative example, embodiments of the present disclosure:

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, sending a request message for requesting a bus to the MCU core so as to acquire a bus for transmitting a request opening message;

the MCU core is also provided with: according to the received request message requesting the bus, notifying the dynamic power consumption control module to open the bus so as to receive the request opening message; sending a response message to the request mechanism unit;

the enable request subunit is set to: and when receiving the response message, sending a request opening message to the dynamic power consumption control module through the acquired bus.

When the request opening message needs to be transmitted, the corresponding bus is opened through the processing, and the transmission of the request opening message is realized.

In one illustrative example, the dynamic power consumption control module of the disclosed embodiments is configured to:

after detecting the notice of the MCU kernel opening the bus, receiving a request opening message through the bus obtained by the bus control request and response subunit; and opening clock gating of the first peripheral module according to the request opening message.

In one illustrative example, embodiments of the present disclosure:

the MCU core is also provided with: judging that the instruction execution is completed, and sending a preset second notification message to the first peripheral module;

the request mechanism unit is further arranged to: when receiving the second notification message, generating a request closing message according to a preset data structure; sending the generated request closing message to a dynamic power consumption control module, wherein the request closing message comprises the mapping address of the first peripheral module and the operation information for closing clock gating;

the dynamic power consumption control module is further configured to: and closing clock gating of the first peripheral module according to the received request closing message.

According to the embodiment of the disclosure, the MCU closes the clock gating of the first peripheral module after executing the instruction, so that the system power consumption control is dynamically realized, and the system power consumption is reduced.

The following briefly describes embodiments of the present disclosure by way of application examples, which are merely set forth embodiments of the present disclosure and are not intended to limit the scope of the embodiments of the present disclosure.

Application example

The embodiment of the disclosure realizes a request opening and closing mechanism for each peripheral module in the MCU system;

when the MCU kernel executes an instruction, if a certain peripheral module (a first peripheral module in the embodiment of the disclosure, hereinafter referred to as a first peripheral module for short) is needed to execute the instruction, but Clock gating (Clock Gate) of the peripheral module is closed by default, the MCU kernel sends a preset notification message to the first peripheral module, wherein the notification message contains information for opening the Clock gating;

the request mechanism unit of the first peripheral module generates a request opening message according to a preset structure and a received notification message, and sends the request opening message to the dynamic power consumption control module, wherein the request opening message comprises the mapping address of the first peripheral module and the operation information for opening clock gating;

the dynamic power consumption control module analyzes the request opening message from the request mechanism unit, acquires the mapping address and the operation information of the first peripheral module from the request opening message, and executes the operation of opening clock gating on the first peripheral module according to the mapping address.

The instructions executed by the MCU core in embodiments of the present disclosure may be defined by its instruction set. The instruction set specifies the functions to be performed by the processor, including arithmetic operations, logical operations, and data transfers. The instruction set of an MCU is typically composed of a Reduced Instruction Set Computer (RISC) or Complex Instruction Set Computer (CISC) architecture, which uses some simple instructions to increase the execution rate and minimize the time required for instructions. The process of executing the program is actually the process of executing instructions one by one, and each time the computer executes an instruction, the computer can be divided into three stages of instruction fetching, analysis and execution; the instruction set of the MCU is the basis for the execution code of the CPU of the core unit, and determines the functions and the performance of the MCU.

In the above processing of the embodiment of the present disclosure, the MCU core only notifies the peripheral module at the beginning, during which the MCU core may perform other operation processing, and the request mechanism unit of the first peripheral module communicates directly with the dynamic power consumption control module.

In one illustrative example, the communication process between the requesting mechanism unit and the dynamic power consumption control module may be implemented with reference to the principle of Direct Memory Access (DMA).

In an exemplary embodiment, the embodiment of the disclosure sets a dynamic power consumption control module in the MCU; when an instruction executed by the MCU needs to use the first peripheral module, a notification message is sent to the peripheral module, a request mechanism unit of the first peripheral module sends a request opening message to a dynamic power consumption control module, and after the dynamic power consumption control module receives the request opening message, the operation of opening clock gating of the first peripheral module is executed;

in an exemplary embodiment, embodiments of the present disclosure preset a request to open message, including a header, data, and a trailer; the packet head comprises a 1-byte initial symbol and a 4-byte mapping address of a peripheral module; the data includes operation information, which may be operation code information, for example, 0x01 indicates on and 0x00 indicates off; the trailer includes a 1 byte end symbol.

According to the embodiment of the disclosure, when the request mechanism unit of the first peripheral module sends a request opening message, it can be determined that the first peripheral module can execute clock gating switching operation; in other words, when the request mechanism unit of the first peripheral module sends a request to open message, it indicates that the peripheral module is ready, and clock gating switching operation can be performed;

in an exemplary embodiment, when the MCU core completes use of the first peripheral module, that is, after executing the instruction that requires the first peripheral module, the request mechanism unit of the first peripheral module is further configured to: and sending a request closing message to the dynamic power consumption control module, and closing clock gating of the first peripheral module according to the request closing message after the dynamic power consumption control module receives the request closing message.

The MCU system in the embodiment of the disclosure can be provided with a dynamic power consumption control module and corresponding request mechanism units in each peripheral module.

In an exemplary embodiment, after the MCU is powered on, each peripheral module in the MCU system defaults to turn off clock gating, and the overall power consumption of the MCU system is the lowest state during power-on.

According to the embodiment of the disclosure, clock gating is only started when the MCU core uses the first peripheral module, and the clock gating of the unused peripheral module is in a closed state, so that the MCU is always in a state with the lowest power consumption, and the power consumption of the MCU is reduced.

In the following, embodiments of the present disclosure will be briefly described by way of specific examples, and fig. 2 is a schematic process diagram of an embodiment of the present disclosure, as shown in fig. 2, including:

when the MCU core executes an instruction, it is assumed that the instruction is to operate I2C, but the system defaults to clock gating of I2C to off.

The MCU kernel sends a notification message to inform I2C that I2C needs to be used through a bus connected with I2C, wherein the notification message contains information of opening clock gating; and the communication processing between the I2C and the dynamic power consumption control module is carried out, the MCU is not participated any more, and other processing is carried out.

After the I2C receives the notification message of the MCU core, the request mechanism unit in the I2C generates a request open message, for example 01400000000101, where 01 represents a start symbol, 40000000 represents a mapping address of the I2C,01 represents opening the I2C, and 01 represents an end symbol.

The request mechanism unit of the I2C sends a request opening message to the dynamic power consumption control module. The dynamic power consumption control module analyzes the received request opening message, finds a clock gating signal of the I2C according to the mapping address of the I2C in the request opening message, and enables gating of the I2C to be started, so that the I2C is enabled.

After the clock gating of the I2C is started, the MCU kernel controls the I2C to execute an instruction needing to be operated, after the instruction operation is completed, the I2C is also informed of the completion of the execution operation, the clock gating of the I2C can be closed, and then the clock gating of the I2C is closed based on the same flow of starting the clock gating; corresponding to the request-to-open message described above, the request-to-close message of the disclosed embodiments may be 01400000000001, where 01 represents a start symbol, 40000000 represents a mapped address of I2C, 00 represents opening I2C, and 01 represents an end symbol.

In one illustrative example, the request mechanism unit of embodiment I2C of the present disclosure includes: an interrupt trigger detection subunit, a bus control request and response subunit and an enabling request subunit; wherein,

the interrupt trigger detection subunit is configured to: detecting whether a notification message sent by an MCU kernel is received or not;

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the notification message sent by the MCU kernel is received, sending a request message for requesting the bus to the MCU kernel so as to acquire the bus;

the enable request subunit is set to: sending an I2C request opening message to the dynamic power consumption control module through the acquired bus;

the MCU core is set as follows: according to the received request message requesting the bus, notifying the dynamic power consumption control module I2C that the bus is required to send the request opening message of the I2C to the dynamic power consumption control module I2C; meanwhile, a response message is sent to the request mechanism unit, the I2C is notified to the dynamic power consumption control module, and a request opening message of the I2C can be sent through a bus;

the dynamic power consumption control module is set as follows: after detecting a request message of a bus request notified by the MCU core, receiving a request opening message sent by the I2C through the bus by a bus control request and a bus opened by a response subunit; and when receiving the request opening message, sending a control signal to the clock gating to open the clock gating of the I2C. The embodiment of the disclosure can refer to the flow request to close the clock gating of the I2C when the MCU core no longer needs the I2C.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (7)

1. A single chip microcomputer system, comprising: the system comprises a singlechip MCU core, a dynamic power consumption control module and a first peripheral module; wherein,

the MCU core is set as follows: when the executed instruction is judged to need to operate the first peripheral module, a preset first notification message is sent to the first peripheral module;

the first peripheral module includes a request mechanism unit configured to: when receiving the first notification message, generating a request opening message according to a preset data structure; sending the generated request opening message to a dynamic power consumption control module, wherein the request opening message comprises the mapping address of the first peripheral module and the operation information of opening clock gating;

the dynamic power consumption control module is set as follows: according to the received request opening message, opening clock gating of the first peripheral module;

the first peripheral module is one of peripheral modules with more than one clock gating closed in the singlechip system.

2. The single-chip microcomputer system of claim 1, wherein the dynamic power consumption control module is configured to:

and analyzing the request opening message from the request mechanism unit, acquiring the mapping address and the operation information of the first peripheral module from the request opening message, and opening clock gating of the first peripheral module according to the mapping address.

3. The single-chip microcomputer system of claim 1, wherein the one or more peripheral modules within the single-chip microcomputer system comprise one or any combination of the following:

universal asynchronous receiver/transmitter UART, timer, watchDog, I2C, serial bus interface SPI, SD, GPIO, flash, and Ethernet.

4. The single-chip microcomputer system of claim 1, wherein the request mechanism unit comprises: an interrupt trigger detection subunit, a bus control request and response subunit and an enabling request subunit; wherein,

the interrupt trigger detection subunit is configured to: detecting whether the first notification message is received;

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, a bus for transmitting the request opening message is acquired;

the enabling request subunit is configured to: and sending the request opening message to the dynamic power consumption control module through the acquired bus.

5. The single-chip microcomputer system as defined in claim 4, wherein:

the bus control request and response subunit is configured to: when the interrupt triggering detection subunit detects that the first notification message is received, sending a request message for requesting a bus to the MCU kernel so as to acquire a bus for transmitting the request opening message;

the MCU core is further configured to: according to the received request message requesting the bus, notifying the dynamic power consumption control module to open the bus so as to receive the request opening message; sending a response message to the request mechanism unit;

the enabling request subunit is configured to: and when the response message is received, sending the request opening message to the dynamic power consumption control module through the acquired bus.

6. The single chip microcomputer system of claim 5, wherein the dynamic power consumption control module is configured to:

after detecting the notification of the MCU kernel opening the bus, receiving the request opening message through the bus acquired by the bus control request and response subunit; and opening clock gating of the first peripheral module according to the request opening message.

7. The single-chip microcomputer system according to any one of claims 1 to 6, wherein:

the MCU core is further configured to: judging that the instruction execution is completed, and sending a preset second notification message to the first peripheral module;

the request mechanism unit is further configured to: when receiving the second notification message, generating a request closing message according to a preset data structure; the generated request closing message is sent to a dynamic power consumption control module, wherein the request closing message comprises a mapping address of a first peripheral module and operation information for closing clock gating;

the dynamic power consumption control module is further configured to: and closing clock gating of the first peripheral module according to the received request closing message.