CN117833866A - Non-integer multiple downsampling CIC filter - Google Patents

Abstract

The application relates to digital signal processing and discloses a non-integer multiple downsampling CIC filter, which adopts the technology of PipleLine to convert an integrator of CIC, upscales data under the condition of not changing CIC clock, and simultaneously cooperates with a downsampler and a differentiator to realize non-integer multiple downsampling CIC filtering of original data. By reconstructing the interpolator and integrator, the zero-insertion operation is avoided, thereby avoiding the need to add an additional clock, and secondly preserving the variability of the downsampling system, without increasing the computational complexity.

Description

Non-integer multiple downsampling CIC filter

Technical Field

The present application relates to digital signal processing, and more particularly to digital signal multi-sample rate CIC (Cascade Integrator Comb, cascaded integrator-comb filter, abbreviated as "CIC") conversion techniques.

Background

In digital signal processing, CIC filters use integration and a cascade of comb filters. The CIC filter consists of one or more pairs of integrating-comb filters, and in decimating the CIC, the input signal is sequentially subjected to integration, downsampling, and comb filters of the same number as the integration segments. In interpolation CIC, the input signal is sequentially subjected to comb filter, up-sampling, and integration links with the same number of combs

However, the basic architecture of the existing downsampling CIC is 'integral-downsampling-derivative', only the downsampling filtering of integer multiples of data can be realized, in order to realize the downsampling function of non-integer multiples, the original data needs to be subjected to 0-insertion processing, then the data subjected to 0-insertion is sent to the CIC for filtering, the clock frequency of the CIC is also increased along with the multiple of 0-insertion, and when the multiple of the upsampling exceeds the upper limit of the possible increase of the CIC clock, the method is not applicable any more.

On the other hand, as shown in fig. 1, the conventional CIC downsampling technique is shown in the following diagram, and the CIC structure is integrated first, then downsampled, and finally differentiated. This structure can only achieve integer multiples of data x (n). If the non-integer multiple downsampling is needed, the upsampling operation of 0 insertion is needed to be performed on x (n) first, then CIC is entered, and meanwhile, the clock frequency of the CIC is correspondingly increased, so that data with higher sampling rate after 0 insertion can be processed.

Therefore, there is a need for a technique that enables CIC extraction at non-integer multiples without increasing the clock frequency.

Disclosure of Invention

The utility model provides a CIC wave filter is adopted down to non-integer multiple can realize that non-integer multiple adopts down the CIC not need to improve clock frequency to, through with interpolator and integrator reconfiguration, avoided inserting zero operation, thereby avoid needing to increase extra clock, secondly remain down the variability of adopting the system, and do not increase computational complexity.

The application discloses CIC filter is adopted down to non-integer multiple includes: the P-order integrator, the downsampler and the differentiator are sequentially connected, and is characterized in that the P-order integrator comprises a first-stage integrator to a P-stage integrator, P is an integer larger than 2, and,

the calculation formula of the first-stage integrator is as follows:

S1(n)＝S1(n-1)+x(n)

the calculation formula of the second-stage integrator is:

the calculation formula of the L-th integrator is 2< L < P:

wherein x (n) and S1 (n) are the input signal and the output signal of the first stage integrator at the nth clock period, M _ij (n) is the j-th output signal of the I-th integrator at the n-th clock cycle, I is a multiple of the up-sampling, and the second to P-th integrators output I signals at each clock cycle.

In a preferred embodiment, the output sequence M of the second to L-th integrator stages _L0 To delay one data point, the sequence [ M ] is output _L0 (n-1),M _L1 (n),M _L2 (n),…,M _L(I-1) (n)]As [ M ] _L0 (n),M _L1 (n),M _L2 (n),…,M _L(I-1) (n)]To the next integrator or to the downsampler.

In a preferred embodiment, in the downsampler, the input data of the downsampler is represented as M _Li (n), wherein i=0, 1,2, …, I-1, the rule that the downsampler performs D-fold downsampling is:

when M _Li (n) satisfying "(n×i+i) is an integer multiple of D", M _Li The output of (n) is z (k).

In a preferred embodiment, the multi-stage integrator transforms the integration portion and the integrator of the CIC is equivalently transformed using the pileline technique to upsample the data without changing the CIC clock.

The embodiment of the application has the following technical effects:

non-integer multiple downsampling CIC can be achieved without increasing clock frequency, zero insertion operation is avoided by reconstructing the interpolator and the integrator, so that the need of adding an additional clock is avoided, the variability of downsampling is reserved, and computational complexity is not increased.

In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are all regarded as being already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

FIG. 1 is a schematic diagram of a prior art CIC downsampling technique;

FIG. 2 is a schematic diagram of equivalent conversion of CIC integrators using the PipleLine technique with non-integer multiple downshifting CIC filters according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of one example of a non-integer multiple down-conversion CIC filter according to the present application;

FIG. 4 is a schematic diagram of a conventional fractional sample rate CIC filter structure;

fig. 5 is a schematic diagram of comparing a non-integer multiple down-sampling CIC filter of the present application with prior art output sequence waveforms.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

The following summary illustrates some of the innovative features of the present application:

through many years of intensive researches, the inventor of the application finds that in digital signal processing, a CIC filter is often used for realizing variable rate sampling technology, and the general idea is that the original data is subjected to 0 interpolation operation to achieve the purpose of up-sampling, and then the CIC filter is used for down-sampling, so that variable rate sampling is realized. The up-sampling operation results in a doubling of the original data sampling rate, so that the clock frequency of the CIC filter is correspondingly increased, and the processing of the data with higher sampling rate can be realized. However, when the clock frequency of the CIC filter cannot be increased due to certain limitations, the above method cannot be directly implemented. Based on the requirement, the inventor of the application creatively proposes a new implementation method for implementing CIC (common information carrier) under non-integer multiple without increasing the clock frequency of the CIC. The integrator of the CIC is converted by adopting the PipleLine technology, the data is up-sampled under the condition of not changing the CIC clock, and the non-integer multiple of the down-sampled CIC filtering of the original data is realized by matching the down-sampler and the differentiator.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application relates to a non-integer multiple downsampling CIC filter, as shown in fig. 2, comprising: the P-order integrator, the downsampler and the differentiator are sequentially connected, and P is an integer greater than 2.

Wherein, for the integrator, the basic technical concept is as follows: the integrator of the CIC is converted using the pieline technique to upsample the data without changing the CIC clock. The PipLine technique is a parallel processing technique, and the core idea is to decompose and change computation required to be executed sequentially into sentences which can be executed in parallel, so as to increase the speed of operation, and the PipLine technique is widely applied to the design of cpu. The invention creatively combines the technology with the CIC filter, completes the function of data up-sampling, and does not need to increase the clock frequency.

The implementation means of the integrator will be explained in detail below.

The structure shown in fig. 2 is proposed by performing equivalent conversion on the integrator of the CIC by using the npileline technology, and is specifically as follows:

preferably, the first-stage integrator is a simple first-order integrator, and the calculation formula is:

S1(n)＝S1(n-1)+x(n)

preferably, the calculation formula of the second-stage integrator is as follows:

preferably, the calculation formula of the L-th stage integrator is as follows, wherein 2< L < p:

it should be noted that, due to the characteristics of the npileline, it should be noted that the output sequences M of the second to L-th integrator _L0 To delay one data point, the sequence [ M ] is output _L0 (n-1),M _L1 (n),M _L2 (n),…,M _L(I-1) (n)]As [ M ] _L0 (n),M _L1 (n),M _L2 (n),…,M _L(I-1) (n)]To the next integrator or to the downsampler.

Since I data are calculated in parallel each time, the downsampler is improvedInput data is denoted as M _Li (n), wherein i=0, 1,2, …, I-1. The rule of D times downsampling by the downsampling device is as follows: when M _Li (n) satisfying "(n×i+i) is an integer multiple of D", M _Li The output of (n) is z (k). The method of differential calculation of z (k) data is identical to that of fig. 1.

In order to better understand the technical solutions of the present application, the following description is given with reference to a specific example, in which details are listed mainly for the sake of understanding, and are not meant to limit the scope of protection of the present application.

As shown in fig. 3, in this example, the first-stage integrator is a simple first-stage integrator, i.e., S1 (n) =s1 (n-1) +x (n).

The second integrator calculates three output data simultaneously each time one input data is received, and the algorithm is as follows:

the third stage integrator algorithm is as follows:

M ₃₀ (n)，M ₃₁ (n)，M ₃₂ (n) represents 3n+1,3n+2,3n+3 points, respectively, and M is a pair of every 320 points _3x Downsampling is performed and then fed to a differentiator. Based on this, the CIC realizes the function of 320/3= 106.666666 … times sampling data with a sampling rate of 1.6384MHz at a clock frequency of 1.6384 MHz.

According to the CIC filter of the embodiment, non-integer times of downsampling CIC can be realized without increasing clock frequency, zero insertion operation is avoided by reconstructing the interpolator and the integrator, so that the need of adding an extra clock is avoided, the variability of downsampling is reserved, and the computational complexity is not increased.

The embodiment has the beneficial effects that:

by reconstructing the interpolator and integrator, the zero-insertion operation is avoided, thereby avoiding the need to add additional clocks, secondly preserving the variability of the downsampling coefficients, and furthermore not increasing the computational complexity, since the final objective is to derive the transfer functions of SLi (n) and x (n), as the above-described graph structure shows, the computational complexity ultimately depends on the number of integrations.

The first embodiment is tested as follows:

with 1.6384MHz as sampling frequency, 60Hz fundamental wave signals are overlapped with 0.2% of direct current signals and 20% of 3 rd harmonics as input sequences, two groups of output sequences are obtained through a traditional fractional sampling rate CIC filter structure shown in figure 4 and a non-integer multiple down-sampling CIC filter structure realized by the invention respectively, and the results of the two groups of output sequences are completely consistent with the results of the comparison of waveforms of the output sequences in figure 5.

In the above embodiment, by reconstructing the interpolator and integrator, the zero-insertion operation is avoided, thereby avoiding the need to add an additional clock, and secondly preserving the variability of the downsampling system, and furthermore, the computational complexity is not increased, because the final objective is to derive the transfer functions of SLi (n) and x (n), and the computational complexity is still ultimately dependent on the number of integrations, as known from the above-described structure.

It should be noted that, in general, the parallel processing technology obtains the benefit of reducing the operation speed, and the cost is worth increasing the hardware resources such as the operation unit and the storage unit. Compared with the similar technology, the scheme provided by the invention can basically achieve the least increase of hardware resources.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

All documents mentioned in the present application are considered to be included in the disclosure of the present application in their entirety, so that they may be subject to modification if necessary. Further, it will be understood that various changes or modifications may be made to the present application by those skilled in the art after reading the foregoing disclosure of the present application, and such equivalents are intended to fall within the scope of the present application as claimed.

Claims (4)

1. A non-integer multiple downsampling CIC filter, comprising: the P-order integrator, the downsampler and the differentiator are sequentially connected, and is characterized in that the P-order integrator comprises a first-stage integrator to a P-stage integrator, P is an integer larger than 2, and,

the calculation formula of the first-stage integrator is as follows:

S1(n)＝S1(n-1)+x(n)

the calculation formula of the second-stage integrator is:

the calculation formula of the L-th integrator is that 2< L < P:

wherein x (n) and S1 (n) are the input signal and the output signal of the first stage integrator at the nth clock period, M _ij (n) is the j-th output signal of the I-th integrator at the n-th clock cycle, I is a multiple of the up-sampling, and the second to P-th integrators output I signals at each clock cycle.

2. The non-integer down-sampling CIC filter of claim 1, wherein the output sequence M of the second-stage to L-th-stage integrators _L0 To delay one data point, the sequence [ M ] is output _L0 (n-1)，M _L1 (n)，M _L2 (n)，...，M _L(I-1) (n)]As [ M ] _L0 (n)，M _L1 (n)，M _L2 (n)，...，M _L(I-1) (n)]To the next integrator or to the downsampler.

3. The non-integer multiple downscaled CIC filter of claim 2, wherein the downscaler represents input data to the downscaler as M _Li (n), wherein i=0, 1,2, …, I-1, the rule that the downsampler performs D-fold downsampling is:

when M _Li (n) satisfying "(n×i+i) is an integer multiple of D", M _Li The output of (n) is z (k).

4. The non-integer multiple downsampling CIC filter of claim 1, wherein the multi-stage integrator transforms the integration portion to equivalently transform the integrator of the CIC using a pileline technique to upsample the data without changing the CIC clock.