CN117833604A - Open type integrated isolation power supply chip - Google Patents
Open type integrated isolation power supply chip Download PDFInfo
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- CN117833604A CN117833604A CN202311774246.XA CN202311774246A CN117833604A CN 117833604 A CN117833604 A CN 117833604A CN 202311774246 A CN202311774246 A CN 202311774246A CN 117833604 A CN117833604 A CN 117833604A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides an open type integrated isolation power supply chip, which comprises: the PWM modulation module is connected with the positive electrode of the direct current input voltage input end and is used for PWM modulating the direct current input voltage and outputting PWM modulation signals; the boosting module is connected with the PWM adjusting module and used for receiving the PWM modulation signal and outputting the boosted PWM modulation signal; the capacitor module is connected with the boosting module and used for carrying out isolation voltage division on the boosted PWM modulation signal and outputting the PWM modulation signal subjected to the isolation voltage division; and the rectification output module is connected with the capacitor module and is used for receiving the PWM modulation signal after the isolation voltage division and outputting the rectified direct current output voltage.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an open type integrated isolation power supply chip.
Background
The capacity-isolation type isolation power supply chip has the following advantages compared with an isolation power supply module integrated with an isolation transformer in the principle of realizing energy isolation transmission: the energy is not converted by the magnetic field, the EMC effect is good, and the implementation mode is cleaner.
In the implementation mode of the capacity-isolation type isolation power supply chip, the capacity of the voltage division capacitor and the inductance of the rectifying inductor are integrated by an integrated circuit, and the transmitted power is obviously limited.
Disclosure of Invention
The invention aims to provide an open type integrated isolation power supply chip which can solve the problems.
The technical scheme provided by the invention is as follows:
in some embodiments, the present invention provides an open integrated isolated power chip comprising:
the PWM modulation module is connected with the positive electrode of the direct current input voltage input end and is used for PWM modulating the direct current input voltage and outputting PWM modulation signals;
the boosting module is connected with the PWM adjusting module and used for receiving the PWM modulation signal and outputting the boosted PWM modulation signal;
the capacitor module is connected with the boosting module and used for carrying out isolation voltage division on the boosted PWM modulation signal and outputting the PWM modulation signal subjected to the isolation voltage division;
and the rectification output module is connected with the capacitor module and is used for receiving the PWM modulation signal after the isolation voltage division and outputting the rectified direct current output voltage.
In some embodiments, the capacitive module comprises: the first capacitor, the second capacitor, the third capacitor and the fourth capacitor;
the first capacitor is connected with the output end of the boosting module and the input end of the rectifying output module;
the second capacitor is connected with the negative electrode of the direct current input voltage input end and the negative electrode of the direct current output voltage input end;
one end of the third capacitor is positioned between the first capacitor and the input end of the rectification output module, and the other end of the third capacitor is positioned between the second capacitor and the input end of the direct current output voltage;
one end of the fourth capacitor is positioned between the third capacitor and the input end of the rectification output module, and the other end of the fourth capacitor is positioned between the second capacitor and the input end of the direct current output voltage; wherein the third capacitor and the fourth capacitor are connected in parallel.
In some embodiments, the effective positive amplitude voltage across the third capacitor and the fourth capacitor parallel capacitor is calculated as: v (V) C Node C positive level magnitude/(2 x (1-PWM duty cycle)), node C being the connection node of the first capacitor and the third capacitor.
In some embodiments, the capacitive module further comprises: and the power tube is connected with the third capacitor and the fourth capacitor.
In some embodiments, the output node of the boost module is at a high level, and the voltage amplitude level in the positive half period is a positive voltage level amplitude obtained by connecting the third capacitor and the external fourth capacitor in parallel and then connecting the third capacitor and the first capacitor in series and dividing the voltage;
the output node of the boosting module is of a low level, and the voltage amplitude level in the negative half period is the negative voltage level amplitude obtained by connecting the third capacitor with the external fourth capacitor in series and dividing the third capacitor and the second capacitor in parallel.
In some embodiments, the PWM modulation module comprises: the fifth capacitor, the sixth capacitor, the first diode and the PMOS tube;
the drain electrode of the PMOS tube is connected with the first end of the fifth capacitor, and the source electrode of the PMOS tube is connected with the first end of the first diode and the first end of the sixth capacitor and is connected with the positive electrode of the direct current input voltage input end; the grid electrode of the PMOS tube is connected with the primary side clock control end;
and the second end of the fifth capacitor, the second end of the first diode and the second end of the sixth capacitor are connected with the negative electrode of the direct current input voltage input end.
In some embodiments, further comprising:
and the primary side feedback module is connected with the PWM modulation module and the boosting module and is used for collecting the voltage of the output node of the boosting module and controlling the working duty ratio or frequency of the primary side clock control end.
In some embodiments, the primary side feedback module comprises: the device comprises an amplifier, a reference voltage source, a first resistor, a second resistor and a filtering processing module;
the amplifier is connected with the PWM modulation module and the reference voltage source, and is also connected with the filtering processing module through the first resistor and the second resistor which are connected in parallel.
In some embodiments, the rectifying output module comprises: an inductor, a voltage stabilizing tube and a sixth capacitor;
the inductor is connected with the capacitor module, and is also connected with the first end of the voltage stabilizing tube and the first end of the sixth capacitor after being connected in parallel to the positive electrode of the direct current input voltage input end, and the second end of the voltage stabilizing tube and the second end of the sixth capacitor are connected to the negative electrode of the direct current input voltage input end.
In some embodiments, the voltage drop across the inductor is: (V) CD -ΔV)*ton＝V D *toff；V CD Positive periodic forward level amplitude voltage is input to the inductor; ton, toff=t D Ton is the initial on-chip primary side clock set point, V D For a target set point voltage level, Δv=l (Δi/ton), Δi being the amount of change that flows through the inductor when the inductor is rectifying on.
The open type integrated isolation power supply chip provided by the invention has at least the following beneficial effects:
the invention provides an open type integrated isolation power supply implementation mode, which effectively solves the problem of limitation by internally integrating a Y capacitor and a functional circuit and externally connecting a voltage dividing capacitor and a rectifying circuit in parallel, and improves the cost performance of the whole scheme of an integrated isolation power supply chip and the use flexibility of a system user.
Drawings
The above features, technical features, advantages and implementation of an open integrated isolated power chip will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clearly understandable manner.
FIG. 1 is a schematic diagram of one embodiment of an open-type integrated isolated power chip of the present invention;
FIG. 2 is a schematic diagram of a conventional differential circuit;
FIG. 3 is a schematic diagram of another embodiment of an open-type integrated isolated power chip according to the present invention;
FIG. 4 is a schematic diagram of the internal implementation of the primary side input side of the chip of the present invention;
FIG. 5 is a schematic diagram of the level amplitude waveforms of the nodes A, AB and B in the present invention;
FIG. 6 is a schematic diagram of the raw edge feedback circuit of the present invention;
FIG. 7 is a schematic diagram of an input side auxiliary circuit inside a chip according to the present invention;
FIG. 8 is a simplified REF configuration of the present invention;
FIG. 9 is a schematic diagram of a secondary side implementation of a chip in accordance with the present invention;
FIG. 10 is a schematic diagram of auxiliary wiring for secondary side integration within a chip in accordance with the present invention;
FIG. 11 is a schematic diagram of the amplitude waveforms of the CD and D node levels in the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
The conventional method is shown in FIG. 2, and the capacitors C1 and C2 are calculated by a capacitance series voltage division calculation formulaSerial connection corresponding to the partial pressure U between the C2 two polar plates O ＝(1/C2)/(1/C1+1/C2)*U IN The larger the corresponding voltage-dividing capacitance is, the smaller the divided voltage is; energy storage calculation formula E=C2×U between two polar plates of capacitor C2 O *U O /2. The capacitance series connection partial pressure calculation formula and the capacitance energy storage calculation formula can show that after the capacitors are connected in series, the capacitance value of each partial pressure capacitor needs to be improved in order to realize larger energy isolation transmission.
In this embodiment, in order to solve the problem that capacitive voltage division and capacitive energy storage are contradictory and the goal of transmitting larger energy, a Y capacitor with large capacitance, high withstand voltage and high cost performance is introduced to realize the isolation function and capacitive voltage division.
The Y capacitance is a safety capacitor and spans between L-G/N-G. The application occasion of the Y capacitor is an occasion which can not cause electric shock hazard after the capacitor fails.
In one embodiment, as shown in fig. 1, the present invention provides an open integrated isolated power chip, comprising:
the PWM modulation module 101 is connected to the positive electrode of the dc input voltage input terminal, and is configured to PWM-modulate the dc input voltage and output a PWM modulation signal.
Specifically, in this embodiment, a PWM-modulated overall energy transmission scheme is introduced, where DC voltage energy of the primary side input power VIN is modulated by PWM.
And the boosting module 102 is connected with the PWM adjusting module and is used for receiving the PWM modulation signal and outputting the boosted PWM modulation signal.
The PWM energy output by the PWM modulation module is raised by the booster circuit by the PWM level amplitude.
And the capacitor module 103 is connected with the boosting module and is used for carrying out isolation voltage division on the boosted PWM modulation signal and outputting the PWM modulation signal subjected to the isolation voltage division.
The boosted PWM energy is subjected to voltage division treatment by the Y capacitor and the voltage division capacitor, so that the PWM energy is transmitted to the secondary side in a large-amplitude isolation way, the PWM modulation energy of the voltage division capacitor coupling is subjected to rectification circuit treatment, the output DC voltage VOUT, and the limit value of the driving current capacity of the VOUT is approximately equal to the limit value of the voltage division capacitor energy storage divided by the voltage division value.
And the rectification output module 104 is connected with the capacitor module and is used for receiving the PWM modulation signal after the isolation voltage division and outputting the rectified direct current output voltage.
The invention provides an open type integrated isolation power supply implementation mode, which effectively solves the problem of limitation by internally integrating a Y capacitor and a functional circuit and externally connecting a voltage dividing capacitor and a rectifying circuit in parallel, and improves the cost performance of the whole scheme of an integrated isolation power supply chip and the use flexibility of a system user.
In one embodiment, the capacitive module includes: the first capacitor, the second capacitor, the third capacitor and the fourth capacitor.
Exemplary, a capacitive module comprising: the first capacitor CA1, the second capacitor C00, the third capacitor CB0, and the fourth capacitor C20.
The first capacitor CA1 and the second capacitor C00 are high withstand voltage Y capacitors, and the fourth capacitor C20 is a conventional capacitor, that is, a non-Y capacitor, and a common capacitor. The fourth capacitor C20 is an external extended parallel capacitor.
In addition, when the first capacitor CA1 is a large capacitance, the capacitance of the third capacitor CB0 and the fourth capacitor C20 connected in parallel can also be raised, so as to further realize higher voltage division and finally realize isolation transmission of larger energy.
The connection relation of the capacitor module is specifically described below:
the first capacitor is connected with the output end of the boosting module and the input end of the rectifying output module.
The second capacitor is connected with the negative electrode of the direct current input voltage input end and the negative electrode of the direct current output voltage input end.
One end of the third capacitor is located between the first capacitor and the input end of the rectification output module, and the other end of the third capacitor is located between the second capacitor and the input end of the direct current output voltage.
One end of the fourth capacitor is positioned between the third capacitor and the input end of the rectification output module, and the other end of the fourth capacitor is positioned between the second capacitor and the input end of the direct current output voltage; wherein the third capacitor and the fourth capacitor are connected in parallel.
In one embodiment, the effective positive amplitude voltage equivalent across the third capacitor CB0 and the fourth capacitor C20 is calculated as: v (V) C Node C positive level magnitude/(2 x (1-PWM duty cycle)), node C being the connection node of the first capacitor and the third capacitor.
In one embodiment, the capacitive module further comprises: and the power tube is connected with the third capacitor and the fourth capacitor.
The power transistor Q20 is connected to the third capacitor CB0 and the fourth capacitor C20, and has a clamping function. The power transistor Q20 may be an NMOS switch transistor.
In one embodiment, the output node of the boost module is at a high level, and the voltage amplitude level in the positive half period is a positive voltage level amplitude obtained by connecting the third capacitor and the external fourth capacitor in parallel and then connecting the third capacitor and the first capacitor in series and dividing the voltage;
the output node of the boosting module is of a low level, and the voltage amplitude level in the negative half period is the negative voltage level amplitude obtained by connecting the third capacitor with the external fourth capacitor in series and dividing the third capacitor and the second capacitor in parallel.
In one embodiment, as shown in fig. 3, the PWM modulation module includes: the fifth capacitor, the sixth capacitor, the first diode and the PMOS tube;
the drain electrode of the PMOS tube is connected with the first end of the fifth capacitor, and the source electrode of the PMOS tube is connected with the first end of the first diode and the first end of the sixth capacitor and is connected with the positive electrode of the direct current input voltage input end; the grid electrode of the PMOS tube is connected with a primary side clock control end clk 0;
and the second end of the fifth capacitor, the second end of the first diode and the second end of the sixth capacitor are connected with the negative electrode of the direct current input voltage input end. In one embodiment, as shown in fig. 6, the present invention further includes:
and the primary side feedback module is connected with the PWM modulation module and the boosting module and is used for collecting the voltage of the output node of the boosting module and controlling the working duty ratio or frequency of the primary side clock control end.
Wherein, the primary side feedback module includes: the circuit comprises an amplifier GAIN, a reference voltage source REF, a first resistor, a second resistor and a filtering processing module.
Specifically, the amplifier is connected with the PWM modulation module and the reference voltage source, and is also connected with the filtering processing module through the first resistor and the second resistor which are connected in parallel.
In one embodiment, as shown in fig. 9, the rectifying output module includes: an inductor L, a voltage stabilizing tube D21 and a sixth capacitor C21.
The inductor is connected with the capacitor module, and is further connected with the first end of the voltage stabilizing tube and the first end of the sixth capacitor after being connected in parallel to the positive electrode of the direct current input voltage input end, and the second end of the voltage stabilizing tube and the second end of the sixth capacitor are connected to the negative electrode of the direct current input voltage input end.
The sixth capacitor C21 is a voltage stabilizing capacitor.
In the rectifying output line, the zener diode D21 is matched with the PWM energy modulation mode in the overall line architecture, and the auxiliary clamp VOUT outputs a constant DC level target set value.
In the rectifying output line, the output voltage level after the inductance rectification is stabilized by the output-side stabilizing capacitor C21.
In one embodiment, the voltage drop across the inductor is: (V) CD -ΔV)*ton＝V D *toff；V CD Positive periodic forward level amplitude voltage is input to the inductor; ton, toff=t D Ton is the initial on-chip primary side clock set point, V D For a target set point voltage level, Δv=l (Δi/ton), Δi being the amount of change that flows through the inductor when the inductor is rectifying on.
In an embodiment, based on the foregoing embodiment, the present invention further provides an open integrated isolated power chip, as shown in fig. 3, which specifically includes:
in the integrated isolation power supply chip architecture, the inner part of the gray background block diagram is an integrated isolation power supply chip inner structure part, and the parallel voltage dividing capacitor, the rectifying output, VIN and VOUT are external matched structure parts of the integrated isolation power supply chip.
Specifically, the schematic illustration of the implementation architecture of the open-type isolated power chip with integrated capacity as shown in fig. 3:
the node A is an anode access port of direct current input voltage VIN of the integrated isolation power supply module, DC energy VIN of the node A is preprocessed into PWM modulation energy by PWM modulation, the PWM modulation energy corresponds to energy of the node AB, the node AB is lifted by a booster circuit, and the PWM modulation energy with a large amplitude is output to the node B.
CA1 and C00 are high withstand voltage Y capacitors, and under the condition that CA1 is a large capacitance value, the capacitance value of CB0 and C20 which are connected in parallel can also be raised, so that higher voltage division is realized, and finally, isolation transmission of larger energy is realized.
The node C is a large-amplitude PWM energy of the node B which is serially connected with the CA1 after being connected with the CB0 and the C20 in parallel; and the PWM energy divided by the node C is subjected to rectification and voltage stabilization treatment, so that the output of VOUT energy in the form of Direct Current (DC) voltage is realized.
C20 can be connected with a CB0 capacitor in parallel, the amplitude of the PWM level of the C node is adjusted, and the integral VOUT output target set value of PWM modulation is realized by matching with a rectifying output circuit part, so that the aim of external configuration of VOUT is achieved.
Therefore, the scheme realizes the Direct Current (DC) energy VIN of the node A on the primary side through the isolation voltage division of the Y capacitor, the isolation transmission to the VOUT on the secondary side, and the energy isolation transmission process of the DC-DC.
According to the scheme of the integrated circuit, the Y capacitor with high withstand voltage and large capacitance and the functional circuit are integrated in the power module, and the capacitor and the rectifying output circuit are externally connected in parallel in a voltage dividing mode, so that the function of the integrated isolated power module is realized.
The whole energy transmission scheme of PWM modulation is introduced, DC voltage energy of a power supply VIN is input to a primary side, PWM energy is modulated, a booster circuit lifts PWM level amplitude, and then Y capacitance and a voltage dividing capacitance are used for dividing the voltage, so that the PWM energy is transmitted to a secondary side in a large-amplitude isolation way, the PWM energy coupled with the voltage dividing capacitance is processed by a rectifying circuit, and the driving current capacity limit value of the output DC voltage VOUT is approximately equal to the limit value of the voltage dividing capacitance energy storage divided by the voltage dividing value.
In the chip architecture, the introduced Y capacitor has a large capacitance value and high withstand voltage, and the capacitance value of the voltage division capacitor can be synchronously and effectively improved, so that the isolation transmission function of larger energy is finally achieved.
In the chip architecture, only 2Y capacitors and functional circuits with larger volumes are integrated, the parallel voltage dividing capacitors and the rectification output circuits are external, and the whole integrated isolation power supply chip has smaller volume and external circuit parts compared with the existing isolation power supply module of the integrated isolation transformer, so that the device model can be freely combined by a system user, and a module scheme with higher cost performance is realized.
Specifically, the schematic diagram of the primary input side internal implementation of the chip shown in fig. 4 is as follows:
the node A is a primary side input power supply port, and the power supply for external power supply is DC energy.
In a primary side input side line, clk0 controls a power tube P tube switch, PWM energy modulation frequency of the whole power supply system is controlled, DC energy of an A node is converted into PWM modulation energy, the PWM modulation energy is stabilized to an AB node through a simplified voltage stabilizing processing line (a voltage stabilizing tube and a capacitor), and PWM modulation energy amplitude voltage of the AB node is boosted through a boosting line and is output to a B node as large-amplitude PWM modulation energy. The amplitude of the level of the AB node is the amplitude of the external input power supply voltage, and the frequency and the duty ratio of PWM modulation energy of the A node, the AB node and the B node are controlled by clk 0.
The schematic diagrams of the level amplitude waveforms of the a, AB, and B nodes shown in fig. 5 are as follows:
the level amplitude of the node B is the corresponding level after the level amplitude of the node AB is lifted by the booster circuit, and is N input level- (Vt11+ … +Vt1N), and the related frequency and the duty ratio are the same as those of the node AB.
Specifically, the primary feedback circuit diagram shown in fig. 6 is described as follows:
the primary side feedback circuit functions to sample the voltage amplitude variation of the node B and control the duty cycle or frequency of primary side clk 0:
when the output load of the secondary side is increased, CB0 and C20 capacitors store energy and unload, the voltage amplitude of the node C is reduced, the voltage amplitude of the node B is calculated by capacitor voltage division, the voltage amplitude of the node B is also reduced, and after the voltage amplitude of the node B is subjected to filtering treatment, the working frequency or the switching duty ratio of clk0 is increased through a gain amplifier;
when the output load of the secondary side is reduced, the CB0 and the C20 capacitors store energy and charge, the voltage amplitude of the C node is raised, the voltage amplitude of the B node is also raised, and after the voltage amplitude of the B node is filtered, the working frequency of clk0 or the switching duty ratio is reduced through the gain amplifier.
The explanation of the internal input-side auxiliary wiring diagram of the chip shown in fig. 7 is as follows:
the square wave phase of the AB node is complementary to the square wave phase of clk1, i.e., clk1 is low when the AB node is high.
As shown in fig. 8, the a node inputs power to a REF (bandgap reference), which is a base line in a semiconductor integrated circuit, a stable voltage reference line, and REF is a stable voltage reference.
Specifically, the explanation of the chip secondary side implementation circuit profile shown in fig. 9 is as follows:
PWM modulation energy obtained by partial pressure between two polar plates of CB0 capacitor:
the node B is high level, when the capacitor is charged, the voltage amplitude level in the positive half period is the level obtained by connecting the CB0 capacitor and the external C20 capacitor in parallel and then connecting the capacitor with the CA1 capacitor in series for voltage division; when the node B is at a low level, the capacitor discharges, the voltage amplitude of the GND1 point at the CB0 position in the negative half period is approximately equal to the amplitude of the negative voltage level obtained by connecting the CB0 capacitor with an external C20 capacitor in parallel and then connecting the capacitor with the C00 capacitor in series for voltage division.
Therefore, the voltage at two sides of the CB0 capacitor is directly used for output, negative pressure is generated at the CD node, and negative pressure is generated at the output level of the final VOUT. The function of the capacitive isolation type isolation power supply chip is to realize that the output of VOUT is carried, the output level is the DC level of constant voltage, and the influence of the negative half period of CB0 capacitor discharge on the constant DC level of the output of VOUT is required to be processed, so that a Q20 NMOS switching tube is introduced, and the switching of the constant DC level is controlled by CGND voltage.
The body diode portion of Q20 has a clamping function.
The node C is high level, a Q20 power switch is turned on, after the capacitor C20 is connected in parallel with the capacitor CB0, the capacitor C is connected in series with the capacitor CA1 to divide the PWM modulation energy, and then the PWM modulation energy is rectified and stabilized by a rectifying output circuit, and the target set value of the DC level is output by VOUT; the node C is low level, the Q20 power switch is closed, at the moment, the rectifying output line is freewheeling by the voltage stabilizing tube D21, the output capacitor C21 is stabilized, and the target set value of the output DC level of VOUT is maintained;
in the rectifying output line, the zener diode D21 is matched with the PWM energy modulation mode in the overall line architecture, and the auxiliary clamp VOUT outputs a constant DC level target set value.
In the rectifying output line, a voltage stabilizing capacitor C21 on the output side performs voltage stabilizing processing on the output voltage level after inductance rectification.
In the scheme, the whole PWM energy modulation implementation method comprises the following steps:
when the CD node is opened and is recorded as ton, the level amplitude of the CD node is the level amplitude obtained by the serial voltage division of the C node CB0 capacitor and the external C20 capacitor connected in parallel and the CA1 capacitor, and the corresponding PWM modulation energy frequency and the duty ratio are the initial set control frequency and the duty ratio of the primary side input side clk 0; at this time, PWM modulation energy of the CD node is rectified by an inductor L, and D21 is stabilized to charge C21; when the CD node is closed and is denoted as toff, the current direction on the rectifying inductor L is kept unchanged, the C21 port and the VOUT port are discharged, and D21 also continuously supplies power to the C21 port and the VOUT port.
The VOUT output energy is directly extracted from the C21 capacitor, when the C21 capacitor energy is released, the output level amplitude drops by a certain amplitude value, so that the voltage level amplitude drops between two polar plates of the CB0 and C20 voltage dividing capacitors are driven to be conducted to the node B, when the voltage level amplitude of the node B drops, the frequency or the duty ratio of the clk0 switch is synchronously adjusted, and a closed loop feedback loop of the VOUT output level is realized at intervals.
The voltage drop DeltaV across the rectifying inductor L can be obtained by using the volt-second balance calculation formula, i.e. the inductor is balanced on and off by volt-second, approximately (V) CD -ΔV)*ton＝V D * toff, where V CD The forward level amplitude voltage is a forward level amplitude voltage of a positive period of the CD node, and the amplitude of the forward level amplitude can be externally adjustable by adjusting the size of C20 to realize the amplitude of CB0 and C20 parallel capacitor voltage division; ton, toff=t D Ton is the initial on-chip clk0 set point, V D For the target set value VOUT voltage level, Δv=l (Δi/ton), where Δi is the amount of change in L flowing through the L rectifier when the L rectifier is on, and is approximately 1/2 times the inductance ripple current. The magnitude of the inductor ripple current is limited by the saturation current of the rectifying inductor L and the peak current available at node C. The peak current limit that the CD node can provide can be calculated approximately from the limit of stored energy divided by the effective positive amplitude voltage across the CB0 and C20 capacitors after the CB0 and C20 capacitors are connected in parallel.
The effective positive amplitude voltage at two ends of the CB0 and C20 parallel capacitors is equivalently calculated as V C The PWM duty ratio is approximately clk0 control duty ratio, and the calculation of the positive level amplitude of the C node has been described, so as to calculate the effective positive level value V at both ends of the CB0 capacitor C 。
The value of the VOUT setting value is adjusted by C20 and CB0, and then the external adjustable target of the VOUT setting value is achieved indirectly by changing the inductance of L and the clamp level of the voltage stabilizing tube under the condition of clk0 default switching frequency or duty ratio.
In the whole chip realization architecture, PWM energy modulation is used as a basic stone, and energy isolation transmission is realized by using capacitive series voltage division; the structure only uses the positive level energy storage period energy of the voltage dividing capacitor to supply the output.
Specifically, the auxiliary circuit profile integrated on the secondary side inside the chip as shown in fig. 10 is described as follows:
the high level of the C node, in the positive half period, the high amplitude level of the C node is divided by filtering, the conduction of the N pipe Q20 is controlled, and GND1 and GND2 are directly connected; in the low level of the C node and the negative half period, the negative voltage amplitude level of the C node is subjected to filtering voltage division, and is lower than the level potential bit at the GND2, the N tube Q20 cannot be conducted, at the moment, the GND2 and the GND1 are disconnected, and the negative voltage amplitude at the GND1 point cannot influence the level potential bit at the GND2 point.
The schematic diagram of the CD and D node level amplitude waveforms shown in fig. 11 is described as follows:
the forward PWM modulation energy of the CD node is rectified by an inductance L, regulated by a voltage stabilizing tube, clamped and regulated by an output capacitor, the output is converted into a DC level D node, and the level amplitude of the D node can be regulated by the voltage stabilizing tube.
The chip architecture has the advantages that:
the structure uses an integral PWM energy modulation mode to realize that a voltage division parallel capacitor and a secondary side output side rectifying circuit can be arranged externally, and a system user freely configures an output level according to application requirements, so that the application is flexible.
The structure uses the Y capacitance to realize the isolated transmission of energy, has small electromagnetic radiation and good EMC effect, does not rely on magnetic field conversion, and can integrate the Y capacitance with large capacitance value more cleanly and realize the isolated transmission of larger energy.
The isolation voltage endurance capacity of the chip architecture depends on different voltage endurance grades of the Y capacitor, such as 1.5kVrms, 3kVrms, 5kVrms and the like, and is matched with different creepage distance packaging forms, so that the combination of various chip packaging forms such as DFN4 with creepage distance of 2mm, NB SOIC4 with creepage distance of 4mm, WB SOIC4 with creepage distance of 8mm and the like can be realized.
The chip architecture can realize smaller packaging volume than an integrated isolation power module of an integrated isolation transformer, and saves the occupied area of a PCB at the board end of the system.
Under the external voltage division parallel capacitor and rectifying circuit, a system user can flexibly select the device type according to application requirements and own resources, and the cost performance of the whole isolation power supply scheme is improved.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. An open integrated isolated power chip, comprising:
the PWM modulation module is connected with the positive electrode of the direct current input voltage input end and is used for PWM modulating the direct current input voltage and outputting PWM modulation signals;
the boosting module is connected with the PWM adjusting module and used for receiving the PWM modulation signal and outputting the boosted PWM modulation signal;
the capacitor module is connected with the boosting module and used for carrying out isolation voltage division on the boosted PWM modulation signal and outputting the PWM modulation signal subjected to the isolation voltage division;
and the rectification output module is connected with the capacitor module and is used for receiving the PWM modulation signal after the isolation voltage division and outputting the rectified direct current output voltage.
2. An open-ended integrated isolated power supply chip according to claim 1, wherein the capacitive module comprises: the first capacitor, the second capacitor, the third capacitor and the fourth capacitor;
the first capacitor is connected with the output end of the boosting module and the input end of the rectifying output module;
the second capacitor is connected with the negative electrode of the direct current input voltage input end and the negative electrode of the direct current output voltage input end;
one end of the third capacitor is positioned between the first capacitor and the input end of the rectification output module, and the other end of the third capacitor is positioned between the second capacitor and the input end of the direct current output voltage;
one end of the fourth capacitor is positioned between the third capacitor and the input end of the rectification output module, and the other end of the fourth capacitor is positioned between the second capacitor and the input end of the direct current output voltage; wherein the third capacitor and the fourth capacitor are connected in parallel.
3. An open-type integrated isolated power supply chip according to claim 2, wherein the effective positive amplitude voltage equivalent across the third capacitor and the fourth capacitor parallel capacitor is calculated as: v (V) C Node C positive level magnitude/(2 x (1-PWM duty cycle)), node C being the connection node of the first capacitor and the third capacitor.
4. An open-ended integrated isolated power supply chip as defined in claim 2 wherein the capacitive module further comprises: and the power tube is connected with the third capacitor and the fourth capacitor.
5. An open-ended integrated isolated power chip as claimed in claim 2, wherein,
the output node of the boosting module is in a high level, and the voltage amplitude level in the positive half period is a positive voltage level amplitude obtained by connecting the third capacitor and the external fourth capacitor in series and dividing the third capacitor and the first capacitor in a voltage-dividing way;
the output node of the boosting module is of a low level, and the voltage amplitude level in the negative half period is the negative voltage level amplitude obtained by connecting the third capacitor with the external fourth capacitor in series and dividing the third capacitor and the second capacitor in parallel.
6. An open-ended integrated isolated power supply chip according to claim 1, wherein the PWM modulation module comprises: the fifth capacitor, the sixth capacitor, the first diode and the PMOS tube;
the drain electrode of the PMOS tube is connected with the first end of the fifth capacitor, and the source electrode of the PMOS tube is connected with the first end of the first diode and the first end of the sixth capacitor and is connected with the positive electrode of the direct current input voltage input end; the grid electrode of the PMOS tube is connected with the primary side clock control end;
and the second end of the fifth capacitor, the second end of the first diode and the second end of the sixth capacitor are connected with the negative electrode of the direct current input voltage input end.
7. An open-ended integrated isolated power supply chip as defined in claim 6, further comprising:
and the primary side feedback module is connected with the PWM modulation module and the boosting module and is used for collecting the voltage of the output node of the boosting module and controlling the working duty ratio or frequency of the primary side clock control end.
8. An open-ended integrated isolated power supply chip according to claim 7, wherein the primary side feedback module comprises: the device comprises an amplifier, a reference voltage source, a first resistor, a second resistor and a filtering processing module;
the amplifier is connected with the PWM modulation module and the reference voltage source, and is also connected with the filtering processing module through the first resistor and the second resistor which are connected in parallel.
9. An open-ended integrated isolated power supply chip as defined in claim 8, wherein the rectifying output module comprises: an inductor, a voltage stabilizing tube and a sixth capacitor;
the inductor is connected with the capacitor module, and is also connected with the first end of the voltage stabilizing tube and the first end of the sixth capacitor after being connected in parallel to the positive electrode of the direct current input voltage input end, and the second end of the voltage stabilizing tube and the second end of the sixth capacitor are connected to the negative electrode of the direct current input voltage input end.
10. An open-ended integrated isolated power supply chip according to claim 9 wherein the voltage drop across the inductor is: (V) CD -ΔV)*ton＝V D *toff；V CD Positive periodic forward level amplitude voltage is input to the inductor; ton, toff=t D Ton is the initial on-chip primary side clock set point, V D For a target set point voltage level, Δv=l (Δi/ton), Δi being the amount of change that flows through the inductor when the inductor is rectifying on.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311774246.XA CN117833604A (en) | 2023-12-22 | 2023-12-22 | Open type integrated isolation power supply chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311774246.XA CN117833604A (en) | 2023-12-22 | 2023-12-22 | Open type integrated isolation power supply chip |
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| CN117833604A true CN117833604A (en) | 2024-04-05 |
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| CN202311774246.XA Pending CN117833604A (en) | 2023-12-22 | 2023-12-22 | Open type integrated isolation power supply chip |
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| CN (1) | CN117833604A (en) |
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