CN117832274A - Pseudo grid array DEMOS device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a pseudo grid array DEMOS device and a manufacturing method thereof. The pseudo grid array DEMOS device comprises a silicon substrate, a well region, a source region, a drain region, a drift region, a pseudo grid array structure and a grid structure; a well region and a drift region are arranged on the silicon substrate; the grid structure covers part of the well region and part of the drift region; the source region is self-aligned to a first side of the gate structure; the pseudo grid array structure consists of a plurality of pseudo grid structures and is positioned above the drift region for adjusting the electric field of the drift region; the drain region is self-aligned with a second side of the dummy gate structure remote from the gate structure. The invention designs a pseudo grid array DEMOS device, which can effectively regulate and control the electric field at the drift region of the device, reduce the peak electric field at the junction of the grid and the drift region and greatly improve the breakdown voltage and the reliability of the device by adding the pseudo grid array above the drift region and giving different bias voltages to the pseudo grid.

Description

A pseudo gate array DEMOS device and its manufacturing method

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a pseudo gate array DEMOS device and a manufacturing method thereof.

Background technique

DEMOS (Drain Extended Metal Oxide Semiconductor) is a high-voltage MOS device with high breakdown voltage and low on-resistance. It is usually used as a high-voltage and high-power module in the BCD process.

As shown in Figure 1, taking n-type devices as an example, DEMOS usually includes:

The silicon substrate is composed of a p-type epitaxial substrate 100. Shallow trench isolation oxides 101a, 101b and 101c are formed on the surface of the silicon substrate. The active area of the DEMOS device is isolated by the shallow trench isolation oxide.

The well region is composed of a p-type well 102 .

The drift region is composed of an n-type drift region 103 .

The gate structure 106 is composed of a gate oxide layer, a gate polysilicon layer and a silicon nitride sidewall, and the gate structure covers a portion of the p-type well 102 and a portion of the n-type drift region 103 .

The body region is composed of a p-type heavily doped region 104 on the surface of the p-type well 102;

A source region, which is composed of an n-type heavily doped region 105a on the surface of the p-type well 102, wherein the source region is self-aligned with the first side of the gate structure;

The drain region is composed of an n-type heavily doped region 105 b on the surface of the n-type drift region 103 . The drain region is separated from the second side of the gate structure by a distance.

With the rapid development of industries such as electric vehicles and smart driving, people have put forward higher requirements for high voltage resistance and high reliability of automotive chips. However, the internal electric field of the above-mentioned traditional DEMOS devices is unevenly distributed, and the peak electric field is concentrated at the junction of the gate and the drift region, which greatly limits the breakdown voltage of the device and damages the reliability of the device.

Summary of the invention

In order to solve the problems of low breakdown voltage and insufficient reliability of traditional DEMOS devices, the present invention provides a pseudo gate array DEMOS device and a manufacturing method thereof.

In a first aspect of the present invention, a pseudo gate array DEMOS device is provided, comprising a silicon substrate, a well region, a source region, a drain region, a drift region, a pseudo gate array structure and a gate structure. A well region and a drift region are provided on the silicon substrate; the gate structure covers part of the well region and part of the drift region; the source region is self-aligned with a first side of the gate structure;

The dummy gate array structure is composed of a plurality of dummy gate structures, and all of them are located above the drift region, and are used to adjust the electric field of the drift region, thereby reducing the peak electric field at the junction of the gate and the drift region;

The drain region is self-aligned with a second side of the dummy gate structure away from the gate structure.

Furthermore, each of the dummy gate structures includes a gate oxide layer, a gate polysilicon layer and a silicon nitride sidewall.

Furthermore, the array density of the dummy gate array structure near the gate structure is greater than the array density far from the gate structure.

Furthermore, the bias voltages of the pseudo-gate structures are the same and adjustable.

A second aspect of the present invention provides a method for manufacturing a pseudo gate array DEMOS device, comprising the following steps:

Step 301, providing an epitaxial substrate, locally oxidizing and isolating on the substrate, and defining a DEMOS device active area;

Step 302, respectively implanting p-type ions and n-type ions into the DEMOS region and diffusing them to form a well region and a drift region of the device;

Step 303, growing a gate oxide layer, depositing polysilicon, depositing silicon nitride sidewalls, and forming a gate structure and a pseudo gate array structure;

Step 304 , implanting n-type ions and p-type ions at high doses to form a source region, a drain region, and a body region.

Beneficial effects of the present invention:

The present invention designs a pseudo gate array DEMOS device without adding additional masks and additional process steps. By adding a pseudo gate array above the drift region and giving different bias voltages to the pseudo gate, the device can effectively regulate the electric field in the drift region of the device, reduce the peak electric field at the junction of the gate and the drift region, and greatly improve the breakdown voltage and reliability of the device.

In addition, since the electric field strength is higher the closer to the gate, the pseudo-gate array is arranged densely near the gate and sparsely far away. This can reduce the number of pseudo-gates while ensuring that the breakdown voltage and reliability remain unchanged, thereby reducing the device area and increasing the device density within the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural diagram of a DEMOS device in the prior art;

FIG2 is a structural diagram of a DEMOS device in an embodiment of the present application;

FIG. 3 is a diagram of the manufacturing process of a DEMOS device in an embodiment of the present application.

Detailed ways

The present invention is further described below in conjunction with the accompanying drawings and embodiments.

The embodiment of the present application provides a pseudo gate array DEMOS device, as shown in FIG2. Taking an n-type device as an example, it at least includes:

The silicon substrate is composed of a p-type epitaxial substrate 200. Shallow trench isolation oxides 201a, 201b and 201c are formed on the surface of the silicon substrate. The active area of the DEMOS device is isolated by the shallow trench isolation oxide.

The well region is composed of a p-type well 202 .

The drift region is composed of an n-type drift region 203 .

The gate structure 206 is composed of a gate oxide layer, a gate polysilicon layer and a silicon nitride sidewall, and the gate structure covers a portion of the p-type well 202 and a portion of the n-type drift region 203 .

The pseudo gate array structure is composed of pseudo gate structures 207a, 207b, and 207c, wherein each pseudo gate structure is composed of a gate oxide layer, a gate polysilicon layer, and a silicon nitride sidewall. The pseudo gate structure 207a is close to the pseudo gate structure 207b, and the pseudo gate structure 207b is far from the pseudo gate structure 207c. All pseudo gate structures are located above the drift region 203, and all pseudo gate structures have the same bias voltage, and the bias voltage is adjustable.

The body region is composed of a p-type heavily doped region 204 on the surface of the p-type well 202 .

A source region, which is composed of an n-type heavily doped region 205 a on the surface of the p-type well 202 , is self-aligned with the first side of the gate structure.

In this embodiment, the left side of the gate structure or the dummy gate structure is defined as the first side, and the right side of the gate structure or the dummy gate structure is defined as the second side. Of course, those skilled in the art will appreciate that the above two sides are interchangeable and do not constitute a limitation of the present invention.

The drain region is composed of an n-type heavily doped region 205 b on the surface of the n-type drift region 203 , and the drain region is self-aligned with the second side of the dummy gate structure 207 c .

If it is a p-type device, then

a well region, which is composed of an n-type well 202;

a drift region, which is composed of a p-type drift region 203;

The body region is composed of an n-type heavily doped region 204 on the surface of the n-type well 202;

A source region, which is composed of a p-type heavily doped region 205a on the surface of the n-type well 202, wherein the source region is self-aligned with the first side of the gate structure;

The drain region is composed of a p-type heavily doped region 205 b on the surface of the p-type drift region 203 , and the drain region is self-aligned with the second side of the dummy gate structure 207 c .

The rest remains unchanged.

The present application also provides a method for manufacturing a pseudo gate array DEMOS device. As shown in FIG3 , it shows a flow chart of a method for manufacturing a pseudo gate array DEMOS device provided in the present application, the method is used to manufacture the pseudo gate array DEMOS device shown in FIG2 , and the method at least includes:

Step 301 , providing a p-type epitaxial substrate, locally oxidizing and isolating on the substrate, and defining a DEMOS device active region.

Step 302 : P-type ions and n-type ions are respectively implanted and diffused in the DEMOS region to form a p-type well and an n-type drift region of the device.

Step 303, growing a gate oxide layer, depositing polysilicon, depositing silicon nitride sidewalls, and forming a gate structure and a dummy gate array structure.

Step 304 , implanting n-type ions and p-type ions at high doses to form a source region, a drain region, and a body region.

The above are preferred embodiments of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims (5)

1. A dummy gate array DEMOS device, characterized by: the device comprises a silicon substrate, a well region, a source region, a drain region, a drift region, a pseudo grid array structure and a grid structure;

a well region and a drift region are arranged on the silicon substrate; the grid structure covers part of the well region and part of the drift region; the source region is self-aligned to a first side of the gate structure;

the pseudo grid array structure consists of a plurality of pseudo grid structures and is positioned above the drift region and used for adjusting the electric field of the drift region so as to reduce the peak electric field at the junction of the grid and the drift region;

the drain region is self-aligned with a second side of the dummy gate structure remote from the gate structure.

2. A high frequency DEMOS device as claimed in claim 1, wherein: each dummy gate structure comprises a gate oxide layer, a gate polysilicon layer and a silicon nitride side wall.

3. A high frequency DEMOS device according to claim 1 or 2, wherein: the array density of the pseudo grid array structure is greater near the grid structure than the array density of the pseudo grid array structure far away from the grid structure.

4. A high frequency DEMOS device according to any one of claims 3, wherein: the bias voltages of the dummy gate structures are the same and are adjustable.

5. A method of fabricating a dummy gate array DEMOS device according to any one of claims 1 to 4, comprising the steps of:

step 301, providing an epitaxial substrate, and locally oxidizing and isolating the epitaxial substrate to define an active region of a DEMOS device;

step 302, p-type ions and n-type ions are respectively injected and diffused in a DEMOS region to form a well region and a drift region of the device;

step 303, growing a gate oxide layer, depositing polysilicon, and depositing a silicon nitride side wall to form a gate structure and a pseudo gate array structure;

and 304, implanting n-type ions and p-type ions in large doses respectively to form a source region, a drain region and a body region.