CN117832274A - Pseudo grid array DEMOS device and manufacturing method thereof - Google Patents
Pseudo grid array DEMOS device and manufacturing method thereof Download PDFInfo
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- CN117832274A CN117832274A CN202311772058.3A CN202311772058A CN117832274A CN 117832274 A CN117832274 A CN 117832274A CN 202311772058 A CN202311772058 A CN 202311772058A CN 117832274 A CN117832274 A CN 117832274A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000005684 electric field Effects 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 210000000746 body region Anatomy 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a pseudo grid array DEMOS device and a manufacturing method thereof. The pseudo grid array DEMOS device comprises a silicon substrate, a well region, a source region, a drain region, a drift region, a pseudo grid array structure and a grid structure; a well region and a drift region are arranged on the silicon substrate; the grid structure covers part of the well region and part of the drift region; the source region is self-aligned to a first side of the gate structure; the pseudo grid array structure consists of a plurality of pseudo grid structures and is positioned above the drift region for adjusting the electric field of the drift region; the drain region is self-aligned with a second side of the dummy gate structure remote from the gate structure. The invention designs a pseudo grid array DEMOS device, which can effectively regulate and control the electric field at the drift region of the device, reduce the peak electric field at the junction of the grid and the drift region and greatly improve the breakdown voltage and the reliability of the device by adding the pseudo grid array above the drift region and giving different bias voltages to the pseudo grid.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a pseudo grid array DEMOS device and a manufacturing method thereof.
Background
DEMOS (Drain Extended Metal Oxide Semiconductor, drain-extended metal oxide semiconductor) is a high voltage MOS device with a high breakdown voltage and low on-resistance, typically used as a high voltage high power module in BCD processes.
As shown in fig. 1, taking an n-type device as an example, DEMOS generally comprises:
and a silicon substrate, which is composed of a p-type epitaxial substrate 100, wherein shallow trench isolation oxides 101a, 101b and 101c are formed on the surface of the silicon substrate, and the active region of the DEMOS device is isolated by the shallow trench isolation oxides.
A well region, which is comprised of p-type well 102.
A drift region consisting of an n-type drift region 103.
The gate structure 106 is composed of a gate oxide layer, a gate polysilicon layer and silicon nitride sidewalls, and covers a portion of the p-type well 102 and a portion of the n-type drift region 103.
A body region consisting of a p-type heavily doped region 104 on the surface of the p-type well 102;
a source region consisting of an n-type heavily doped region 105a of the surface of the p-type well 102, the source region being self-aligned to a first side of the gate structure;
and a drain region consisting of an n-type heavily doped region 105b on the surface of the n-type drift region 103, said drain region being spaced apart from the second side of the gate structure.
With the rapid development of industries such as electric automobiles and intelligent driving, people have put higher demands on high withstand voltage and high reliability of automobile chips. However, the electric field distribution inside the conventional DEMOS device is uneven, and the peak electric field is concentrated at the junction of the gate and the drift region, so that the breakdown voltage of the device is greatly limited and the reliability of the device is damaged.
Disclosure of Invention
In order to solve the problems of low breakdown voltage and insufficient reliability of the traditional DEMOS device, the invention provides a pseudo grid array DEMOS device and a manufacturing method thereof.
In a first aspect of the present invention, a dummy gate array DEMOS device is provided that includes a silicon substrate, a well region, a source region, a drain region, a drift region, a dummy gate array structure, and a gate structure. A well region and a drift region are arranged on the silicon substrate; the grid structure covers part of the well region and part of the drift region; the source region is self-aligned to a first side of the gate structure;
the pseudo grid array structure consists of a plurality of pseudo grid structures and is positioned above the drift region and used for adjusting the electric field of the drift region so as to reduce the peak electric field at the junction of the grid and the drift region;
the drain region is self-aligned with a second side of the dummy gate structure remote from the gate structure.
Further, each dummy gate structure comprises a gate oxide layer, a gate polysilicon layer and a silicon nitride side wall.
Further, the array density of the pseudo grid array structure is greater near the grid structure than far from the grid structure.
Further, the bias voltages of the dummy gate structures are the same and are adjustable.
In a second aspect of the present invention, a method for fabricating a DEMOS device of a dummy gate array is provided, including the steps of:
step 301, providing an epitaxial substrate, and locally oxidizing and isolating the epitaxial substrate to define an active region of a DEMOS device;
step 302, p-type ions and n-type ions are respectively injected and diffused in a DEMOS region to form a well region and a drift region of the device;
step 303, growing a gate oxide layer, depositing polysilicon, and depositing a silicon nitride side wall to form a gate structure and a pseudo gate array structure;
and 304, implanting n-type ions and p-type ions in large doses respectively to form a source region, a drain region and a body region.
The invention has the beneficial effects that:
according to the invention, under the condition that no extra photomask and extra process steps are added, the pseudo grid array DEMOS device is designed, and by adding the pseudo grid array above the drift region and giving different bias voltages to the pseudo grid, the electric field at the drift region of the device can be effectively regulated and controlled, the peak electric field at the junction of the grid and the drift region is reduced, and the breakdown voltage and reliability of the device are greatly improved.
In addition, the closer to the grid electrode, the higher the electric field intensity, so that the pseudo grid array close to the grid electrode is arranged densely, and the arrangement at the far position is arranged sparsely, so that the number of the pseudo grid electrodes can be reduced under the condition that the breakdown voltage and the reliability are unchanged, the area of a device is reduced, and the density of the device in a chip is improved.
Drawings
Fig. 1 is a block diagram of a DEMOS device in the prior art;
fig. 2 is a structural diagram of a DEMOS device in an embodiment of the present application;
fig. 3 is a schematic diagram of a DEMOS device manufacturing process according to an embodiment of the present application.
Detailed Description
The invention will be further described with reference to the drawings and examples.
The embodiment of the application provides a pseudo grid array DEMOS device, as shown in figure 2. Taking an n-type device as an example, at least the n-type device includes:
and a silicon substrate, which is composed of a p-type epitaxial substrate 200, wherein shallow trench isolation oxides 201a, 201b and 201c are formed on the surface of the silicon substrate, and the active region of the DEMOS device is isolated by the shallow trench isolation oxides.
Well region, which is comprised of p-type well 202.
A drift region consisting of an n-type drift region 203.
The gate structure 206 is composed of a gate oxide layer, a gate polysilicon layer and silicon nitride sidewalls, and covers a portion of the p-well 202 and a portion of the n-type drift region 203.
And the dummy gate array structure consists of dummy gate structures 207a, 207b and 207c, wherein each dummy gate structure consists of a gate oxide layer, a gate polysilicon layer and a silicon nitride side wall. Wherein dummy gate structure 207a is closer to dummy gate structure 207b, dummy gate structure 207b is farther from dummy gate structure 207c, all dummy gate structures are above drift region 203, all dummy gate structures have a specifically same bias voltage, and the bias voltage is adjustable.
A body region consisting of a p-type heavily doped region 204 at the surface of the p-type well 202.
A source region consisting of an n-type heavily doped region 205a on the surface of the p-type well 202, the source region being self-aligned to the first side of the gate structure.
In this embodiment, the left side of the gate structure or the dummy gate structure is defined as the first side, and the right side of the gate structure or the dummy gate structure is defined as the second side, which, of course, is understood by those skilled in the art to be exchangeable, and does not limit the present invention.
A drain region consisting of an n-type heavily doped region 205b at the surface of the n-type drift region 203, said drain region being self-aligned to the second side of said dummy gate structure 207 c.
In the case of a p-type device, then
A well region composed of an n-type well 202;
a drift region composed of a p-type drift region 203;
a body region consisting of an n-type heavily doped region 204 on the surface of the n-type well 202;
a source region consisting of a p-type heavily doped region 205a of the surface of the n-type well 202, the source region being self-aligned to a first side of the gate structure;
a drain region consisting of a p-type heavily doped region 205b at the surface of the p-type drift region 203, said drain region being self-aligned to the second side of said dummy gate structure 207 c.
The rest is unchanged.
The embodiment of the application also provides a manufacturing method of the pseudo grid array DEMOS device. As shown in fig. 3, a flowchart of a method for fabricating a dummy gate array DEMOS device according to an embodiment of the present application is shown, where the method is used to fabricate the dummy gate array DEMOS device shown in fig. 2, and the method at least includes:
step 301 provides a p-type epitaxial substrate, and local oxidation isolation is performed on the substrate to define a DEMOS device active region.
In step 302, p-type ions and n-type ions are respectively implanted and diffused in the DEMOS region to form a p-type well and an n-type drift region of the device.
And 303, growing a gate oxide layer, depositing polysilicon, and depositing a silicon nitride side wall to form a gate structure and a pseudo gate array structure.
And 304, implanting n-type ions and p-type ions in large doses respectively to form a source region, a drain region and a body region.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (5)
1. A dummy gate array DEMOS device, characterized by: the device comprises a silicon substrate, a well region, a source region, a drain region, a drift region, a pseudo grid array structure and a grid structure;
a well region and a drift region are arranged on the silicon substrate; the grid structure covers part of the well region and part of the drift region; the source region is self-aligned to a first side of the gate structure;
the pseudo grid array structure consists of a plurality of pseudo grid structures and is positioned above the drift region and used for adjusting the electric field of the drift region so as to reduce the peak electric field at the junction of the grid and the drift region;
the drain region is self-aligned with a second side of the dummy gate structure remote from the gate structure.
2. A high frequency DEMOS device as claimed in claim 1, wherein: each dummy gate structure comprises a gate oxide layer, a gate polysilicon layer and a silicon nitride side wall.
3. A high frequency DEMOS device according to claim 1 or 2, wherein: the array density of the pseudo grid array structure is greater near the grid structure than the array density of the pseudo grid array structure far away from the grid structure.
4. A high frequency DEMOS device according to any one of claims 3, wherein: the bias voltages of the dummy gate structures are the same and are adjustable.
5. A method of fabricating a dummy gate array DEMOS device according to any one of claims 1 to 4, comprising the steps of:
step 301, providing an epitaxial substrate, and locally oxidizing and isolating the epitaxial substrate to define an active region of a DEMOS device;
step 302, p-type ions and n-type ions are respectively injected and diffused in a DEMOS region to form a well region and a drift region of the device;
step 303, growing a gate oxide layer, depositing polysilicon, and depositing a silicon nitride side wall to form a gate structure and a pseudo gate array structure;
and 304, implanting n-type ions and p-type ions in large doses respectively to form a source region, a drain region and a body region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311772058.3A CN117832274A (en) | 2023-12-21 | 2023-12-21 | Pseudo grid array DEMOS device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311772058.3A CN117832274A (en) | 2023-12-21 | 2023-12-21 | Pseudo grid array DEMOS device and manufacturing method thereof |
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| CN117832274A true CN117832274A (en) | 2024-04-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311772058.3A Pending CN117832274A (en) | 2023-12-21 | 2023-12-21 | Pseudo grid array DEMOS device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118263330A (en) * | 2024-05-31 | 2024-06-28 | 钰泰半导体股份有限公司 | DMOS device capable of being subjected to bidirectional voltage withstanding |
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2023
- 2023-12-21 CN CN202311772058.3A patent/CN117832274A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118263330A (en) * | 2024-05-31 | 2024-06-28 | 钰泰半导体股份有限公司 | DMOS device capable of being subjected to bidirectional voltage withstanding |
| CN118263330B (en) * | 2024-05-31 | 2024-08-06 | 钰泰半导体股份有限公司 | DMOS device capable of being subjected to bidirectional voltage withstanding |
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