CN117831478A - Panel driving circuit, display device and display driving method - Google Patents

Abstract

The application relates to a panel driving circuit, a display device and a display driving method, wherein the circuit comprises: the time sequence controller is used for transmitting at least one data pair and generating at least one control signal group, and the control signal group comprises a plurality of control signals; the driving chip comprises a data processing unit, and the data processing unit is electrically connected with the time sequence controller through at least three connecting components so as to receive at least one data pair transmitted by the connecting components; the different connection components are respectively positioned at different positions of the driving chip, and each connection component comprises at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal, so that the transmission state of at least three connection components is controlled based on a plurality of control signals. The driving cost can be reduced, and the verification and introduction time of the driving chip can be shortened.

Description

Panel driving circuit, display device and display driving method

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a panel driving circuit, a display device, and a display driving method.

Background

Chip On Glass (COG) is a packaging technique for packaging a driver Chip On Glass. In order to meet different frame requirements of a Narrow frame (NB) display product, two routing modes exist for the COG driver chip data pair: one is to route from the middle position of the driving chip opposite to the receiving circuit Rx, and the number of the receiving circuits Rx is one at the moment; the other is to route wires from two sides of the driving chip, and at this time, a receiving circuit Rx is respectively disposed on two sides of the driving chip, i.e. the number of the receiving circuits Rx is two. As a result, even if the specifications of the display panels are the same, at least two different driving chips need to be developed in order to meet different narrow frame requirements or achieve other development purposes, so that the driving cost is increased and the verification and introduction time of the driving chips is also increased.

Disclosure of Invention

In view of this, the application provides a panel driving circuit, a display device and a display driving method, which can reduce the number of receiving circuits and clock data recovery circuits in a driving chip, and adjust a connection component in an enabled state by using a control line according to different product requirements, thereby reducing driving cost and shortening verification and import time of the driving chip, and further improving development efficiency of panel driving.

According to an aspect of the present application, there is provided a panel driving circuit electrically connected to a display panel, the panel driving circuit including: a timing controller for transmitting at least one data pair and generating at least one control signal group, wherein the control signal group comprises a plurality of control signals; the driving chip comprises a data processing unit, and the data processing unit is electrically connected with the time sequence controller through at least three connecting components so as to receive at least one data pair transmitted by the connecting components; the driving chip is arranged on the driving device, wherein different connecting components are respectively positioned at different positions of the driving chip, and each connecting component comprises at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal so as to control the transmission states of at least three connecting components based on a plurality of control signals.

According to another aspect of the present application, there is provided a display device, wherein the display device includes a display panel and the panel driving circuit.

According to another aspect of the present application, there is provided a display driving method applied to the panel driving circuit, the display driving method including: judging the working mode of the time sequence controller according to the target frame of the display panel, wherein the working mode comprises a first working mode and a second working mode; in the first working mode, at least one control line in at least three connecting assemblies is controlled to be in an enabling state; and in the second working mode, controlling at least two control lines in at least three connecting assemblies to be in an enabling state, wherein the control lines in the enabling state in the first working mode are different from the control lines in the enabling state in the second working mode.

Through making receiving circuit pass through at least three coupling assembling electricity and connect in time schedule controller to with different coupling assembling respectively be located the different positions of driver chip, and then based on the transmission state of a plurality of control signal control at least three coupling assembling, according to the each aspect of this application can reduce the quantity that sets up receiving circuit and clock data recovery circuit inside the driver chip, and utilize the control line to adjust the coupling assembling that is in the enabling state according to different product demands, both reduced driving cost, shortened driver chip again and verified leading-in time, thereby improve panel drive's development efficiency.

Drawings

Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a first COG wiring method of the related art.

Fig. 2 shows a schematic diagram of a second COG routing of the related art.

Fig. 3 shows a schematic diagram of a panel driving architecture of an embodiment of the present application.

Fig. 4 shows an internal block diagram of a driver chip of an embodiment of the present application.

Fig. 5 shows a schematic diagram of a driving chip according to an embodiment of the present application.

Fig. 6 shows a flowchart of a display driving method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements or interaction relationship between the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials. In some instances, methods, means, elements, and circuits have not been described in detail as not to unnecessarily obscure the present application.

Fig. 1 shows a schematic diagram of a first COG wiring method of the related art.

As shown in fig. 1, a plurality of Input pads (Input pads) and a plurality of Output pads (Output pads) are provided on both sides of the driving chip in the width direction in a plan view. In the length direction of the driving chip, each input pad and each output pad are arranged along the length direction of the driving chip.

The driving chip is internally provided with a data processing unit, and the data processing unit comprises a receiving circuit Rx and a clock data recovery circuit (Clock and Data Recovery, CDR) electrically connected with the receiving circuit Rx. The signal received by the receiving circuit Rx may be forwarded to a clock data recovery circuit CDR for further processing. The signal received by the receiving circuit Rx is Rx1N, rx1P, rx0N, rx P, which is two data pairs, rx1N, rx P is one data pair, and Rx0N, rx P is another data pair.

The two data pairs of fig. 1 are respectively transmitted through the four input pads, and are each arranged at a middle position of the data processing unit, i.e., directly below the data processing unit of fig. 1.

Fig. 2 shows a schematic diagram of a second COG routing of the related art.

As shown in fig. 2, a plurality of Input pads (Input pads) and a plurality of Output pads (Output pads) are provided on both sides of the driving chip in the width direction in a plan view. In the length direction of the driving chip, each input pad and each output pad are arranged along the length direction of the driving chip.

Unlike fig. 1, two data processing units are disposed on two sides of the driving chip of fig. 2, each data processing unit includes a receiving circuit Rx and a clock data recovery circuit CDR corresponding to the receiving circuit Rx, and the receiving circuit Rx is electrically connected to the corresponding clock data recovery circuit CDR.

Wherein, the signal received by the left data processing unit is Rx0P-L, rx0N-L, rx1N-L, rx1P-L, rx-L-EN, and the signal received by the right data processing unit is Rx0P-R, rx0N-R, rx1N-R, rx1P-R, rx-R-EN. The receiving circuits in the data processing units on the left are enabled by Rx-L-EN and the receiving circuits in the data processing units on the right are enabled by Rx-R-EN. The signal received by the data processing unit on the left and the signal received by the data processing unit on the right have two data pairs.

The left two data pairs and a control signal Rx-L-EN of fig. 2 are respectively transmitted through five input pads, the right two data pairs and a control signal Rx-R-EN are respectively transmitted through five input pads, and the left five input pads and the right five input pads are respectively located at both sides of the driving chip, for example, the lower left corner and the lower right corner of fig. 2.

In practical applications, both the layouts of fig. 1 and 2 may affect the need to display a narrow bezel of the product. Therefore, even if the technical specifications of the display panels are the same, at least two different driving chips need to be developed in order to adapt to different narrow frame requirements or achieve other development purposes, so that the driving cost is increased, and the verification and introduction time of the driving chips is also prolonged.

The application provides a panel drive circuit, panel drive circuit electricity is connected in the display panel, panel drive circuit includes: a timing controller for transmitting at least one data pair and generating at least one control signal group, wherein the control signal group comprises a plurality of control signals; the driving chip comprises a data processing unit, and the data processing unit is electrically connected with the time sequence controller through at least three connecting components so as to receive at least one data pair transmitted by the connecting components; the driving chip is arranged on the driving device, wherein different connecting components are respectively positioned at different positions of the driving chip, and each connecting component comprises at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal so as to control the transmission states of at least three connecting components based on a plurality of control signals.

Through making receiving circuit pass through at least three coupling assembling electricity and connect in time schedule controller to with different coupling assembling respectively be located driving chip's different positions, and then based on the transmission state of a plurality of control signal control at least three coupling assembling, this application embodiment can reduce the quantity that sets up receiving circuit and clock data recovery circuit inside the driving chip, and utilize the control line to adjust the coupling assembling that is in enabling state according to different product demands, both reduced driving cost, shortened driving chip again and verified leading-in time, thereby improve panel drive's development efficiency.

Fig. 3 shows a schematic diagram of a panel driving architecture of an embodiment of the present application. As shown in fig. 3, the panel driving circuit of the embodiment of the present application is electrically connected to the display panel 1. The display panel 1 will be described below as an example of a liquid crystal display panel, but those skilled in the art will understand that the present application is not limited to the type of display panel.

The display panel 1 may include a plurality of pixels arranged in rows and columns, each of the pixels is electrically connected to a data line, and each of the pixels in columns is electrically connected to a scan line. The data lines may be transmitted with positive polarity data or negative polarity data. Alternatively, the driving manner of the display panel may be a column inversion manner.

In an embodiment, the driving chip of the present application may be the first driving chip 21 or the second driving chip 22. The first driving chip 21 may be a source driver, and the second driving chip 22 may be a gate driver. The panel driving circuit may include the first driving chip 21 and the second driving chip 22.

In an embodiment, the first driving chip 21 and the second driving chip 22 are packaged on the glass substrate of the display panel by a chip on glass COG method. Optionally, the timing controller may be packaged on the glass substrate of the display panel by a chip on glass COG method, so that space and process can be further saved. The chip is directly packaged on the glass through the anisotropic conductive adhesive in the COG mode, so that the chip conductive bumps and the transparent conductive pads on the glass are interconnected and packaged together. Alternatively, a plurality of the pixels may be disposed on a glass substrate of the display panel, and the first driving chip 21, the second driving chip 22, and the timing controller may be disposed at one side of the plurality of the pixels.

In one embodiment, the timing controller is configured to transmit at least one data pair and generate at least one control signal group, where the control signal group includes a plurality of control signals. Each of the data pairs may include the positive polarity data and negative polarity data. The positive polarity data and the negative polarity data may be of the same pixel, with the difference that different moments are used to drive the pixel. The number of data pairs may be determined based on the number of pixels or, alternatively, may be related to the resolution of the display panel. Optionally, each control signal group comprises 3 control signals. It will be appreciated that the present application is not limited to the number of data pairs.

In an embodiment, the driving chip includes a data processing unit 201, where the data processing unit 201 includes a receiving circuit 211 and a clock data recovery circuit 212 electrically connected to the receiving circuit 211, where the receiving circuit 211 is electrically connected to the timing controller through at least three connection components, and the clock data recovery circuit 212 is used for further processing at least one data pair received by the receiving circuit 211.

In this application, the timing controller may receive the original display data from the motherboard, where the original display data does not conform to the data format required by the first driver chip 21 and the second driver chip 22, so that the timing controller is required to process the original display data to generate the display data conforming to the data format required by the first driver chip 21 and the second driver chip 22, and then send the processed display data to the first driver chip 21 and the second driver chip 22. The first driving chip 21 outputs the positive polarity data and the negative polarity data, and the second driving chip 22 outputs a scan signal. In some embodiments, the scan signal may also be considered a data modality.

After the first driving chip 21 receives the display data processed by the timing controller, it is necessary to further process the display data by using the clock data recovery circuit 212, thereby generating positive polarity data and negative polarity data that meet the requirements. The clock data recovery circuit 212 can recover clock signals and data information from the serial data stream by sampling, clock recovery, signal demodulation, etc. the clock data recovery circuit is operative to recover normal clock and data information from the serial data signal. In high-speed serial communication, due to attenuation of transmission signals, clock signals and data signals are severely disturbed and deformed, while the clock data recovery circuit 212 performs clock extraction and recovery on received data through internal circuit design and algorithm, and samples and demodulates the data at the correct time so as to recover the original clock and data information. There is also a similar process inside the second driving chip 22 as inside the first driving chip 21.

In one embodiment, the at least three connection assemblies include a first connection assembly, a second connection assembly, and a third connection assembly. The receiving circuit 211 is electrically connected to the timing controller through three connection components, where the three connection components are respectively: the first connection assembly, the second connection assembly and the third connection assembly.

The number of the data lines of the first connection assembly, the second connection assembly and the third connection assembly is the same, and the number of the control lines of the first connection assembly, the second connection assembly and the third connection assembly is the same. Optionally, the number of control lines of the first connection assembly, the second connection assembly and the third connection assembly is 1, that is, 1 control line is disposed in each connection assembly.

Taking fig. 3 as an example, for the first driving chip 21, the first connection assembly may include a first control line L1, the second connection assembly may include a second control line L2, and the third connection assembly may include a third control line L3; for the second driving chip 22, the first connection assembly may include a fourth control line L4, the second connection assembly may include a fifth control line L5, and the third connection assembly may include a sixth control line L6. The first driving chip 21 may be further electrically connected to the display panel through a trace L7, and the second driving chip 22 may be further electrically connected to the display panel through a trace L8.

Fig. 4 shows an internal block diagram of a driver chip of an embodiment of the present application. As shown in fig. 4, taking the first driving chip 21 as an example, the first driving chip 21 may include a data processing unit 210, and the data processing unit 210 may include a receiving circuit 211 and a clock data recovery circuit 212 electrically connected to the receiving circuit 211. It should be noted that the data processing unit 210 in fig. 4 is exemplary. In practical applications, the driving chip may be directly provided with the receiving circuit 211 and the clock data recovery circuit 212, without the data processing unit 210. In other words, the reception circuit 211 and the clock data recovery circuit 212 may coexist in the data processing unit 210 in the driver chip, or may be separately provided in the driver chip.

In one embodiment, as shown in fig. 4, the timing controller includes: a transmit circuit 31 and a processor 32. A transmitting circuit 31 for transmitting at least one data pair to at least one of the driving chips and generating at least one control signal group; the processor 32 is electrically connected to the transmitting circuit 31, and the processor 32 is configured to adjust a plurality of control signals according to a preset operation mode, so as to control the transmission states of at least three of the connection components based on the plurality of control signals. The transmitting circuit 31 may be provided corresponding to the receiving circuit 211 of the first driving chip 21.

In an embodiment, the second connection component is located on a middle line of the driving chip along the length direction, and the first connection component and the third connection component are located on two sides of the second connection component. In fig. 4, the second control line L2 of the second connection assembly may be located on a middle line of the driving chip along the length direction, and the first control line L1 of the first connection assembly and the third control line L3 of the third connection assembly are located at two sides of the second control line L2 of the second connection assembly.

In an embodiment, the control signal group includes: the control line of the first connecting component is used for transmitting the first control signal, the control line of the second connecting component is used for transmitting the second control signal, and the control line of the third connecting component is used for transmitting the third control signal. In fig. 4, a first control line L1 transmits a first control signal, a second control line L2 transmits a second control signal, and a third control line L3 transmits a third control signal.

The second control signal is opposite to the first control signal and the third control signal in level, and the first control signal and the third control signal are identical in level. Optionally, when the second control signal is at a high level, the first control signal and the third control signal are both at a low level; when the second control signal is at a low level, the first control signal and the third control signal are both at a high level.

Fig. 5 shows a schematic diagram of a driving chip according to an embodiment of the present application.

In one implementation, the driving chip further includes: the plurality of input pads are arranged along a first direction, which may be a length direction of the driving chip, i.e., a horizontal direction in fig. 5. The driving chip may further include a plurality of output pads, the plurality of input pads being arranged in rows, the plurality of output pads also being arranged in rows. The input pads and the output pads are oppositely arranged at two ends of the driving chip along the width direction of the driving chip.

One of the connection assemblies comprises at least three input pads, wherein two of the input pads are used for transmitting one data pair, and the other input pad is used for transmitting one control signal.

Taking fig. 5 as an example, the signal transmitted by the first connection component on the left side is Rx0P-L, rx0N-L, rx1N-L, rx1P-L, rx-L-EN, and the signal transmitted by the second connection component in the middle is Rx1N, rx1P, rx0N, rx0P, rx-C-EN; the third connection element on the right transmits the signal Rx0P-R, rx0N-R, rx1N-R, rx1P-R, rx-R-EN. Wherein Rx0P-L, rx0N-L, rx1N-L, rx1P-L are two data pairs, rx-L-EN is a first control signal; rx1N, rx1P, rx0N, rx0P is two data pairs, rx-C-EN is a second control signal; rx0P-R, rx0N-R, rx N-R, rx1P-R is two data pairs and Rx-R-EN is the third control signal.

In an embodiment, in the driving chip, for the same connection assembly, a plurality of the data lines are adjacently disposed, and the control line is disposed at one side of the plurality of adjacently disposed data lines. As shown in FIG. 5, the signals transmitted by the first connection element on the left side are Rx0P-L, rx0N-L, rx1N-L, rx1P-L, rx-L-EN, where Rx0P-L is the positive polarity data of the first data pair, rx0N-L is the negative polarity data of the first data pair, rx1N-L is the negative polarity data of the second data pair, rx1P-L is the positive polarity data of the second data pair, and Rx-L-EN is the first control signal transmitted by the control line. The control lines may be arranged in accordance with the signal sequence shown in fig. 5. In the first connection assembly, the first control line may be disposed at the leftmost side, and the other four data lines may be disposed adjacently.

The application also provides a display device, which comprises a display panel and the panel driving circuit.

Fig. 6 shows a flowchart of a display driving method according to an embodiment of the present application. As shown in fig. 6, the display driving method is applied to the panel driving circuit, and the processor is operable to perform the display driving method, the display driving method including:

step S1: judging the working mode of the time sequence controller according to the target frame of the display panel, wherein the working mode comprises a first working mode and a second working mode;

the target frame of the display panel can be an integral frame preset by the display panel and the panel driving circuit, and according to the target frame, the most suitable working mode adopted in practical application can be judged in advance, namely, the target frame can be matched with the working mode of the processor. In practical application, the working mode of the processor in the timing controller can be determined according to other situations, which is not limited in this application.

Step S2: in the first working mode, at least one control line in at least three connecting assemblies is controlled to be in an enabling state;

optionally, in the first operation mode, the second control line of the second connection component is in an enabled state, and at this time, the transmitting circuit may transmit data to the receiving circuit through the second connection component, but may not transmit data through the first connection component and the third connection component.

Step S3: and in the second working mode, controlling at least two control lines in at least three connecting assemblies to be in an enabling state, wherein the control lines in the enabling state in the first working mode are different from the control lines in the enabling state in the second working mode.

Optionally, in the second operation mode, the first control line of the first connection component and the third control line of the third connection component are in an enabled state, and at this time, the transmitting circuit may transmit data to the receiving circuit through the first connection component and the third connection component, but cannot transmit data through the second connection component.

In sum, through making receiving circuit pass through at least three coupling assembling electricity and connect in time schedule controller, and be located the different positions of driver chip respectively with different coupling assembling, and then based on the transmission state of a plurality of control signal control at least three coupling assembling, this application can compatible multiple operating mode, moreover, the specification convergence of panel, no longer need redesign driver circuit to different panel specifications, the quantity of receiving circuit and clock data recovery circuit has been reduced, the quantity of the whole required driver chip of while also correspondingly reduces, at least 50% signal processing circuit has been practiced thrift, both reduced driving cost, and shortened driver chip again and verify the lead-in time, thereby improve panel drive's development efficiency.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The panel driving circuit, the display device and the display driving method provided by the embodiment of the application are described in detail, and specific examples are applied to the description of the principle and the implementation of the application, and the description of the above embodiments is only used for helping to understand the technical scheme and the core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A panel driving circuit, wherein the panel driving circuit is electrically connected to a display panel, the panel driving circuit comprising:

a timing controller for transmitting at least one data pair and generating at least one control signal group, wherein the control signal group comprises a plurality of control signals;

the driving chip comprises a data processing unit, and the data processing unit is electrically connected with the time sequence controller through at least three connecting components so as to receive at least one data pair transmitted by the connecting components;

the driving chip is arranged on the driving device, wherein different connecting components are respectively positioned at different positions of the driving chip, and each connecting component comprises at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal so as to control the transmission states of at least three connecting components based on a plurality of control signals.

2. The panel driving circuit according to claim 1, wherein the driving chip further comprises:

a plurality of input pads arranged along a first direction;

one of the connection assemblies comprises at least three input pads, wherein two of the input pads are used for transmitting one data pair, and the other input pad is used for transmitting one control signal.

3. The panel driving circuit according to claim 1, wherein at least three of the connection assemblies include a first connection assembly, a second connection assembly, and a third connection assembly, the first connection assembly and the third connection assembly being located at both sides of the second connection assembly.

4. The panel driving circuit of claim 3, wherein the number of data lines of the first, second and third connection assemblies is the same, and the number of control lines of the first, second and third connection assemblies is the same.

5. A panel driving circuit according to claim 3, wherein the control signal group comprises a first control signal, a second control signal and a third control signal, the control line of the first connection assembly being used for transmitting the first control signal, the control line of the second connection assembly being used for transmitting the second control signal, and the control line of the third connection assembly being used for transmitting the third control signal.

6. The panel driving circuit according to claim 1, wherein in the driving chip, a plurality of the data lines are adjacently disposed for the same connection assembly, and the control line is disposed at one side of the plurality of adjacently disposed data lines.

7. The panel driving circuit according to claim 1, wherein the driving chip is a first driving chip or a second driving chip, the panel driving circuit comprising:

the first driving chip is a source driver;

the second driving chip is a grid driver;

the first driving chip and the second driving chip are packaged on the glass substrate of the display panel.

8. The panel driving circuit according to claim 7, wherein the timing controller comprises:

the transmitting circuit is used for transmitting at least one data pair to at least one driving chip and generating at least one control signal group;

the processor is electrically connected to the sending circuit and is used for adjusting a plurality of control signals according to a preset working mode so as to control the transmission states of at least three connecting components based on the control signals.

9. A display device comprising a display panel and a panel driving circuit according to any one of claims 1 to 8.

10. A display driving method, wherein the display driving method is applied to the panel driving circuit according to any one of claims 1 to 8, the display driving method comprising:

judging the working mode of the time sequence controller according to the target frame of the display panel, wherein the working mode comprises a first working mode and a second working mode;

in the first working mode, at least one control line in at least three connecting assemblies is controlled to be in an enabling state;

and in the second working mode, controlling at least two control lines in at least three connecting assemblies to be in an enabling state, wherein the control lines in the enabling state in the first working mode are different from the control lines in the enabling state in the second working mode.