CN117829299A - Quantum circuit simulation method and device, medium and electronic device - Google Patents
Quantum circuit simulation method and device, medium and electronic device Download PDFInfo
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Abstract
The application discloses a quantum circuit simulation method, a quantum circuit simulation device, a quantum circuit simulation medium and an electronic device, wherein the quantum circuit simulation method comprises the following steps: acquiring an instruction input by a user, wherein the instruction is used for acting a target quantum logic gate on a target quantum bit; generating a plurality of computing tasks according to the instructions, wherein each computing task comprises a processing operation and an input variable and an output variable corresponding to the processing operation; according to the dependency relationship between each computing task, determining the computing sequence of each computing task, and parallelly computing the computing tasks with the same computing sequence. The speed of the classical computer analog quantum circuit can be improved.
Description
Technical Field
The application belongs to the technical field of quantum computing, and particularly relates to a quantum circuit simulation method, a quantum circuit simulation device, a quantum circuit simulation medium and an electronic device.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and calculates a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
Since large-scale quantum computers are not very easy to build and maintain at present, classical computers are also commonly used to simulate quantum computing, including quantum circuit simulation processes. However, in the existing quantum circuit simulation method, the advantage of parallel computation of the quantum bits is ignored, and each computation task in the quantum circuit is simply computed in series, so that the computation speed is slow.
Content of the application
The purpose of the application is to provide a quantum circuit simulation method, a device, a medium and an electronic device, which aim to improve the speed of quantum circuit simulation.
One embodiment of the present application provides a quantum circuit simulation method, the method comprising:
acquiring an instruction input by a user, wherein the instruction is used for acting a target quantum logic gate on a target quantum bit;
generating a plurality of computing tasks according to the instructions, wherein each computing task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
according to the dependency relationship between each computing task, determining the computing sequence of each computing task, and parallelly computing the computing tasks with the same computing sequence.
Optionally, the determining the computing order of each computing task according to the dependency relationship between each computing task includes:
Constructing a directed acyclic graph by using a topological sorting algorithm based on the dependency relationship between each computing task, wherein nodes of the directed acyclic graph represent the computing tasks, and edges of the directed acyclic graph represent the dependency relationship between the computing tasks;
and determining the calculation sequence of each calculation task according to the directed acyclic graph.
Optionally, the input variable and the output variable are provided with virtual tags, and the method further includes:
determining virtual labels of input variables and output variables corresponding to each computing task based on the computing sequence of each computing task;
according to the calculation sequence, sequentially submitting calculation tasks with virtual labels of input variables being first virtual labels and virtual labels of output variables being second virtual labels to a task execution pool;
after one computing task of the task execution pool is executed, updating the virtual tag of the output variable of the computing task into the first virtual tag;
parallel computing of computing tasks in the same computing order, comprising:
and calculating the calculation tasks in parallel in the task execution pool.
Optionally, the virtual labels of the input variables of the computing task are determined by the virtual labels of the output variables of the computing task which have a dependency relationship with the computing task and have a previous computing sequence.
Optionally, the computing task includes a slicing task, a matrix multiplication task, and a tensor product task;
the input variable of the slicing task is a quantum state corresponding to the target quantum bit;
the input variable of the matrix multiplication task is the output variable of the slicing task;
the input variable of the tensor product task is the output variable of the matrix multiplication task and/or the output variable of another tensor product task.
Optionally, the target qubit includes a plurality of qubits, the processing operation of the slicing task is to slice the quantum state corresponding to the target qubit, and the output variable of the slicing task is the first quantum state of each qubit;
the processing operation of the matrix multiplication task is to perform matrix multiplication calculation on matrix representations of each first quantum state and the corresponding target quantum logic gate, and the output variable of the matrix multiplication task is a second quantum state of each quantum bit.
Optionally, the tensor product task processing operation is to perform tensor product calculation on the second quantum state of the qubit after one matrix multiplication task is performed.
Yet another embodiment of the present application provides a quantum circuit simulation apparatus, the apparatus comprising:
The acquisition module is used for acquiring an instruction input by a user, wherein the instruction is used for acting the target quantum logic gate on the target quantum bit;
the generation module is used for generating a plurality of calculation tasks according to the instructions, wherein each calculation task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
and the computing module is used for determining the computing sequence of each computing task according to the dependency relationship among each computing task and parallelly computing the computing tasks with the same computing sequence.
A further embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the above when calculated.
Yet another embodiment of the present application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to calculate the computer program to perform the method described in any of the above.
The application provides a quantum circuit simulation method, a quantum circuit simulation device, a quantum circuit simulation medium and an electronic device, wherein a plurality of calculation tasks are generated according to instructions input by a user, the execution sequence of the calculation tasks is determined based on the dependency relationship between input variables and output variables corresponding to each calculation task, the tasks with the same execution sequence are calculated in parallel, and classical computer calculation resources are utilized to the maximum extent. Compared with the existing quantum circuit simulation method, the quantum circuit simulation method provided by the embodiment of the application greatly improves the speed of simulating the quantum circuit by a classical computer.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal of a quantum circuit simulation method according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a quantum circuit simulation method according to an embodiment of the present application;
FIG. 3 is an exemplary schematic diagram of a quantum circuit provided in an embodiment of the present application;
FIG. 4 is an exemplary schematic diagram of a directed acyclic graph provided by an embodiment of the present application;
FIG. 5 is a flow chart of another quantum circuit simulation method according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a quantum circuit simulation device according to an embodiment of the present application.
Detailed Description
The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.
Fig. 1 is a hardware block diagram of a computer terminal of a quantum circuit simulation method according to an embodiment of the present application. Quantum circuit simulation system may include network 110, server 120, wireless device 130, client 140, storage 150, classical computing unit 160, and may also include additional memory, classical processors, and other devices not shown.
Network 110 is a medium used to provide a communication link between various devices and computers connected together within the quantum circuit emulation system, including but not limited to the internet, intranets, local area networks, mobile communication networks, and combinations thereof, and may be connected by wired, wireless communication links, or fiber optic cables, etc.
Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and have applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, tablet, notebook, smart wearable device, or the like. The memory unit 150 may include a database 151 that may be configured to store data of qubit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc. under a classical architecture.
Classical computing unit 160 may include a classical processor 161 for processing classical data, which may be boot files, an operating system image, and an application 163, and a memory 162 for storing classical data, which application 163 may be used to implement algorithms compiled according to the quantum circuit simulation method provided by embodiments of the present application.
Any data or information stored or generated in classical computing unit 160 may also be configured to be stored or generated in a similar manner in another classical processing system, as may any application program executed thereby.
The computation unit of the classical processor 161 in the classical computation unit 160 is a CMOS tube based on silicon chips, which is not limited by time and coherence, i.e. which is not limited by the time of use, which is available at any time. Furthermore, in silicon chips, the number of such computation units is also sufficient, the number of computation units in a classical processor 161 is now thousands, the number of computation units is sufficient and the CMOS pipe selectable computation logic is fixed, for example: and AND logic. When the CMOS tube is used for operation, a large number of CMOS tubes are combined with limited logic functions, so that the operation effect is realized.
The design of classical logic functions acting on CMOS transistors and the design of quantum logic functions acting on qubits are significantly and essentially different; the classical logic function acts on the design of the CMOS tube without considering the individuality of the CMOS tube, such as the individuality identification and the position of the CMOS tube in the silicon chip, and the usable time length of each CMOS tube, so the classical algorithm formed by the classical logic function only expresses the operation relation of the algorithm, and does not express the dependence of the algorithm on the individuals of the CMOS tube.
The quantum logic function acts on the qubit, and the individuality of the qubit needs to be considered, such as the individuality identification, the position and the relation with surrounding qubits of the number of the qubit in the quantum chip, and the usable duration of each qubit. Therefore, the quantum algorithm formed by the quantum logic functions not only expresses the operation relation of the algorithm, but also expresses the dependence of the algorithm on quantum bit individuals.
Exemplary:
quantum algorithm one: h1, H2, CNOT (1, 3) H3, CNOT (2, 3);
and a quantum algorithm II: h1, H2, CNOT (1, 2), H3, CNOT (2, 3);
wherein 1/2/3 respectively represents three sequentially connected qubits Q1, Q2, Q3 or mutually connected qubits Q1, Q2, Q3;
an exemplary explanation of the quantum algorithm's influence by the quantum bit coherence time is as follows:
defining the execution time of a single-quantum bit logic gate as t, and 1 two single-quantum bit logic gates acting on adjacent bits as 2t; then:
when three Q1, Q2, Q3 are mutually connected, the first quantum algorithm needs to be calculated in 6t and 4 time periods, the time period needed by each time period is respectively t,2t, and the operations executed in each time period are as follows: h1 and H2; CNOT (1, 3); h3; CNOT (2, 3);
the first quantum algorithm is calculated by 5t and is carried out in 3 time periods, the time duration required by each time period is t,2t and 2t respectively, and the operation executed in each time period is as follows: h1, H2, H3; CNOT (1, 2); CNOT (2, 3);
when the Q1, the Q2 and the Q3 are connected in sequence, the quantum algorithm one needs to be equivalent to: h1 and H2; swap (1, 2), CNOT (2, 3), swap (1, 2); h3; CNOT (2, 3); the equivalent quantum algorithm I needs 10t to be calculated, and 4 time periods are divided, and the time duration needed by each time period is t,6t, t and 2t respectively. The operations performed in each time period are: h1 and H2; swap (1, 2), CNOT (2, 3), swap (1, 2); h3; CNOT (2, 3).
Therefore, the design of the quantum logic function acting on the quantum bit (including the design of whether the quantum bit is used or not and the design of the use efficiency of each quantum bit) is the key for improving the operation performance of the quantum computer, and special design is required, which is the uniqueness of the quantum algorithm realized based on the quantum logic function and is different from the nature and the significance of the classical algorithm realized based on the classical logic function.
Because of the limited development of quantum device hardware, quantum computing simulations are often required to validate quantum algorithms, quantum applications, and the like. Quantum computing simulation is a process of realizing the simulated operation of a quantum circuit corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. Quantum circuits also weigh sub-logic circuits, the most commonly used general quantum computing model, consisting of qubits and quantum logic gates acting on the qubits, and finally the result often needs to be read out by quantum measurement operations.
At present, when a classical computer is adopted to simulate the operation of a quantum circuit, a great deal of time is required to be consumed, and based on the fact, the application provides a quantum circuit simulation method and a related device, and the purpose of improving the speed of the classical computer to simulate the quantum circuit is achieved.
Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum circuit simulation method according to an embodiment of the present application, which may include the following steps:
s201, acquiring an instruction input by a user, wherein the instruction is used for acting a target quantum logic gate on a target quantum bit;
qubits (qubits) are the fundamental unit of quantum computation, which is based on physical entities of the quantum system (such as atoms, ions, or quantum states in superconducting circuits). Unlike two definite states where a classical bit can only be in 0 or 1, a qubit can be in a superposition of states at the same time under the principles of quantum mechanics, which represents a linear combination of the states where the qubit is in multiple possible states at the same time.
Quantum logic gates are the basic units in quantum computing for operating on qubits and performing computations. They are similar to logic gates in classical computation, but in quantum computation they can change the relative phase between qubits and interact between qubits due to their quantum properties, by changing and manipulating the states between qubits, logic operations in quantum computation are achieved.
The target qubit refers to any one qubit or any combination of a plurality of qubits in the quantum circuit, and the target qulogic gate refers to a quantum logic gate acting on any one or more qubits included in the target qubit.
S202, generating a plurality of computing tasks according to the instructions, wherein each computing task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
a computing task refers to a particular task or function that a computer performs, typically consisting of one or more functions. The computational tasks may be comprised of processing operations, input variables, output variables.
Processing operations are the core of a computing task, i.e., a particular operation or algorithm performed by a computer. The processing operations may be various functions, algorithms, or methods of operation for processing input variables and generating output variables.
The input variables are the data that needs to be processed. The input variables may be various types of data such as numerical values, text, images, audio, etc.
The output variables are the results of the computational task or output data. Which is new data or information calculated from the processing operations performed on the input variables.
When a computing task consists of only one or more functions, the input variables may be considered as independent variables of the functions, the input variables may be considered as dependent variables of the functions, and the processing operations may be considered as independent variables, function mappings between the dependent variables.
It should be noted that the weighed sub bits, quantum logic gates, and quantum states are analog quantities on a classical computer.
S203, determining the calculation sequence of each calculation task according to the dependency relationship among each calculation task, and parallelly calculating the calculation tasks with the same calculation sequence.
In one embodiment of the present application, the determining the computing order of each computing task according to the dependency relationship between each computing task includes:
constructing a directed acyclic graph by using a topological sorting algorithm based on the dependency relationship between each computing task, wherein nodes of the directed acyclic graph represent the computing tasks, and edges of the directed acyclic graph represent the dependency relationship between the computing tasks;
and determining the calculation sequence of each calculation task according to the directed acyclic graph.
A directed acyclic graph (Directed Acyclic Graph, DAG) is a graph structure made up of a set of nodes and edges. It satisfies both the conditions of both the tropism and the acyclic nature. By directional is meant that the edges in the graph are all directional, i.e., pointing from one node to another. For an edge (u, v), node u is referred to as the start node of the edge and node v is referred to as the end node of the edge. Loop-free means that there is no loop in the graph, i.e. there is no path from a node through several edges and finally back to the node. If there is a path in the directed graph from node a that passes through edges that eventually can return to node a, then the graph is not a loop-free graph. This graph is considered a directed acyclic graph only if it eventually fails to return to a node in the direction of the edge from that node.
Directed acyclic graphs are very common in practical applications, especially in the fields of task scheduling, dependency modeling, compiler optimization, etc. The method is characterized in that the dependency relationship between the nodes can be represented, so that the processing of the graph is more efficient and reliable.
The topological ordering algorithm is an ordering algorithm for directed acyclic graphs. It orders the nodes in the graph according to their dependency relationship such that for any one edge (u, v), node u appears before node v in the ordering result. The basic idea of the topology ordering algorithm is to remove nodes with an ingress of 0 from the graph by continually finding them until all nodes have been processed.
The specific algorithm steps of the topology ordering algorithm are as follows: counting the ingress of each node (i.e. how many edges point to the node); initializing a queue, and putting all nodes with the degree of 0 into the queue; the following operations are performed in a loop until the queue is empty:
taking out a node u from the queue; adding the node u to the sequencing result; for each adjacent node v of the node u, reducing the ingress of the node v; if the degree of entry of the node v becomes 0, putting the node v into a queue; if the number of the nodes in the ordering result is equal to the number of the nodes in the graph, the graph is described as having no ring, and the ordering is successful; otherwise, there is a ring in the graph and the ordering fails.
According to the embodiment of the application, the topological ordering algorithm is used, the relation among the calculation tasks is represented as the directed acyclic graph, and the calculation sequence of the calculation tasks is determined according to the directed acyclic graph, so that the calculation sequence of the calculation tasks can meet the dependency relation among the calculation tasks, each calculation task is ensured to calculate after the dependent calculation tasks are completed, the waiting time and redundant calculation can be reduced to the greatest extent through calculating according to the reasonable sequence of the dependency relation, and the speed of a classical computer simulation quantum circuit is greatly improved.
In one embodiment of the present application, the input variable and the output variable are provided with virtual tags, and the method further comprises:
determining virtual labels of input variables and output variables corresponding to each computing task based on the computing sequence of each computing task;
according to the calculation sequence, sequentially submitting calculation tasks with virtual labels of input variables being first virtual labels and virtual labels of output variables being second virtual labels to a task execution pool;
after one computing task of the task execution pool is executed, updating the virtual tag of the output variable of the computing task into the first virtual tag;
Parallel computing of computing tasks in the same computing order, comprising:
and calculating the calculation tasks in parallel in the task execution pool.
In one embodiment of the present application, the method further comprises:
in the process of executing one computing task in the task execution pool, the virtual tag of the output variable of the computing task is updated to be a third virtual tag.
Virtual tags refer to a symbol or identifier used to identify, describe, classify, or organize data, for purposes of marking and identifying a particular entity or providing additional information to the data. Virtual tags may be semantically meaningful names or symbols that do not have specific semantic meaning for tagging different data elements, object attributes, or page elements for better organization, processing, and retrieval of data.
A task execution pool refers to a pool of resources in a computing system that are used to execute tasks. The task execution pool is used to manage and schedule task execution to improve the efficiency and performance of the computing system. The task execution pool typically contains a plurality of available execution resources, such as thread pools, process pools, or compute node pools. These resources may perform multiple computing tasks simultaneously, thereby enabling parallel computing and task scheduling.
By setting virtual tags for the input and output variables of each computing task, the computing tasks can be submitted to a task execution pool in a correct order and sequentially executed according to the dependency relationship. By setting specific virtual labels for the input and output variables corresponding to the calculation tasks submitted to the task execution pool and updating the virtual labels of the input and output variables in the calculation process of the calculation tasks and after the calculation is finished, the thread competition among the calculation tasks can be prevented, the calculation task scheduling is optimized, and the speed of the classical computer simulation quantum circuit is greatly improved.
In one embodiment of the present application, the task execution pool is an operator execution pool.
An operator execution pool is a special task execution pool in which a computing task is treated as an operator. It may be a set of computing nodes, a cluster of servers, a distributed system, or other available computing resources for executing various operators.
In one embodiment of the present application, the virtual tag of the input variable of the computing task is determined by the virtual tag of the output variable of the computing task having a dependency relationship with the computing task and having a preceding computing order.
The virtual labels of the input variables of the computing task being determined by the virtual labels of the output variables of the computing task having a dependency relationship with the computing task and having a preceding computing order means that when the virtual labels of all the output variables of the computing task having a dependency relationship with the computing task and having a preceding computing order change, for example, when an update occurs, the virtual labels of the input variables of the computing task change accordingly.
In one embodiment of the present application, the computing tasks include a slicing task, a matrix multiplication task, and a tensor product task;
the input variable of the slicing task is a quantum state corresponding to the target quantum bit;
the input variable of the matrix multiplication task is the output variable of the slicing task;
the input variable of the tensor product task is the output variable of the matrix multiplication task and/or the output variable of another tensor product task.
The slicing task is a calculation task for slicing the input variable to obtain the corresponding output variable. The slicing operation is used to obtain sub-sequences of a specified range from a sequence (e.g., a string, list, or tuple). In the embodiment of the present application, the slicing operation is used to obtain, from a sequence corresponding to a quantum state of a target qubit, a sequence corresponding to a first quantum state of each qubit. For example, the sequence corresponding to the quantum state of the target qubit may be a representation matrix of the target qubit, and the sequence corresponding to the first quantum state of each qubit may be a representation vector of each qubit. It should be noted that each qubit may be a single qubit or multiple qubits.
The matrix multiplication task is a calculation task for performing matrix multiplication operation on input variables to obtain corresponding output variables. Matrix multiplication is a common numerical computation task in which multiplication of two matrices is required. The result of the multiplication of the two matrices is a new matrix obtained by multiplying each row of the first matrix by each column of the second matrix by the corresponding element and accumulating the products. When two one-dimensional vectors are included in two matrices corresponding to a matrix multiplication task, a matrix multiplication operation may be considered as a dot product operation on the two one-dimensional vectors.
The tensor product task refers to a calculation task that generates a new tensor by calculating the tensor product of two input variables (tensors). Tensors are abstractions of a multidimensional array (or matrix), and in this embodiment of the present application, the tensors may be output variables of a matrix multiplication task and/or output variables of another tensor product task, where the output variables of the matrix multiplication task and the output variables of the other tensor product task are all in matrix form.
For two tensors A and B, their tensor product may be denoted as A ≡B. The result is a new tensor whose dimension and shape depend on the dimension and shape of the input tensor. If a is an m-dimensional vector (or m-dimensional matrix) and B is an n-dimensional vector (or n-dimensional matrix), then the result will be a tensor of (m n) dimensions. Each element is obtained by multiplying each element in a with each element in B.
In one embodiment of the present application, the target qubit includes a plurality of qubits, the processing operation of the slicing task is to slice the quantum state corresponding to the target qubit, and the output variable of the slicing task is the first quantum state of each qubit;
the processing operation of the matrix multiplication task is to perform matrix multiplication calculation on matrix representations of each first quantum state and the corresponding target quantum logic gate, and the output variable of the matrix multiplication task is a second quantum state of each quantum bit.
In one embodiment of the present application, the processing operation of the tensor product task is to perform tensor product calculation on the second quantum state of the qubit after one matrix multiplication task is performed.
The first and second quantum states referred to in this application are not particularly limited to a specific quantum state, and the first and second states are merely distinguished.
In one embodiment of the present application, the first virtual tag is read-only and the second virtual tag is variable.
In one embodiment of the present application, the third virtual tag is unreadable.
Read-only, variable, non-readable, and non-variable are virtual tags that represent data read-write rights.
Read-only is used to denote data that can only be read, but cannot be modified. The data provided with the read-only virtual tag cannot be updated, deleted or new elements added.
The variable is used to represent data that can be read as well as modified. The data provided with the variable virtual tag may be updated, deleted or new elements added.
Unreadable immutable is used to denote data that cannot be read nor modified. The data provided with the unreadable, immutable virtual tag cannot be read nor updated, deleted or added with new elements.
It should be specifically noted that, the virtual tag provided in the embodiment of the present application is not limited to the virtual tag that represents the data read-write authority, and in fact, the virtual tag may be any symbol or identifier and may not have any semantic meaning.
In one embodiment of the present application, the parallel computing of the computing task in the task execution pool includes:
and if the idle computing resources exist in the task execution pool, computing the computing task in the task execution pool.
In one embodiment of the present application, the quantum circuit is a variable component sub-circuit.
In one embodiment of the present application, the quantum circuit simulation method is used for training of variable component sub-circuits.
The variable component sub-circuit is a quantum circuit composed of parameter sub-logic gates, when the problem is solved, the variable component sub-circuit is used for representing the solution space of the problem, the variable of the problem is represented by the parameters of the quantum logic gates, and by adjusting the parameters of the quantum logic gates, a high-adjustable quantum circuit is constructed, so that the circuit can perform different modes of transformation on input data, and thus, various different problems can be dealt with. And, unlike the traditional quantum circuit, the variable component sub-circuit searches the optimal parameter capable of minimizing the problem loss through the variable component optimization algorithm, so that the approximate solution of the problem is obtained, and the calculation efficiency is greatly improved.
Through training, parameters of the quantum logic gates can be optimized, so that the variable component sub-circuit is better adapted to different problems, and the calculation efficiency and accuracy are improved.
The following specifically illustrates a quantum circuit simulation method provided in the embodiments of the present application.
The graphical instruction input by the user is obtained, and the graphical instruction can be a graphical representation of a quantum circuit, and particularly, the graphical instruction can be referred to as an exemplary schematic diagram of the quantum circuit shown in fig. 3.
A quantum circuit shown in fig. 3 includes a qubit q 0 、q 1 、q 2 The target qubit is q 0 、q 1 、q 2 In its entirety, a quantum circuit as shown in FIG. 3 further comprises a quantum bit q 0 A first quantum logic gate RX on the first quantum bit q 1 A second quantum logic gate RY on the upper, acting on the qubit q 2 And a third quantum logic gate RZ gate. The ellipses in one of the quantum circuits shown in fig. 3 represent the remaining logic gate operations that the quantum circuit includes.
The following computational tasks (in code) may be generated using the instructions:
slicing task 1: q0=init_state.slice (0);
slicing task 2: q1=init_state.slice (1);
slicing task 3: q2=init_state.slice (2);
matrix multiplication task 1: q0_dot (q 0, rx_mat);
matrix multiplication task 2: q1_dot (q 1, ry_mat);
matrix multiplication task 3: q2_dot (q 2, rz_mat);
tensor product task 1: q01=kron (q0_q1_);
tensor product task 2: final_state=kron (q 01, q 2_).
Wherein, the slice is arbitraryThe input variables of tasks 1, 2 and 3 are all quantum state_state of target quantum bit, the processing operation of the slicing task 1 is slicing operation slice (0), the processing operation of the slicing task 2 is slicing operation slice (1), the processing operation of the slicing task 3 is slicing operation slice (2), and the output variable of the slicing task 1 is quantum bit q 0 The output variable of slicing task 2 is the qubit q 1 The output variable of slicing task 3 is the qubit q 2 Is a first quantum state q2;
the processing operations of the matrix multiplication task 1 are dot products (one type of matrix multiplication operation), and the input variable of the matrix multiplication task 1 is a qubit q 0 The input variable of the matrix multiplication task 2 is the qubit q, the representation vector rx_mat of the first quantum state q0 and the first quantum logic gate RX gate 1 The input variable of the matrix multiplication task 3 is the qubit q, the representation vector ry_mat of the first quantum state q1 and the first quantum logic gate RY gate 2 The output variable of the matrix multiplication task 1 is the qubit q 0 The output variable of matrix multiplication task 2 is the qubit q 1 The output variable of matrix multiplication task 3 is the qubit q 2 And (2) a second quantum state q 2.
The processing operations of the tensor product tasks 1 and 2 are tensor product operation kron, and the input variable of the tensor product task 1 is a qubit q 0 And qubit q 1 The output variable is the tensor product of the second quantum state q0_and the second quantum state q1_and the input variable of the tensor product task 2 is the output variable of the tensor product task 1 and the quantum bit q 2 The output variables are the tensor products of the second quantum state q0_and the second quantum state q1_and the second quantum state q2_which are the output quantum states of the target quantum bit, q01 represents the tensor products of the second quantum state q0_and the second quantum state q1_and final_state represents the output quantum state of the target quantum bit.
As can be seen, each computing task input and output variable has the following dependency:
the input variable q0 of the matrix multiplication task 1 is an output variable of the slicing task 1, and the matrix multiplication task 1 can be calculated only after the slicing task 1 is executed;
the input variable q1 of the matrix multiplication task 2 is an output variable of the slicing task 2, and the matrix multiplication task 2 can be calculated only after the slicing task 2 is executed;
the input variable q2 of the matrix multiplication task 3 is an output variable of the slicing task 3, and the matrix multiplication task 3 can be calculated only after the slicing task 3 is executed;
the input variable q 0_of the tensor product task 1 is an output variable of the matrix multiplication task 1, the input variable q 1_of the tensor product task 1 is an output variable of the matrix multiplication task 2, and the tensor product task 1 can be calculated only after the matrix multiplication task 1 and the matrix multiplication task 2 are executed;
The input variables of the tensor product task 2 are the output variable q01 of the tensor product task 1 and the output variable q2_of the matrix multiplication task 3, and the tensor product task 2 can be calculated only after the tensor product task 1 and the matrix multiplication task 3 are executed.
Based on the above dependencies, the above computational tasks can be represented as directed acyclic graphs using a topological ordering algorithm, see in particular the exemplary schematic of one of the directed acyclic graphs shown in FIG. 4.
One directed acyclic graph is shown in FIG. 4 including eight nodes and edges between the nodes. Wherein, eight nodes include:
node 1, representing slicing task 1;
node 2, representing slicing task 2;
node 3, representing slicing task 3;
node 4, representing matrix multiplication task 1;
node 5, representing the matrix multiplication task 2;
node 6, representing a matrix multiplication task 3;
node 7, representing tensor product task 1;
node 8 represents tensor product task 2.
The edges between eight nodes represent the dependency relationship between the calculation tasks, for example, the edge from node 1 to node 4 represents the execution of matrix multiplication task 1 depending on the execution of slicing task 1, the matrix multiplication task 1 can be calculated only after the execution of slicing task 1 is completed, the edge from node 4 to node 7 and the edge from node 5 to node 7 represent the execution of tensor product task 1 depending on the execution of matrix multiplication task 1 and matrix multiplication task 2, and the matrix multiplication task 1 can be calculated only after the execution of matrix multiplication task 1 and matrix multiplication task 2 is completed. The dependency between the computing tasks represented by the remaining edges is similarly the same and is not described in detail herein.
The directional acyclic graph may be drawn by referring to the above description provided in the present application, and will not be described herein.
Based on the directed acyclic graph, virtual labels of input variables and output variables corresponding to each computing task can be determined, wherein the virtual labels corresponding to the input variables and the output variables of the computing task comprise:
slicing task 1: the virtual tag of the input variable init_state is read-only, and the virtual tag of the output variable q0 is variable;
slicing task 2: the virtual tag of the input variable init_state is read-only, and the virtual tag of the output variable q1 is variable;
slicing task 3: the virtual tag of the input variable init_state is read-only, and the virtual tag of the output variable q2 is variable;
matrix multiplication task 1: the virtual tag of the input variable q0, rx_mat is read-only, and the virtual tag of the output variable q 0_mat is variable;
matrix multiplication task 2: the virtual labels of the input variables q1, ry_mat are read-only, and the virtual labels of the output variables q 1_are variable;
matrix multiplication task 3: the virtual tag of the input variable q2, rz_mat is read-only, and the virtual tag of the output variable q 2_mat is variable;
tensor product task 1: the virtual label of the input variable q 0_q1_is read-only, and the virtual label of the output variable q01 is variable;
Tensor product task 2: the virtual tag of the input variable q01, q 2_is read-only, and the virtual tag of the output variable final_state is variable.
Based on this, when the task execution pool always has idle computing resources, and the computing time of each computing task does not exceed the time corresponding to each time step, the above processes of submitting and executing the computing tasks may be:
time step 1: since the virtual labels init_state of the input variables of the slicing task 1, the slicing task 2 and the slicing task 3 are read-only (first virtual labels), the virtual labels q0, q1 and q2 of the output variables are variable (second virtual labels), and the slicing task 1, the slicing task 2 and the slicing task 3 are submitted to a task execution pool;
time step 2: performing parallel computation on the slicing task 1, the slicing task 2 and the slicing task 3 in a task execution pool, and updating virtual labels of output variables q0, q1 and q2 into unreadable and unchangeable (third virtual labels) in the computation process;
time step 3: after the slicing task 1, the slicing task 2 and the slicing task 3 are all calculated, virtual labels of output variables q0, q1 and q2 are updated to be read-only (first virtual labels), and as the output variables q0, q1 and q2 of the slicing task 1, the slicing task 2 and the slicing task 3 are simultaneously input variables of the matrix multiplication task 1, the matrix multiplication task 2 and the matrix multiplication task 3, the virtual labels of the input variables of the matrix multiplication task 1, the matrix multiplication task 2 and the matrix multiplication task 3 are correspondingly updated to be read-only (first virtual labels), and the matrix multiplication task 1, the matrix multiplication task 2 and the matrix multiplication task 3 are submitted to a task execution pool;
Time step 4: parallel computing is carried out on the matrix multiplication task 1, the matrix multiplication task 2 and the matrix multiplication task 3 in a task execution pool, and virtual labels of output variables q0_q1_q2_are updated to be unreadable and unchangeable (a third virtual label) in the computing process;
time step 5: after the matrix multiplication task 1, the matrix multiplication task 2 and the matrix multiplication task 3 are all calculated, the virtual labels of the output variables q 0_q 1_q 2_are updated to be read-only (first virtual labels), and as the output variables q 0_q 1_q 2_q of the matrix multiplication task 1 and the matrix multiplication task 2 are simultaneously input variables of the tensor product task 1, the virtual labels of the input variables of the tensor product task 1 are correspondingly updated to be read-only (first virtual labels), and the tensor product task 1 is submitted to a task execution pool;
time step 6: calculating a tensor product task 1 in a task execution pool, and updating a virtual tag of an output variable q01 to be unreadable and unchangeable (a third virtual tag) in the calculation process;
time step 7: after the tensor product task 1 is calculated, updating the virtual tag of the output variable q01 to be read-only (first virtual tag), and submitting the tensor product task 2 to a task execution pool because the output variable q2_of the matrix multiplication task 3 and the virtual tag of the output variable q01 of the tensor product task 1 are simultaneously input variables of the tensor product task 2, and the virtual tag of the input variable of the tensor product task 2 is correspondingly updated to be read-only (first virtual tag);
Time step 8: the tensor product task 2 is calculated in the task execution pool, and the virtual label of final_state is updated to be unreadable and unchangeable (third virtual label) in the calculation process.
Time step 9: after the tensor product task 2 finishes its calculation, the virtual tag of the output variable final_state is updated to be read-only (first virtual tag).
It should be specifically noted that, in the above examples provided in the present application, the target quantum logic gate includes only a single quantum logic gate, which is set for convenience of description. In practical applications, the target quantum logic gate may also include a multiple quantum logic gate, where the multiple quantum logic gate may be regarded as a single quantum logic gate in the above-described example, and a plurality of qubits acted by the multiple quantum logic gate may be regarded as one qubit in the above-described example, and the quantum circuit simulation is implemented by referring to the method provided in the above-described example, which is not repeated herein.
In an embodiment of the present application, before the computing tasks with the virtual labels of the input variables being the first virtual labels and the virtual labels of the output variables being the second virtual labels are sequentially submitted to the task execution pool according to the computing order, the method further includes:
And sequentially submitting the calculation tasks to a task waiting pool according to the calculation sequence.
In one embodiment of the present application, the sequentially submitting, according to the calculation order, calculation tasks with virtual labels of input variables being first virtual labels and virtual labels of output variables being second virtual labels to a task execution pool includes:
and sequentially submitting the calculation tasks with the virtual labels of the input variables being the first virtual labels and the virtual labels of the output variables being the second virtual labels from the task waiting pool to a task execution pool according to the calculation sequence.
A task-waiting pool refers to a queue or buffer for holding computing tasks waiting to be executed. When the preconditions required for executing a computing task are not satisfied, the computing task is put into a task waiting pool to wait for the execution conditions to be satisfied and then scheduled for execution.
The task waiting pool is used for managing the execution sequence of the computing tasks and processing the dependency relationship among the computing tasks. When all input variables for a computing task are not ready, the computing task cannot execute immediately. Instead, it will be placed in a task waiting pool, waiting for input variables to be available, and will not be scheduled for execution until execution conditions are met. Thus, the correct execution of the calculation task can be ensured, and the generation of errors or abnormal results is avoided.
In one embodiment of the present application, the task waiting pool is an operator waiting pool. An operator waiting pool is a special task waiting pool in which computing tasks are treated as operators.
Referring to fig. 5, fig. 5 is a schematic flow chart of another quantum circuit simulation method provided in the embodiment of the present application, and taking fig. 5 as an example, the flow chart of another quantum circuit simulation method provided in the embodiment of the present application is described below:
acquiring an instruction input by a user, and generating a plurality of calculation tasks by utilizing the instruction input by the user, wherein the plurality of calculation tasks comprise a slicing task, a matrix multiplication task and a tensor product task;
based on the dependency relationship between the input variable and the output variable of the calculation task, the calculation task is expressed as a directed acyclic graph by using a topological sorting algorithm;
determining the calculation sequence of each calculation task according to the directed acyclic graph, and determining the virtual labels of the input variable and the output variable of the calculation task based on the calculation sequence of each calculation task;
sequentially submitting the calculation tasks with the virtual labels of the input variables being read-only and the virtual labels of the output variables being variable to a task execution pool according to a calculation sequence;
and calculating the calculation task in the task execution pool, if space calculation resources exist in the task execution pool, performing parallel calculation on the calculation task in the task execution pool, updating the virtual tag of the output variable of the calculation task to be unreadable or unchangeable when the calculation task is in the execution process, and updating the virtual tag of the output variable of the calculation task to be read only when the calculation task is executed.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a quantum circuit simulation device according to an embodiment of the present application, corresponding to the flow shown in fig. 2, where the device includes:
an obtaining module 601, configured to obtain an instruction input by a user, where the instruction is used to apply a target quantum logic gate to a target qubit;
a generating module 602, configured to generate a plurality of computing tasks according to the instruction, where each computing task includes a processing operation and an input variable and an output variable corresponding to the processing operation;
the computing module 603 is configured to determine a computing order of each computing task according to a dependency relationship between each computing task, and perform parallel computing on computing tasks with the same computing order.
In some embodiments of the present invention, the determining the computing order of each computing task according to the dependency relationship between each computing task may include:
constructing a directed acyclic graph by using a topological sorting algorithm based on the dependency relationship between each computing task, wherein nodes of the directed acyclic graph represent the computing tasks, and edges of the directed acyclic graph represent the dependency relationship between the computing tasks;
and determining the calculation sequence of each calculation task according to the directed acyclic graph.
In some embodiments of the present invention, the input variable and the output variable are provided with virtual tags, and the quantum circuit simulation method may further include:
determining virtual labels of input variables and output variables corresponding to each computing task based on the computing sequence of each computing task;
according to the calculation sequence, sequentially submitting calculation tasks with virtual labels of input variables being first virtual labels and virtual labels of output variables being second virtual labels to a task execution pool;
after one computing task of the task execution pool is executed, updating the virtual tag of the output variable of the computing task into the first virtual tag;
parallel computing of computing tasks in the same computing order may include:
and calculating the calculation tasks in parallel in the task execution pool.
In some embodiments of the present invention, the virtual tag of the input variable of the computing task may be determined by the virtual tag of the output variable of the computing task having a dependency relationship with the computing task and having a preceding computing order.
In some embodiments of the invention, the computation tasks may include a slicing task, a matrix multiplication task, and a tensor product task;
The input variable of the slicing task can be a quantum state corresponding to the target quantum bit;
the input variable of the matrix multiplication task may be the output variable of the slicing task;
the input variable of the tensor product task may be an output variable of the matrix multiplication task and/or an output variable of another tensor product task.
In some embodiments of the present invention, the target qubit may include a plurality of qubits, the processing operation of the slicing task may be slicing a quantum state corresponding to the target qubit, and the output variable of the slicing task may be a first quantum state of each qubit;
the processing operation of the matrix multiplication task may be matrix multiplication computation of matrix representations of each first quantum state and the corresponding target quantum logic gate, and the output variable of the matrix multiplication task is the second quantum state of each quantum bit.
In some embodiments of the present invention, the processing operation of the tensor product task may be performing tensor product calculation on the second quantum state of the qubit after completion of execution of a matrix multiplication task.
The specific functions and effects achieved by the quantum circuit simulation device can be explained with reference to other embodiments of the present specification, and are not described herein. The various modules in the quantum circuit simulation device may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in hardware or independent of a processor in the computer equipment, and can also be stored in a memory in the computer equipment in a software mode, so that the processor can call and execute the operations corresponding to the modules.
The present application also provides a storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of any of the method embodiments described above when calculated.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Yet another embodiment of the present application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to calculate the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, acquiring an instruction input by a user, wherein the instruction is used for acting a target quantum logic gate on a target quantum bit;
S2, generating a plurality of calculation tasks according to the instruction, wherein each calculation task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
s3, determining the calculation sequence of each calculation task according to the dependency relationship among each calculation task, and carrying out parallel calculation on the calculation tasks with the same calculation sequence.
Specifically, the specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the optional implementation manners, and this embodiment is not repeated herein.
The foregoing detailed description of the construction, features and advantages of the present application will be presented in terms of embodiments illustrated in the drawings, wherein the foregoing description is merely illustrative of preferred embodiments of the application, and the scope of the application is not limited to the embodiments illustrated in the drawings.
Claims (10)
1. A method of quantum circuit simulation, the method comprising:
acquiring an instruction input by a user, wherein the instruction is used for acting a target quantum logic gate on a target quantum bit;
generating a plurality of computing tasks according to the instructions, wherein each computing task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
According to the dependency relationship between each computing task, determining the computing sequence of each computing task, and parallelly computing the computing tasks with the same computing sequence.
2. The method of claim 1, wherein determining the order of computation for each computing task based on the dependencies between each computing task comprises:
constructing a directed acyclic graph by using a topological sorting algorithm based on the dependency relationship between each computing task, wherein nodes of the directed acyclic graph represent the computing tasks, and edges of the directed acyclic graph represent the dependency relationship between the computing tasks;
and determining the calculation sequence of each calculation task according to the directed acyclic graph.
3. The method of claim 1, wherein the input variable and output variable are provided with virtual tags, the method further comprising:
determining virtual labels of input variables and output variables corresponding to each computing task based on the computing sequence of each computing task;
according to the calculation sequence, sequentially submitting calculation tasks with virtual labels of input variables being first virtual labels and virtual labels of output variables being second virtual labels to a task execution pool;
After one computing task of the task execution pool is executed, updating the virtual tag of the output variable of the computing task into the first virtual tag;
parallel computing of computing tasks in the same computing order, comprising:
and calculating the calculation tasks in parallel in the task execution pool.
4. A method according to claim 3, wherein the virtual tags of the input variables of the computing task are determined by virtual tags of the output variables of the computing task having a dependency relationship with the computing task and having a preceding computing order.
5. The method of claim 1, wherein the computing tasks include a slicing task, a matrix multiplication task, and a tensor product task;
the input variable of the slicing task is a quantum state corresponding to the target quantum bit;
the input variable of the matrix multiplication task is the output variable of the slicing task;
the input variable of the tensor product task is the output variable of the matrix multiplication task and/or the output variable of another tensor product task.
6. The method of claim 5, wherein the target qubit comprises a plurality of qubits, the processing operation of the slicing task is to slice a quantum state corresponding to the target qubit, and an output variable of the slicing task is a first quantum state of each qubit;
The processing operation of the matrix multiplication task is to perform matrix multiplication calculation on matrix representations of each first quantum state and the corresponding target quantum logic gate, and the output variable of the matrix multiplication task is a second quantum state of each quantum bit.
7. The method of claim 6, wherein the tensor product task processing is performed by performing tensor product calculations on the second quantum states of the qubit after completion of a matrix multiplication task execution.
8. A quantum circuit simulation device, the device comprising
The acquisition module is used for acquiring an instruction input by a user, wherein the instruction is used for acting the target quantum logic gate on the target quantum bit;
the generation module is used for generating a plurality of calculation tasks according to the instructions, wherein each calculation task comprises a processing operation and an input variable and an output variable corresponding to the processing operation;
and the computing module is used for determining the computing sequence of each computing task according to the dependency relationship among each computing task and parallelly computing the computing tasks with the same computing sequence.
9. A storage medium, characterized in that the storage medium has stored therein a computer program, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when calculated.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to calculate the computer program to perform the method of any of the claims 1 to 7.
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