CN117827724A - Digital-analog hybrid equalization receiver circuit - Google Patents
Digital-analog hybrid equalization receiver circuit Download PDFInfo
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Abstract
The invention provides a digital-analog mixed equalization receiver circuit, wherein a first/second high-speed input buffer in an analog domain has a linear equalization effect to compensate inter-code crosstalk introduced by a channel when a signal comparison function is completed; the skew deviation between the data and the clock can be solved by the first/second single bit delay chain; the first/second D trigger module and the parallel data output circuit are used for converting analog domain signals into digital domain signals and completing clock sampling, deserializing and speed reducing functions, meanwhile, the digital filter, the selector array and the digital calibration module in the digital domain are matched to complete decision feedback equalization together to further compensate attenuation caused by a channel, eye pattern quality of the signals is improved, meanwhile, feedback of a key time sequence path is completed in a low-speed digital domain, and the problem of difficult key time sequence convergence is solved.
Description
Technical Field
The invention relates to the technical field of signal equalization, in particular to a digital-analog hybrid equalization receiver circuit.
Background
With the trend of high performance computing and AI (Artificial Intelligence ) large models, the transmission bandwidth of the high-speed interface is continuously increased, so that attenuation, reflection and crosstalk on signals caused by transmission channels such as packaging and PCB (printed circuit board) are more serious, the size of a signal transmission eye diagram is continuously compressed, and the transmission reliability of the high-speed communication interface is seriously affected. In this regard, equalization techniques must be employed to improve eye quality and reduce the transmission error rate of the high speed interface. In the method, at the receiving end of the high-speed interface, equalization technologies such as CTLE (Continuous Time Linear Equalizer, duration linear equalization), DFE (Decision Feedback Equalizer ) and the like are often adopted, for example, in protocol interfaces such as DDR/uci/PCIE, etc., but as the signal rate is continuously improved, the design difficulty of an equalization circuit at the receiving end is continuously increased, the difficulty of timing convergence of a critical path and the complexity of the circuit are continuously improved, and the cost is continuously increased.
Disclosure of Invention
The invention provides a digital-analog hybrid equalization receiver circuit which is used for solving the defects of high difficulty and high circuit complexity of a receiving end equalization circuit in the prior art for timing sequence convergence of a critical path.
The invention provides a digital-analog hybrid equalization receiver circuit, comprising:
a first high-speed input buffer, a first single-bit delay chain, a first D flip-flop module, and a parallel data output circuit;
the first input end of the first high-speed input buffer is connected with an input signal, and the second input end of the first high-speed input buffer is connected with a first reference voltage; the first high-speed input buffer is used for carrying out linear equalization processing on the input signal to obtain a first linear equalization signal;
the first single-bit delay chain is used for carrying out delay processing on the first linear equalization signal to obtain a first delay signal;
the first D trigger module comprises a first D trigger and a second D trigger, the output end of the first single-bit delay chain is respectively connected with the data input ends of the first D trigger and the second D trigger, and the data output ends of the first D trigger and the second D trigger are connected with the input end of the parallel data output circuit;
the parallel data output circuit is used for performing deceleration processing on the first digital signal and the second digital signal output by the first D trigger and the second D trigger to obtain a first parallel low-speed signal.
The invention provides a digital-analog hybrid balanced receiver circuit, which also comprises a second high-speed input buffer, a second single-bit delay chain, a second D trigger module, a digital filter and a selector array;
wherein a first input terminal of the second high-speed input buffer is connected with the input signal, and a second input terminal is connected with a second reference voltage; the second high-speed input buffer is used for carrying out linear equalization processing on the input signal to obtain a second linear equalization signal; the second reference voltage is different from the first reference voltage;
the second single-bit delay chain is used for carrying out delay processing on the second linear equalization signal to obtain a second delay signal;
the second D trigger module comprises a third D trigger and a fourth D trigger, the output end of the second single-bit delay chain is respectively connected with the data input ends of the third D trigger and the fourth D trigger, and the data output ends of the third D trigger and the fourth D trigger are connected with the input end of the parallel data output circuit;
the parallel data output circuit is further used for performing deceleration processing on a third digital signal and a fourth digital signal output by the third D trigger and the fourth D trigger to obtain a second parallel low-speed signal;
the input end of the digital filter and the selector array is connected with the output end of the parallel data output circuit; the digital filter and selector array is configured to select, at a current time, an output signal at the current time from the first parallel low-speed signal and the second parallel low-speed signal based on a sampling value of the input signal at a previous time.
According to the present invention, the digital filter and selector array are configured to select, at a current time, an output signal at the current time from the first parallel low-speed signal and the second parallel low-speed signal based on a sampling value of the input signal at a previous time, and the digital filter and selector array specifically include:
when the sampling value of the input signal at the last moment is at a high level, the digital filter and selector array selects the second parallel low-speed signal as an output signal at the current moment;
when the sampling value of the input signal at the last moment is at a low level, the digital filter and selector array selects the first parallel low-speed signal as an output signal at the current moment;
wherein the first reference voltage is greater than the second reference voltage.
According to the digital-analog hybrid balanced receiver circuit provided by the invention, the digital-analog hybrid balanced receiver circuit further comprises a digital calibration module; the digital calibration module is used for providing an adjustable data clock signal, controlling the linear equalization intensity of the first high-speed input buffer and the second high-speed input buffer, controlling the delay precision and the delay degree of the first single-bit delay chain and the second single-bit delay chain, and controlling the opening and closing of a decision feedback equalization function.
According to the digital-analog hybrid equalization receiver circuit provided by the invention, when the decision feedback equalization function is turned off, the digital calibration module controls the second high-speed input buffer, the second single-bit delay chain and the second D trigger module to be turned off, controls the digital filter in the digital filter and selector array to be turned off and controls the selector array in the digital filter and selector array to output the first parallel low-speed signal.
According to the digital-analog hybrid equalization receiver circuit provided by the invention, the structure of the second high-speed input buffer is the same as that of the first high-speed input buffer.
According to the present invention, there is provided a digital-to-analog hybrid balanced receiver circuit, the first high-speed input buffer includes:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a coupling capacitor;
wherein a power supply is connected to sources of the first transistor, the second transistor, and the third transistor; the gate of the first transistor, the gate of the third transistor, the drain of the third transistor and the drain of the ninth transistor are connected; the grid electrode of the second transistor, the first end of the third resistor and the first end of the fourth resistor are connected; the drain electrode of the second transistor, the source electrode of the fourth transistor and the source electrode of the fifth transistor are connected; the drain of the first transistor is connected with the drain of the sixth transistor, and the drain of the first transistor and the drain of the sixth transistor jointly form an output end of the first high-speed input buffer;
the drain electrode of the fourth transistor, the first end of the coupling capacitor, the grid electrode of the sixth transistor, the first end of the first resistor and the drain electrode of the seventh transistor are connected; the input signal is connected with the grid electrode of the fourth transistor; the grid electrode of the fifth transistor is connected with the second end of the coupling capacitor; a drain of the fifth transistor, a first end of the second resistor, a drain of the eighth transistor, and a gate of the ninth transistor are connected;
a source of the sixth transistor, a source of the seventh transistor, a source of the eighth transistor, and a source of the ninth transistor are grounded; the gate of the seventh transistor, the second end of the third resistor, the second end of the first resistor, the second end of the fourth resistor, the second end of the second resistor and the gate of the eighth transistor are connected.
According to the digital-analog hybrid balanced receiver circuit provided by the invention, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are transistors of a first conductivity type, and the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are transistors of a second conductivity type, and the second conductivity type is different from the first conductivity type.
According to the digital-analog hybrid equalization receiver circuit provided by the invention, the trigger clock edge of the first D trigger and the trigger clock edge of the second D trigger are mutually differential.
According to the digital-analog hybrid equalization receiver circuit provided by the invention, the trigger clock edge of the third D trigger and the trigger clock edge of the fourth D trigger are mutually differential.
The invention provides a digital-analog hybrid equalization receiver circuit, which comprises a first high-speed input buffer, a first single-bit delay chain, a second single-bit delay chain, a first D trigger module, a second D trigger module, a parallel data output circuit, a digital filter, a selector array and a digital calibration module, wherein the whole receiver adopts a half-rate architecture to reduce power consumption, and the first high-speed input buffer and the second high-speed input buffer in an analog domain have a linear equalization effect to compensate inter-code crosstalk introduced by a channel when the function of signal comparison is completed; the skew deviation between the data and the clock can be solved by the first/second single bit delay chain; the first/second D trigger module and the parallel data output circuit are used for converting analog domain signals into digital domain signals and completing clock sampling, deserializing and speed reducing functions, meanwhile, the digital filter, the selector array and the digital calibration module in the digital domain are matched to complete decision feedback equalization together to further compensate attenuation caused by a channel, eye pattern quality of the signals is improved, meanwhile, feedback of a key time sequence path is completed in a low-speed digital domain, and the problem of difficult key time sequence convergence is solved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a digital-analog hybrid equalization receiver circuit according to the present invention;
fig. 2 is a schematic diagram of a digital-analog hybrid equalization receiver circuit according to the second embodiment of the present invention;
fig. 3 is a schematic diagram of decision feedback equalization timing provided in the present invention;
FIG. 4 is a schematic diagram of a first high-speed input buffer according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a digital-analog hybrid equalization receiver circuit according to the present invention, and as shown in fig. 1, the circuit includes: a first high-speed input buffer 110, a first single-bit delay chain 120, a first D flip-flop module 130, and a parallel data output circuit 140.
Wherein a first input terminal of the first high-speed input buffer 110 is connected to the input signal DQ, and a second input terminal is connected to a first reference voltage; the first high-speed input buffer 110 is used for performing linear equalization processing on the input signal DQ to obtain a first linear equalized signal DO1.
The first single-bit delay chain 120 is configured to delay the first linear equalization signal DO1 to obtain a first delayed signal.
The first D flip-flop module 130 includes a first D flip-flop 131 and a second D flip-flop 132, and the output terminal of the first single bit delay chain 120 is connected to the data input terminals of the first D flip-flop 131 and the second D flip-flop 132, respectively, and the data output terminals of the first D flip-flop 131 and the second D flip-flop 132 are connected to the input terminal of the parallel data output circuit 140. In some embodiments, the trigger clock edge of the first D flip-flop 131 and the trigger clock edge of the second D flip-flop 132 are differential from each other. For example, when the clock terminal of the first D flip-flop 131 is connected to the data clock signal DQS, the data clock signal DQS may be inverted and then connected to the clock terminal of the second D flip-flop 132.
The parallel data output circuit 140 is configured to perform a speed reduction process on the first digital signal evoh and the second digital signal ODDH output by the first D flip-flop 131 and the second D flip-flop 132, so as to obtain a first parallel low-speed signal.
In particular, in some low attenuation channel cases, the eye quality and margin of the input signal are large, and the embodiment can reduce the overall power consumption while improving the signal quality by only turning on the linear equalization function. The whole receiver circuit adopts a half-rate architecture to reduce power consumption, and a first high-speed input buffer in an analog domain has a linear equalization effect to compensate inter-code crosstalk introduced by a channel while finishing a signal comparison function; the skew deviation between the data and the clock can be solved through a first single-bit delay chain; the first D flip-flop module and the parallel data output circuit (which may be implemented by FIFO (First In First Out, first-in first-out) circuit) are configured to convert the analog domain signal into the digital domain signal and perform clock sampling, deserializing and speed reducing functions. At this time, the first parallel low-speed signal generated by the parallel data output circuit 140 is the final output signal of the digital-analog hybrid balanced receiver circuit, so that the overall power consumption of the receiver circuit is significantly reduced.
In addition, when the channel attenuation condition is serious, decision feedback equalization can be completed by matching with the digital filter and the selector array of the digital domain at the same time, so that the attenuation brought by the channel is further compensated, the eye pattern quality of the signal is improved, and meanwhile, the feedback of the key time sequence path is completed in the low-speed digital domain, so that the problem of difficult key time sequence convergence can be effectively solved.
Specifically, as shown in fig. 2, the digital-to-analog hybrid balanced receiver circuit further includes a second high-speed input buffer 210, a second single-bit delay chain 220, a second D flip-flop module 230, and a digital filter and selector array 150.
Wherein a first input terminal of the second high-speed input buffer 210 is connected to the input signal DQ, and a second input terminal is connected to the second reference voltage; the second high-speed input buffer 210 is configured to perform linear equalization on the input signal DQ to obtain a second linear equalized signal DO2. Here, the dc offset and the balance coefficient of the first high-speed input buffer 110 and the second high-speed input buffer 210 are different, so that the second reference voltage is different from the first reference voltage. In addition, the structure of the second high-speed input buffer may be the same as that of the first high-speed input buffer.
The second single-bit delay chain 220 is configured to delay the second linear equalization signal DO2 to obtain a second delayed signal.
The second D flip-flop module 230 includes a third D flip-flop 231 and a fourth D flip-flop 232, and the output terminal of the second single bit delay chain 220 is connected to the data input terminals of the third D flip-flop 231 and the fourth D flip-flop 232, respectively, and the data output terminals of the third D flip-flop 231 and the fourth D flip-flop 232 are connected to the input terminal of the parallel data output circuit 140. In some embodiments, the trigger clock edge of the third D flip-flop 231 and the trigger clock edge of the fourth D flip-flop 232 are differential from each other. For example, when the clock terminal of the third D flip-flop 231 is connected to the data clock signal DQS, the data clock signal DQS may be inverted and then connected to the clock terminal of the fourth D flip-flop 232.
The parallel data output circuit 140 is further configured to perform a speed reduction process on the third digital signal EVEL and the fourth digital signal ODDL output by the third D flip-flop 231 and the fourth D flip-flop 232, so as to obtain a second parallel low-speed signal. In some embodiments, the parallel data output circuit 140 may include a first FIFO circuit 141 and a second FIFO circuit 142. The input end of the first FIFO circuit 141 is connected to the output ends of the first D flip-flop 131 and the second D flip-flop 132, and the output end outputs a first parallel low-speed signal and is connected to the input end of the digital filter and selector array 150; the input of the second FIFO circuit 142 is connected to the outputs of the third D flip-flop 231 and the fourth D flip-flop 232, and the output outputs the second parallel low-speed signal and is connected to the input of the digital filter and selector array 150. In other embodiments, a separate FIFO circuit may be used to form the parallel data output circuit 140 to receive the output signals of the four-way D flip-flops.
The digital filter and selector array 150 is mainly used for performing a decision feedback equalization function, and its input terminal is connected to the output terminal of the parallel data output circuit 140 to receive the first parallel low-speed signal and the second parallel low-speed signal. The digital filter and selector array 150 stores the historical data and selects the data coming from the current time according to the sampling value of the input signal DQ at the previous time, and selects the correct signal from the first parallel low-speed signal and the second parallel low-speed signal as the output signal at the current time, thereby achieving the effect of decision feedback equalization. The first parallel low-speed signal and the second parallel low-speed signal are assumed to be N-bit parallel low-speed data, and the speed is 1/N of the input signal DQ, so that the requirement of a critical timing path is reduced to 1/N times of the original requirement. Here, in the prior art, the critical path timing feedback requirement of the DFE is often 1 UI (Unit Interval,1bit signal width) time of the input signal, when the speed of the input signal is continuously increased, the critical path timing feedback difficulty is gradually increased, if the speed cannot be satisfied, a degradation effect is generated on the signal, and the equalization is disabled. Therefore, in the embodiment of the present invention, the timing feedback of the critical path is performed in the digital domain, and the first parallel low-speed data and the second parallel low-speed data output by the parallel data output circuit 140 are both N-bit parallel low-speed data after deserializing in the digital domain, and the rate is 1/N of the input signal DQ, so that the critical timing path requirement is reduced to 1/N of the original one, thereby significantly alleviating the convergence difficulty of the critical timing path.
In some embodiments, the digital filter and selector array 150 is configured to select, at a current time, an output signal at the current time from the first parallel low-speed signal and the second parallel low-speed signal based on a sampling value of the input signal at a previous time, and specifically includes:
when the sampling value of the input signal at the last moment is at a high level, the digital filter and selector array selects the second parallel low-speed signal as an output signal at the current moment;
when the sampling value of the input signal at the last moment is at a low level, the digital filter and selector array selects the first parallel low-speed signal as an output signal at the current moment;
wherein the first reference voltage is greater than the second reference voltage.
Specifically, fig. 3 is a schematic diagram of decision feedback equalization timing provided by the present invention, as shown in fig. 3, the amplitude of the first reference voltage VREFH is half of the amplitude of the DQ level of the input signal plus the dc offset calibration voltage and the first DFE equalization coefficient voltage required by the first high-speed input buffer 110; the magnitude of the second reference voltage VREFL is half the magnitude of the DQ level of the input signal plus the dc offset calibration voltage and the second DFE equalization coefficient voltage required by the second high-speed input buffer 210. It should be noted that the first DFE equalizing voltage and the second DFE equalizing voltage are often opposite coefficients, so the first reference voltage VREFH is greater than the second reference voltage VREFL, so the DO1 signal output from the first high-speed input buffer 110 has a wider "0" sampling margin, so that the signal margin of sampling "0" in the deserialized first parallel low-speed signal is large, and the correct probability is higher; the DO2 signal output from the second high-speed input buffer 210 has a wider sampling margin of "1", so that the signal margin of sampling "1" in the deserialized second parallel low-speed signal is large and the correct probability is higher.
Since the input signal DQ is often random data, and has any bit0 and bit1, as shown by the arrow in fig. 3, when the input signal is sampled to "1" at the previous time, the data filter and selector array 150 will select the parallel low-speed signal corresponding to DO2 as the correct data, i.e. the second parallel low-speed signal, from the data coming at the current time; when the input signal at the previous moment is sampled to be 0, the data filter and selector array 150 selects the data of the parallel low-speed signal corresponding to DO1 as correct data, namely the first parallel low-speed signal, so that the whole output signal obtains wider sampling margin, the sampling margin of an eye pattern is expanded, and the effect of decision feedback equalization is realized.
In some embodiments, the digital-to-analog hybrid equalization receiver circuit further includes a digital calibration module 160. The digital calibration module 160 contains a hardware calibration algorithm for providing an adjustable data clock signal DQS, controlling the linear equalization strength of the first and second high-speed input buffers 110, 210, controlling the delay accuracy and delay degree of the first and second single-bit delay chains 120, 220, and controlling the switching on and off of the decision feedback equalization function.
Specifically, the adjustable data clock signal DQS provided by the digital calibration module 160 is used to provide the trigger signal for each D flip-flop, and the data clock signal DQS may be a single-ended DQS clock, and ensures that the trigger clock edges of the first D flip-flop 131 and the third D flip-flop 231 are different from the trigger clock edges of the second D flip-flop 132 and the fourth D flip-flop 232. In other embodiments, the data clock signal DQS is a differential clock such that the trigger clock edges of the first D flip-flop 131 and the third D flip-flop 231 are differential from the trigger clock edges of the second D flip-flop 132 and the fourth D flip-flop 232, respectively.
The first and second high-speed input buffers 110 and 210 further include a digital enable control access terminal coupled to the digital calibration module 160 for controlling the strength of the linear equalization. The first single bit delay chain 120 and the second single bit delay chain 220 further include digital enable control access terminals coupled to the digital calibration module 160 for controlling the accuracy and range of the delay time. In addition, the digital calibration module 160 can also provide two-dimensional scanning and training functions of an eye diagram, thereby improving flexibility and reliability of the receiver.
In addition, the digital calibration module 160 is further connected to the digital filter and selector array 150, and controls the decision feedback equalization function to be turned on and off. When the decision feedback equalization function is turned off, the digital calibration module 160 controls the second high-speed input buffer 210, the second single-bit delay chain 220, and the second D flip-flop module 230 to be turned off, controls the digital filters in the digital filter and selector array 150 to be turned off, and controls the selector arrays in the digital filter and selector array 150 to output the first parallel low-speed signal. When the decision feedback equalization function is turned on, the digital calibration module 160 controls the second high-speed input buffer 210, the second single-bit delay chain 220, and the second D flip-flop module 230 to be turned on, and controls the digital filter and selector array 150 to perform signal selection in the manner given in the above embodiments, and selects the correct signal from the first parallel low-speed signal and the second parallel low-speed signal to output.
In other embodiments, the first high-speed input buffer 110 and the second high-speed input buffer 210 are configured identically, are self-biased input buffers, have a linear equalization effect, and provide full-swing analog domain signal output. The first high-speed input buffer 110 is described as follows:
as shown in fig. 4, the first high-speed input buffer 110 includes a first transistor 1101, a second transistor 1102, a third transistor 1103, a fourth transistor 1104, a fifth transistor 1105, a sixth transistor 1106, a seventh transistor 1107, an eighth transistor 1108, a ninth transistor 1109, a first resistor 1110, a second resistor 1111, a third resistor 1112, a fourth resistor 1113, and a coupling capacitor 1114;
wherein the power supply is connected to the sources of the first transistor 1101, the second transistor 1102, and the third transistor 1103; a gate of the first transistor 1101, a gate of the third transistor 1103, a drain of the third transistor 1103, and a drain of the ninth transistor 1109 are connected; the gate of the second transistor 1102, the first terminal of the third resistor 1112, and the first terminal of the fourth resistor 1113 are connected; the drain of the second transistor 1102, the source of the fourth transistor 1104, and the source of the fifth transistor 1105 are connected; the drain of the first transistor 1101 and the drain of the sixth transistor 1106 are connected, and the drain of the first transistor 1101 and the drain of the sixth transistor 1106 together constitute the output terminal of the first high-speed input buffer 110;
the drain of the fourth transistor 1104, the first end of the coupling capacitor 1114, the gate of the sixth transistor 1106, the first end of the first resistor 1110, and the drain of the seventh transistor 1107 are connected; the input signal DQ and the gate of the fourth transistor 1104 are connected; the first reference voltage, the gate of the fifth transistor 1105 and the second end of the coupling capacitor 1114 are connected; a drain of the fifth transistor 1105, a first end of the second resistor 1111, a drain of the eighth transistor 1108, and a gate of the ninth transistor 1109 are connected;
a source of the sixth transistor 1106, a source of the seventh transistor 1107, a source of the eighth transistor 1108, and a source of the ninth transistor 1109 are grounded; the gate of the seventh transistor 1107, the second terminal of the third resistor 1112, the second terminal of the first resistor 1110, the second terminal of the fourth resistor 1113, the second terminal of the second resistor 1111, and the gate of the eighth transistor 1108 are connected.
Wherein the drain of the fourth transistor 1104 is connected to the first terminal of the coupling capacitor 1114 for compensating the gain difference between VON and VOP at the high frequency component of the signal shown in fig. 4; fourth transistor 1104 and fifth transistor 1105 provide the first stage transconductance for first high speed input buffer 110 for the first stage signal input pair; the seventh transistor 1107 and the adjustable first resistor 1110, the eighth transistor 1108 and the adjustable second resistor 1111 respectively form an active inductive load, and provide adjustable gain and linear equalization effects; the second transistor 1102 is a first-stage current source, and the gate bias of the second transistor is connected with a common-mode feedback resistor formed by a first resistor 1110, a second resistor 1111, a third resistor 1112 and a fourth resistor 1113; the sixth transistor 1106 and the ninth transistor 1109 are second-stage signal input pair transistors, and gate inputs thereof are connected to VON and VOP, respectively; the first transistor 1101 and the third transistor 1103 constitute a second active load, and a pseudo-differential structure is employed to provide a full swing output.
It should be noted that in the prior art, linear equalization is often completed by adopting an RC resistor-capacitor array, which brings about larger area cost, and in the embodiment of the present invention, an active inductive load is respectively formed by a seventh transistor 1107 and an adjustable first resistor 1110, an eighth transistor 1108 and an adjustable second resistor 1111 to provide a linear equalization effect, so that the area of the input buffer can be significantly reduced; meanwhile, in the embodiment of the invention, a self-bias structure is adopted to stabilize the current bias and output differential signal common mode, and a coupling capacitor 1114 is adopted to reduce the high-frequency gain difference of the output differential signal existing in the single-ended buffer to a certain extent, so that the duty ratio of the output signal is improved.
In some embodiments, the first transistor 1101, the second transistor 1102, the third transistor 1103, the fourth transistor 1104, and the fifth transistor 1105 are transistors of a first conductivity type, and the sixth transistor 1106, the seventh transistor 1107, the eighth transistor 1108, and the ninth transistor 1109 are transistors of a second conductivity type, which is different from the first conductivity type.
In other embodiments, the digital-to-analog hybrid balanced receiver circuit further includes a generation circuit for generating the first reference voltage and the second reference voltage.
In summary, the digital-analog hybrid balanced receiver circuit provided by the embodiment of the invention includes a first/second high-speed input buffer, a first/second single-bit delay chain, a first/second D flip-flop module, a parallel data output circuit, a digital filter, a selector array and a digital calibration module, wherein the overall receiver adopts a half-rate architecture to reduce power consumption, and the first/second high-speed input buffer in the analog domain has a linear equalization effect to compensate inter-code crosstalk introduced by a channel while finishing the function of signal comparison; the skew deviation between the data and the clock can be solved by the first/second single bit delay chain; the first/second D trigger module and the parallel data output circuit are used for converting analog domain signals into digital domain signals and completing clock sampling, deserializing and speed reducing functions, meanwhile, the digital filter, the selector array and the digital calibration module in the digital domain are matched to complete decision feedback equalization together to further compensate attenuation caused by a channel, eye pattern quality of the signals is improved, meanwhile, feedback of a key time sequence path is completed in a low-speed digital domain, and the problem of difficult key time sequence convergence is solved.
It should be noted that although the technical methods of the embodiments of the present invention are described in a particular order in the above embodiments, this does not require or imply that these circuits must be fabricated in accordance with the particular block diagrams or that all of the illustrated circuits must be implemented to achieve the desired results. In contrast, the related circuits of the present embodiment can change the execution order. Additionally or alternatively, certain circuits may be omitted, multiple circuits combined into one circuit, and/or one circuit decomposed into multiple circuits.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of a certain embodiment that are not described in detail in the drawings, reference may be made to the related descriptions of other embodiments.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A digital-to-analog hybrid balanced receiver circuit comprising:
a first high-speed input buffer, a first single-bit delay chain, a first D flip-flop module, and a parallel data output circuit;
the first input end of the first high-speed input buffer is connected with an input signal, and the second input end of the first high-speed input buffer is connected with a first reference voltage; the first high-speed input buffer is used for carrying out linear equalization processing on the input signal to obtain a first linear equalization signal;
the first single-bit delay chain is used for carrying out delay processing on the first linear equalization signal to obtain a first delay signal;
the first D trigger module comprises a first D trigger and a second D trigger, the output end of the first single-bit delay chain is respectively connected with the data input ends of the first D trigger and the second D trigger, and the data output ends of the first D trigger and the second D trigger are connected with the input end of the parallel data output circuit;
the parallel data output circuit is used for performing deceleration processing on the first digital signal and the second digital signal output by the first D trigger and the second D trigger to obtain a first parallel low-speed signal.
2. The digital to analog hybrid balanced receiver circuit according to claim 1, further comprising a second high speed input buffer, a second single bit delay chain, a second D flip-flop module, and a digital filter and selector array;
wherein a first input terminal of the second high-speed input buffer is connected with the input signal, and a second input terminal is connected with a second reference voltage; the second high-speed input buffer is used for carrying out linear equalization processing on the input signal to obtain a second linear equalization signal; the second reference voltage is different from the first reference voltage;
the second single-bit delay chain is used for carrying out delay processing on the second linear equalization signal to obtain a second delay signal;
the second D trigger module comprises a third D trigger and a fourth D trigger, the output end of the second single-bit delay chain is respectively connected with the data input ends of the third D trigger and the fourth D trigger, and the data output ends of the third D trigger and the fourth D trigger are connected with the input end of the parallel data output circuit;
the parallel data output circuit is further used for performing deceleration processing on a third digital signal and a fourth digital signal output by the third D trigger and the fourth D trigger to obtain a second parallel low-speed signal;
the input end of the digital filter and the selector array is connected with the output end of the parallel data output circuit; the digital filter and selector array is configured to select, at a current time, an output signal at the current time from the first parallel low-speed signal and the second parallel low-speed signal based on a sampling value of the input signal at a previous time.
3. The digital-analog hybrid balanced receiver circuit according to claim 2, wherein the digital filter and selector array is configured to select, at a current time, an output signal at the current time from the first parallel low-speed signal and the second parallel low-speed signal based on a sampling value of the input signal at a previous time, specifically comprising:
when the sampling value of the input signal at the last moment is at a high level, the digital filter and selector array selects the second parallel low-speed signal as an output signal at the current moment;
when the sampling value of the input signal at the last moment is at a low level, the digital filter and selector array selects the first parallel low-speed signal as an output signal at the current moment;
wherein the first reference voltage is greater than the second reference voltage.
4. The digital-to-analog hybrid balanced receiver circuit according to claim 2, further comprising a digital calibration module; the digital calibration module is used for providing an adjustable data clock signal, controlling the linear equalization intensity of the first high-speed input buffer and the second high-speed input buffer, controlling the delay precision and the delay degree of the first single-bit delay chain and the second single-bit delay chain, and controlling the opening and closing of a decision feedback equalization function.
5. The digital to analog hybrid equalization receiver circuit of claim 4, wherein when a decision feedback equalization function is turned off, said digital calibration module controls said second high speed input buffer, said second single bit delay chain, and said second D flip-flop module to turn off and controls said digital filter and the digital filter in the selector array to turn off and controls the digital filter and the selector array in the selector array to output said first parallel low speed signal.
6. The digital-to-analog hybrid balanced receiver circuit according to claim 2, wherein the second high-speed input buffer has the same structure as the first high-speed input buffer.
7. A digital-to-analog hybrid balanced receiver circuit according to any of claims 1 to 6, wherein the first high-speed input buffer comprises:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a coupling capacitor;
wherein a power supply is connected to sources of the first transistor, the second transistor, and the third transistor; the gate of the first transistor, the gate of the third transistor, the drain of the third transistor and the drain of the ninth transistor are connected; the grid electrode of the second transistor, the first end of the third resistor and the first end of the fourth resistor are connected; the drain electrode of the second transistor, the source electrode of the fourth transistor and the source electrode of the fifth transistor are connected; the drain of the first transistor is connected with the drain of the sixth transistor, and the drain of the first transistor and the drain of the sixth transistor jointly form an output end of the first high-speed input buffer;
the drain electrode of the fourth transistor, the first end of the coupling capacitor, the grid electrode of the sixth transistor, the first end of the first resistor and the drain electrode of the seventh transistor are connected; the input signal is connected with the grid electrode of the fourth transistor; the grid electrode of the fifth transistor is connected with the second end of the coupling capacitor; a drain of the fifth transistor, a first end of the second resistor, a drain of the eighth transistor, and a gate of the ninth transistor are connected;
a source of the sixth transistor, a source of the seventh transistor, a source of the eighth transistor, and a source of the ninth transistor are grounded; the gate of the seventh transistor, the second end of the third resistor, the second end of the first resistor, the second end of the fourth resistor, the second end of the second resistor and the gate of the eighth transistor are connected.
8. The digital-to-analog hybrid balanced receiver circuit according to claim 7, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are transistors of a first conductivity type, and the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type.
9. The digital-to-analog hybrid balanced receiver circuit of claim 1, wherein the trigger clock edge of the first D flip-flop and the trigger clock edge of the second D flip-flop are differential from each other.
10. The digital-to-analog hybrid balanced receiver circuit according to claim 2, wherein the trigger clock edge of the third D flip-flop and the trigger clock edge of the fourth D flip-flop are differential from each other.
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| US20170031653A1 (en) * | 2015-07-27 | 2017-02-02 | SK Hynix Inc. | Buffer, semiconductor apparatus and semiconductor system using the same |
| US20180262374A1 (en) * | 2017-03-08 | 2018-09-13 | Credo Technology Group Limited | Finite impulse response analog receive filter with amplifier-based delay chain |
| CN112564703A (en) * | 2020-12-22 | 2021-03-26 | 北京时代民芯科技有限公司 | Front stage time error correction circuit of multi-channel time domain interleaved data converter |
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