CN117827722A - Signal processing method and device of binary multiplexer and multiplexer - Google Patents
Signal processing method and device of binary multiplexer and multiplexer Download PDFInfo
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Abstract
The invention discloses a signal processing method and device of a binary multiplexer and the multiplexer, wherein the method comprises the following steps: selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer; the subtree of any one data port of the target multiplexer is turned over to obtain a turning multiplexer; and searching and inputting corresponding target input signals in a preset signal mapping list according to the connection sequence of a plurality of alternative multiplexers of the flip multiplexer. The invention can arbitrarily select one from a plurality of two-way multiplexers of the binary multiplexer as a target multiplexer; the subtree of any data port of the target multiplexer is turned over, and the corresponding target input signal is searched in the preset signal mapping list and is input into the turned multiplexer, so that the fan-out of the circuit can be reduced, no additional element is required, the circuit structure can be simplified, and the waste of wiring resources is avoided.
Description
Technical Field
The present invention relates to the field of digital circuit control, and in particular, to a signal processing method and apparatus for a binary multiplexer, and a multiplexer.
Background
A binary multiplexer (Binary Multiplexer, abbreviated as binary-mux) is a multiplexer with binary codes at the select inputs, and is a common circuit element in the logic synthesis process of digital circuits, and is used for describing the logic behavior of a selection signal to select one of multiple sets of data as an output. The selection terminal of the binary multiplexer is generally denoted by sel, the bit width of the selection terminal is n, and the number of data terminals is 2n.
With the circuit model structure of the binary-mux unchanged, the maximum fan-out of the selector is determined by sel [ n-1:0] and the maximum fan-out is exponentially trending. When the number of fan-outs of one signal is larger, the delay of the layout and wiring is also larger, resulting in an increase in circuit delay, and therefore, it is necessary to reduce the circuit fan-out. The current method is the buf inserting method, which inserts x bufs in the output direction of the multiplexer and adjusts the circuit structure to reduce the fanout of the circuit output.
However, the following technical problems are commonly used at present: the more multiplexers are provided, the more buf elements are added, the more complicated the circuit wiring is, and the more wiring paths are. Not only is the timing path extended, but more routing resources are also occupied.
Disclosure of Invention
The invention provides a signal processing method and device of a binary multiplexer and the multiplexer, and the method can solve one or more of the technical problems.
A first aspect of an embodiment of the present invention provides a signal processing method of a binary multiplexer, the method being applicable to a binary multiplexer composed of a plurality of one-out-of-two multiplexers, the method comprising:
when an initial input signal of a unit width is input to the binary multiplexer, arbitrarily selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer;
the method comprises the steps that a subtree of any one data port of a target multiplexer is turned to obtain a turned multiplexer, the subtree is formed by connecting a plurality of two-for-one multiplexers, and the turning treatment means turning the plurality of two-for-one multiplexers;
and searching and inputting a corresponding target input signal in a preset signal mapping list according to the connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, wherein the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
In a possible implementation manner of the first aspect, the flipping processing of the subtree of any one data port of the target multiplexer to obtain a flipped subtree includes:
selecting one port as a target port from two data ports of the target multiplexer at will;
and turning over a plurality of one-out-of-two multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
In a possible implementation manner of the first aspect, the searching and inputting the corresponding target input signal in the preset signal mapping list according to the connection sequence of the plurality of one-out-of-two multiplexers of the flip multiplexer includes:
determining the connection sequence of a plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer;
and searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turnover multiplexer after forming a data input vector.
In a possible implementation manner of the first aspect, the operation of constructing the preset signal mapping list includes:
acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer;
and determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
A second aspect of an embodiment of the present invention provides a signal processing apparatus for a binary multiplexer, the apparatus being adapted for a binary multiplexer composed of a plurality of one-out-of-two multiplexers, the apparatus comprising:
a selection module for arbitrarily selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer when an initial input signal of a unit width is input to the binary multiplexer;
the overturning module is used for overturning a subtree of any one data port of the target multiplexer to obtain an overturning multiplexer, the subtree is formed by connecting a plurality of one-out-of-two multiplexers, and the overturning processing means overturning the plurality of one-out-of-two multiplexers;
and the signal processing module is used for searching and inputting a corresponding target input signal in a preset signal mapping list according to the connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, wherein the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
In a possible implementation manner of the second aspect, the flipping processing of the subtree of any one of the data ports of the target multiplexer obtains a flipped subtree, which includes:
selecting one port as a target port from two selected ports of the target multiplexer at will;
and turning over a plurality of one-out-of-two multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
In a possible implementation manner of the second aspect, the searching and inputting the corresponding target input signal in the preset signal mapping list according to the connection sequence of the plurality of one-out-of-two multiplexers of the flip multiplexer includes:
determining the connection sequence of a plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer;
and searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turnover multiplexer after forming a data input vector.
In a possible implementation manner of the second aspect, the operation of constructing the preset signal mapping list includes:
acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer;
and determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
A third aspect of an embodiment of the present invention provides a binary multiplexer suitable for a signal processing method of the binary multiplexer as described above, the binary multiplexer comprising: and the two-in-one multiplexers are provided with two data ports, one selection port and one output port.
Compared with the prior art, the signal processing method and device for the binary multiplexer and the multiplexer provided by the embodiment of the invention have the beneficial effects that: the invention can arbitrarily select one from a plurality of two-way multiplexers of the binary multiplexer as a target multiplexer; the subtree of any data port of the target multiplexer is turned over, and the corresponding target input signal is searched in the preset signal mapping list and is input into the turned multiplexer, so that the fan-out of the circuit can be reduced, no additional element is required, the circuit structure can be simplified, and the waste of wiring resources is avoided.
Drawings
FIG. 1 is a schematic diagram of a binary multiplexer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an alternative multiplexer according to an embodiment of the present invention;
FIG. 3 is a flow chart of a signal processing method of a binary multiplexer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a flip-flop multiplexer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a non-flipped binary multiplexer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a flipped binary multiplexer according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a signal processing method of a binary multiplexer according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a signal processing device of a binary multiplexer according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to solve the above problems, a signal processing method of a binary multiplexer according to the present embodiment will be described and illustrated in detail by the following specific embodiments.
Referring to fig. 1, a schematic diagram of a binary multiplexer according to an embodiment of the present invention is shown.
Wherein, as an example, the binary multiplexer may include: a plurality of one-out-of-two multiplexers.
Referring to fig. 2, a schematic diagram of an alternative multiplexer according to an embodiment of the invention is shown.
The one-out-of-two Multiplexer (mux 21) is a Multiplexer having only one select port, one output port and two data ports.
In one embodiment, the select port is denoted by sel, the bit width is n, and the number of data ports is 2n. The input data signals may be represented by d0, d1, d2 … d (2 n-1), respectively. The output signal is denoted by out, and its connection circuit structure may be as shown in fig. 1.
Assuming a bit width of n, the select ports of the plurality of one-for-two multiplexers of the first column are sel [0], the select ports of the plurality of one-for-two multiplexers of the second column are sel [1], until the select port of one of the one-for-two multiplexers of the last column is sel [ n-1].
The output ports of the two multiplexers with the selection ports of sel [0] are respectively connected with the two data ports of the two multiplexers with the selection ports of sel [1], the output ports of the two multiplexers with the selection ports of sel [1] are respectively connected with the two data ports of the two multiplexers with the selection ports of sel [2], and so on until the output ports of the two multiplexers with the selection ports of sel [ n-2] are respectively connected with the two data ports of the two multiplexers with the selection ports of sel [ n-1], as shown in fig. 1.
For further explanation, it is assumed that the one-out-of-two multiplexer of the present invention is an one-out-of-8-1 binary multiplexer, 8=2 3 So select port is 3 bits, denoted by sel; the number of the data ports is 8, and the data ports are respectively represented by i0, i1, i2, i3, i4, i5, i6 and i 7; when the code of sel is 000, selecting the input signal of i0 as output; when the code of sel is 001, selecting the input signal of i1 as output; when sel has a code of 010, the input signal of i2 is selected as the output, and so on.
Referring to fig. 3, a flow chart of a signal processing method of a binary multiplexer according to an embodiment of the invention is shown.
In an embodiment, the method is applied to a binary multiplexer as described in the above embodiments. The binary multiplexer includes a plurality of one-out-of-two multiplexers.
The signal processing method of the binary multiplexer may include:
s11, when an initial input signal with unit width is input to the binary multiplexer, one target multiplexer is arbitrarily selected from a plurality of two-way multiplexers of the binary multiplexer.
In one embodiment, the initial input signal may be obtained and then input to the one-out-of-two multiplexer of the first column, and in this process, one may be arbitrarily selected from the plurality of one-out-of-two multiplexers, to obtain a target multiplexer.
Assuming that the binary multiplexer is structured as shown in fig. 1, the present invention can arbitrarily select one of them, for example, a one-out-of-two multiplexer whose one selection port is sel [0], a one-out-of-two multiplexer whose one selection port is sel [ n-5], or a one-out-of-two multiplexer whose one selection port is sel [ n-1], and the selected one-out-of-two multiplexer is the target multiplexer.
S12, performing overturn processing on a subtree of any one data port of the target multiplexer to obtain an overturn multiplexer, wherein the subtree is formed by connecting a plurality of one-out-of-two multiplexers, and the overturn processing refers to overturn of the plurality of one-out-of-two multiplexers.
In one embodiment, after determining the target multiplexer, the sub-tree of the selected data port may be flipped from either of the two data ports of the target multiplexer, thereby converting the entire binary multiplexer into a flipped multiplexer.
With reference to fig. 1, a port with a data port of 0 is connected to a one-out-of-two multiplexer with a data port of sel [ n-3] and a one-out-of-two multiplexer … with a data port of sel [ n-4] until the data port of sel [ n-2] is a one-out-of-two multiplexer. Such a structure may be a subtree.
After the subtree is selected, a plurality of one-out-of-two multiplexers in the subtree can be turned over, and the positions of the plurality of one-out-of-two multiplexers are interchanged so that the positions of the plurality of one-out-of-two multiplexers are changed.
In an alternative embodiment, step S12 may comprise the sub-steps of:
s121, selecting one port as a target port from two data ports of the target multiplexer.
S122, turning over a plurality of alternative multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
Referring to fig. 4, a schematic diagram of a flip-flop multiplexer according to an embodiment of the present invention is shown.
Suppose that one target multiplexer is selected in the binary multiplexer of fig. 1, whose selection port is sel n-1. Either one of the left subtree (subtree of sel n-1=0) or the right subtree (subtree of sel n-1=1) may then be selected starting from the root node of the target multiplexer.
Assuming that a subtree of sel n-1=0 of the target multiplexer is selected, that is, a port with a data port of 0 is determined as the target port, and then a plurality of one-out-of-two multiplexers of the subtree corresponding to the port can be flipped left and right. The inverted structure is shown in fig. 4.
For sel [ n-1]]Subtree sel [0] of=0]～sel[n-2]Signal inversion, for example: sel [ n-1]]The subtree of =0, the sel signal of mux21 is { sel [0] in order from the leaf node to the root node of the tree],sel[1],sel[2],……,sel[n-3],sel[n-2]Referring to FIG. 1, the sequence obtained by sequentially toggling the sel signal of mux21 from the leaf node to the root node of the tree is { sel [ n-2]],sel[n-3],sel[n-4],……,sel[1],sel[0]And the leaf node inputs (d 0-d (2) n-1 -1) the input vector) will also change to { sel [ n-2] due to the selection signal],sel[n-3],sel[n-4],……,sel[1],sel[0]And change order.
Referring to fig. 4, for ease of understanding, the subtree of sel [ n-1] =1 is not flipped and the subtree of sel [ n-1] =0 is flipped. The sub-tree of sel [ n-1] =1, the corresponding plurality of select ports of the one-out-of-two multiplexers are in order from left to right, sel [0], sel [1], sel [2] … sel [ n-3], sel [ n-2], and then to el [ n-1]. And sub-trees of sel [ n-1] =0, the corresponding plurality of select ports of the one-out-of-two multiplexers are, in left to right order, sel [ n-2], sel [ n-3], sel [2] … sel [0] to el [ n-1].
After the flip is completed, this binary multiplexer may become a flip multiplexer.
S13, searching and inputting a corresponding target input signal in a preset signal mapping list according to the connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, wherein the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
The sub-tree of the target multiplexer is transferred to a binary multiplexer to be changed into a turning multiplexer, at this time, the connection sequence of a plurality of one-out-of-two multiplexers of the turning multiplexer can be obtained, then the corresponding target input signal is searched in a preset signal mapping list according to the type of the data port corresponding to the connection sequence, and then the target input signal is input to the turning multiplexer, so that an output signal is obtained.
In an embodiment, the preset signal mapping list is a table made by using a mapping relation after the binary multiplexer receives an initial input signal, maps the included selection port and data port of the alternative multiplexer and determines the mapping relation.
Wherein, as an example, the construction operation of the preset signal mapping list may include the following sub-steps:
s21, acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer.
S22, determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
In one implementation, the input to the select port may be represented by a vector: (sel [0]],sel[1]…sel[n-1]) The method comprises the steps of carrying out a first treatment on the surface of the Similarly, the input to the data port may be represented by a vector: (d 0, d1, … d (2) n -1))。
The mapping relation between the selected port and the data port, namely, the mapping relation between d and sel can be recorded, and then the mapping relation between d and sel is recorded to obtain a preset signal mapping list, which is specifically shown in the following table:
referring to the above table, when the input signal is d0, the output of the one-out-of-two multiplexer whose selection port is sel [0] is 0, the output of the one-out-of-two multiplexer whose selection port is sel [1] is 0, the output of the one-out-of-two multiplexer whose selection port is sel [2..n-2] is 0, and the output of the one-out-of-two multiplexer whose selection port is sel [ n-1] is 0.
When the input signal is d3, the output of the one-out-of-two multiplexer with the selection port sel [0] is 1, the output of the one-out-of-two multiplexer with the selection port sel [1] is 1, the output of the one-out-of-two multiplexer with the selection port sel [2..n-2] is 0, and the output of the one-out-of-two multiplexer with the selection port sel [ n-1] is 0.
In one embodiment, step S13 may include the sub-steps of:
s131, determining the connection sequence of the plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer.
S132, searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turning multiplexer after forming a data input vector.
After the inversion is completed, the inverted input signal and the signals corresponding to the data ports of each of the two-in-one multiplexers are required to be determined, and the connection sequence of the plurality of two-in-one multiplexers corresponding to each of the sub-trees of the inversion multiplexer can be determined.
As shown in fig. 4, the corresponding connection order may be obtained, and the signal output result of each of the two-in-one multiplexers in the connection order may be determined, where the signal output result is the result of the binary multiplexer receiving the initial input signal.
Then, a corresponding data input vector can be searched in the preset signal mapping list according to the output result, and a signal corresponding to the data input vector is taken as a target input signal.
Inputs d0 to d (2 n-1 -1) the order will be rearranged, but the inputs to the non-leaf nodes need not be changed.
In one embodiment, the flip may be followed by a trend of the sel vector from top to bottom, generating ordered binary numbers, and for each binary number, finding the corresponding d input by looking up the upper table and storing in the new data input vector.
For example, it is determined that the select port is sel [ n-2]]The output of the one-out-of-two multiplexer of (1) and the select port is sel [ n-3]]The output of the one-out-of-two multiplexer is 0 and the select port is sel n-4..1]The output of the one-out-of-two multiplexer of (2) is 0 and the select port is sel 0]The output of the one-out-of-two multiplexer of (2) is 0 and the select port is sel 1]The output of the alternative multiplexer of (a) is 0, and according to the arrangement sequence, the data input vector d (2) n-2 ) Then d (2 n-2 ) For the target input signal, the input to the first select port is sel [ n-2]]The data port of the multiplexer.
If it is determined that the selected port is sel [ n-2]]The output of the one-out-of-two multiplexer of (1) and the select port is sel [ n-3]]The output of the one-out-of-two multiplexer is 1 and the select port is sel n-4..1]The output of the one-out-of-two multiplexer of (2) is 0 and the select port is sel 0]The output of the one-out-of-two multiplexer of (2) is 0 and the select port is sel 1]The output of the alternative multiplexer of (a) is 0, and according to the arrangement sequence, the data input vector d (2) n-3 ) Then d (2 n-3 ) For the target input signal, the input to the second select port is sel [ n-2]]The data port of the alternative multiplexer of (a) is shown in fig. 4.
Taking the subtree of sel [ n-1] =0 as an example, the signals sel [0] to sel [ n-2] are turned over, and d and sel after data input rearrangement are mapped as shown in the following table.
It can be found that, for example, sel [ n-2]When 1 and the rest sel signals are 0, the corresponding data input vector is d (2 n -2 )。
From the predetermined signal mapping list and the above table, it can be seen that, for the sel signal of mux21 of the subtree sel [ n-1] =0, the order from the leaf node to the root node and the rule mapping from left to right in the above table, for example, the mux21 sel model of the subtree sel leaf node sel [ n-1] =0 should be "the leftmost column of sel [ n-2]" in the above table.
The d-terminal of mux21 of the leaf node of the subtree of sel n-1=0 should be in the order of "data input vector" in the table from top to bottom.
For further explanation, a specific embodiment is listed below.
Referring to fig. 5 to 6, a schematic diagram of a binary multiplexer without flipping according to an embodiment of the present invention and a schematic diagram of a binary multiplexer with flipping according to an embodiment of the present invention are shown, respectively.
Let n=4, the bit width of the select port. Totaling (2) 4 -1) one-out-of-two multiplexers (mux 21).
The fan-out (Fanout) of the sel [ n-1:0] signal has the following formula:
sel[0]：
fanout(sel[0])＝2 n-1-(0) ；
sel[1]：
fanout(sel[1])＝2 n-1-(1) ；
sel[2]：
fanout(sel[2])＝2 n-1-(2) ；
sel[n-1]：
fanout(sel[n-1])＝2 n-1-(n-1) ；
sel[n-1:0]：
fanout(sel[n-1：0])＝fanout(sel[0])+fanout(sel[1])+...+fanout(sel[n-1])；
＝2 n -1；
the original result of FIG. 5 computes a Fanout (Fanout) maximum of 8, i.e., the Fanout of sel [0], as calculated from the above equation.
Fig. 6 shows a circuit structure after the technical scheme of the present invention is applied, and the calculation is performed by adopting the above formula, which can be as follows:
sel[0]：
sel[1]：
sel[2]：
……
sel[n-2]：
sel[n-1]：
fanout(sel[n-1])＝1；
sel[n-1:0]：
fanout(sel[n-1：0]＝fanout(sel[0])+fanout(sel[1])+...+fanout(sel[n-1])；
＝2 n -1；
as can be obtained by the calculation of the formula, the maximum value of the fan-out of sel [0] is 5, and compared with the original structure, the reduced fan-out amount is 3, so that the fan-out amount can be greatly reduced.
It should be noted that if the fan-out (fanout) calculation formula of the optimized sel [ n-1:0] signal cannot be divided, the calculation formula may be rounded up (e.g., 5/2 cannot be divided up, resulting in a result of 2.5 and a result of 3.
The total fan-out of the binary multiplexer of the present invention is unchanged;
total fanout = model mux21 number = sel [ n-1:0] fanout;
the maximum fan-out of the binary multiplexer of the present invention is: fanout (sel [0 ])=fanout (sel [ n-2 ]);
and fanout (sel [0 ])=fanout (sel [ n-2 ]), fanout (sel [1 ])=fanout (sel [ n-3 ]), … ….
The maximum fanout reduction amplitude formula can be derived as follows:
can be calculated as the largest fanout in fig. 1.
max_fanou1(sel[n-1:0])＝fanout(sel[0])＝2 n-1 ；
Patent optimization backend max_fanou2 (sel [ n-1:0)])＝fanout(sel[0])＝2 n-2 +1；
Then
The case of more case maximum fan-out reduction is listed below.
Referring to fig. 7, an operation flowchart of a signal processing method of a binary multiplexer according to an embodiment of the present invention is shown.
Specifically, the signal processing method of the binary multiplexer may include the steps of:
in the first step, a unit width binary-mux is input.
Second, initializing mux21 tree information.
Third, one of the sub-trees of mux21 tree is selected.
Fourth, the selected mux21 tree subtree signal is obtained and flipped.
Fifth, the subtrees of the flipped sel signal are reordered for the data-side vector.
In this embodiment, the embodiment of the present invention provides a signal processing method of a binary multiplexer, which has the following beneficial effects: the invention can arbitrarily select one from a plurality of two-way multiplexers of the binary multiplexer as a target multiplexer; the subtree of any data port of the target multiplexer is turned over, and the corresponding target input signal is searched in the preset signal mapping list and is input into the turned multiplexer, so that the fan-out of the circuit can be reduced, no additional element is required, the circuit structure can be simplified, and the waste of wiring resources is avoided.
The embodiment of the invention also provides a signal processing device of the binary multiplexer, and referring to fig. 8, a schematic structural diagram of the signal processing device of the binary multiplexer is shown.
The apparatus is adapted to a binary multiplexer composed of a plurality of one-out-of-two multiplexers, wherein the signal processing apparatus of the binary multiplexer may include, as an example:
a selecting module 201 for arbitrarily selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer when an initial input signal of a unit width is input to the binary multiplexer;
the turning module 202 is configured to perform a turning process on a subtree of any one data port of the target multiplexer to obtain a turned multiplexer, where the subtree is formed by connecting a plurality of one-out-of-two multiplexers, and the turning process refers to turning the plurality of one-out-of-two multiplexers;
the signal processing module 203 is configured to search and input a corresponding target input signal in a preset signal mapping list according to a connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, where the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
Optionally, the flipping processing of the subtree of any one of the data ports of the target multiplexer obtains a flipped subtree, which includes:
selecting one port as a target port from two selected ports of the target multiplexer at will;
and turning over a plurality of one-out-of-two multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
Optionally, the searching and inputting the corresponding target input signal in the preset signal mapping list according to the connection sequence of the plurality of the two-out-of-one multiplexers of the flip multiplexer includes:
determining the connection sequence of a plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer;
and searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turnover multiplexer after forming a data input vector.
Optionally, the operation of constructing the preset signal mapping list includes:
acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer;
and determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
It will be clearly understood by those skilled in the art that, for convenience and brevity, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Further, an embodiment of the present application further provides an electronic device, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the signal processing method of the binary multiplexer as described in the above embodiments when executing the program.
Further, the embodiment of the present application also provides a computer-readable storage medium storing a computer-executable program for causing a computer to execute the signal processing method of the binary multiplexer according to the above embodiment.
It will be appreciated by those skilled in the art that embodiments of the present application may also provide a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), devices and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. A signal processing method of a binary multiplexer, the method being applied to a binary multiplexer composed of a plurality of one-out-of-two multiplexers, the method comprising:
when an initial input signal of a unit width is input to the binary multiplexer, arbitrarily selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer;
the method comprises the steps that a subtree of any one data port of a target multiplexer is turned to obtain a turned multiplexer, the subtree is formed by connecting a plurality of two-for-one multiplexers, and the turning treatment means turning the plurality of two-for-one multiplexers;
and searching and inputting a corresponding target input signal in a preset signal mapping list according to the connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, wherein the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
2. The signal processing method of the binary multiplexer according to claim 1, wherein the flipping process is performed on a sub-tree of any one of the data ports of the target multiplexer to obtain a flipped sub-tree, comprising:
selecting one port as a target port from two data ports of the target multiplexer at will;
and turning over a plurality of one-out-of-two multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
3. The signal processing method of a binary multiplexer according to claim 1, wherein the searching and inputting the corresponding target input signal in a preset signal mapping list according to the connection order of the plurality of one-out-of-two multiplexers of the flip multiplexer comprises:
determining the connection sequence of a plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer;
and searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turnover multiplexer after forming a data input vector.
4. A signal processing method of a binary multiplexer according to any one of claims 1 to 3, wherein the operation of constructing the preset signal mapping list comprises:
acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer;
and determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
5. A signal processing apparatus for a binary multiplexer, the apparatus being adapted for use in a binary multiplexer comprising a plurality of one-out-of-two multiplexers, the apparatus comprising:
a selection module for arbitrarily selecting a target multiplexer from a plurality of one-out-of-two multiplexers of the binary multiplexer when an initial input signal of a unit width is input to the binary multiplexer;
the overturning module is used for overturning a subtree of any one data port of the target multiplexer to obtain an overturning multiplexer, the subtree is formed by connecting a plurality of one-out-of-two multiplexers, and the overturning processing means overturning the plurality of one-out-of-two multiplexers;
and the signal processing module is used for searching and inputting a corresponding target input signal in a preset signal mapping list according to the connection sequence of a plurality of one-out-of-two multiplexers of the flip multiplexer, wherein the preset signal mapping list is a mapping relation table of a selection port and a data port of the one-out-of-two multiplexer when the binary multiplexer receives an initial input signal.
6. The signal processing device of claim 5, wherein the flipping process for the subtree of any one of the data ports of the target multiplexer is performed to obtain a flipped subtree, and the signal processing device comprises:
selecting one port as a target port from two selected ports of the target multiplexer at will;
and turning over a plurality of one-out-of-two multiplexers contained in the subtree corresponding to the target port left and right to obtain a turning-over multiplexer.
7. The signal processing device of the binary multiplexer according to claim 5, wherein the searching and inputting the corresponding target input signal in the preset signal mapping list according to the connection sequence of the plurality of the second multiplexers of the flip multiplexer comprises:
determining the connection sequence of a plurality of alternative multiplexers corresponding to each sub-tree of the flip multiplexer;
and searching corresponding target input signals in a preset signal mapping list based on the connection sequence, and inputting a plurality of target input signals into the turnover multiplexer after forming a data input vector.
8. The signal processing device of a binary multiplexer according to any one of claims 5 to 7, wherein the construction operation of the preset signal mapping list comprises:
acquiring a plurality of selection ports and a plurality of data ports of the binary multiplexer;
and determining the mapping relation between the plurality of selection ports and the plurality of data ports when the initial input signal is input, and obtaining a preset signal mapping list.
9. A binary multiplexer suitable for use in a signal processing method of a binary multiplexer according to any one of claims 1 to 4, wherein the binary multiplexer comprises: and the two-in-one multiplexers are provided with two data ports, one selection port and one output port.
10. A computer-readable storage medium storing a computer-executable program for causing a computer to execute the signal processing method of the binary multiplexer according to any one of claims 1 to 4.
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