CN117827702A - Memory access method and system, electronic device and computer readable storage medium - Google Patents
Memory access method and system, electronic device and computer readable storage medium Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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Abstract
The application discloses a memory access method and system, electronic equipment and a computer readable storage medium, wherein the memory access method comprises the following steps: monitoring real-time bandwidth data, delay data and jump probability of all address lines after detecting a service access command; determining a target address mapping mode according to the bandwidth data, the delay data and the jump probability; and operating the target address mapping mode to finish the access of the business access command to the memory. The method and the device improve the access efficiency of the memory.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a memory access method and system, an electronic device, and a computer readable storage medium.
Background
With the popularization of 5G networks, there is a higher requirement on the transmission bandwidth of the network, and the capability of processing burst data is also higher and higher. Due to chip size and cost considerations, an external memory is required to buffer the data packets during burst, i.e., burst data packets. However, due to the characteristics of the burst data packet, a certain uncertainty exists in the address change rule of the data packet of the read-write memory, and the access efficiency of the network burst data packet when accessing the memory cannot be improved.
Disclosure of Invention
The main objective of the present application is to provide a memory access method and system, an electronic device and a computer readable storage medium, which aim to solve the technical problem of how to improve the access efficiency of the memory.
In order to achieve the above object, the present application provides a memory access method, applied to a memory access system, including:
monitoring real-time bandwidth data, delay data and jump probability of all address lines after detecting a service access command;
determining a target address mapping mode according to the bandwidth data, the delay data and the jump probability;
and operating the target address mapping mode to finish the access of the business access command to the memory.
In some embodiments, the delay data includes read delay data and write delay data, and the step of determining a target address mapping pattern based on the bandwidth data, the delay data, and the transition probability includes:
determining a first weight corresponding to the bandwidth data, a second weight corresponding to the write delay data and a third weight corresponding to the read delay data;
calculating a first product between the first weight and the bandwidth data, a second product between the second weight and the write delay data, and a third product corresponding to the third weight and the read delay data, and taking the sum of the first product, the second product and the third product as a score corresponding to an address mapping mode;
And determining a target address mapping mode according to the score and the jump probability.
In some embodiments, the step of determining a target address mapping pattern based on the score and the transition probability comprises:
determining all address mapping modes corresponding to the jump probability;
and after the address mapping mode at the current moment is the last address mapping mode in the address mapping modes, determining the score corresponding to each address mapping mode, and selecting the address mapping mode with the highest score as a target address mapping mode.
In some embodiments, after the step of determining all address mapping modes corresponding to the transition probabilities, the method includes:
after the address mapping mode at the current moment is the other address mapping modes except the last address mapping mode in the address mapping modes, determining a first jump probability which is larger than a preset threshold value in the jump probabilities and a second jump probability which is smaller than or equal to the preset threshold value in the jump probabilities;
mapping the address corresponding to the second jump probability to a row in a memory, and mapping the bit corresponding to the first jump probability to a bank and a column of the memory to obtain the latest address mapping mode;
And running the latest address mapping mode, and executing the step of monitoring the real-time bandwidth data, delay data and jump probability of all address lines.
In some embodiments, the step of running the target address mapping mode includes:
determining a read command and a write command in the service access command;
and the blocking memory receives the write command, runs the target address mapping mode after the memory executes the read command, performs address mapping rule switching, and allows the memory to receive the write command after the address mapping rule switching is completed.
In addition, to achieve the above object, the present application provides a memory access system including:
the main control module is respectively connected with the target monitoring module and the address mapping module;
the target monitoring module is used for monitoring real-time bandwidth data, delay data and hopping probabilities of all address lines and sending the bandwidth data, the delay data and the hopping probabilities to the main control module;
the main control module is used for determining a target address mapping mode according to the received bandwidth data, the delay data and the jump probability, and sending the target address mapping mode to the address mapping module;
The address mapping module is used for executing the target address mapping mode, and completing the access of the received service access command to the memory according to the executed target address mapping mode.
In some embodiments, the target monitoring module includes:
the bandwidth monitoring module is used for calculating ideal bandwidth according to the monitoring time period and the working frequency of the memory, determining actual bandwidth according to the size and the number of the monitored burst data packets, calculating bandwidth utilization rate according to the actual bandwidth and the ideal bandwidth, and sending the bandwidth utilization rate as bandwidth data to the main control module.
In some embodiments, the target monitoring module includes:
the delay monitoring module is used for determining read delay data and write delay data in the monitoring time period, taking the ratio between preset standard delay data and the read delay data as read delay data, taking the ratio between the standard delay data and the write delay data as write delay data, and sending the read delay data and the write delay data as delay data to the main control module.
In some embodiments, the target monitoring module includes:
the jump monitoring module is used for determining the jump probability of all address lines in the monitoring time period, sequencing the jump probabilities and sending the sequenced jump probabilities to the main control module.
In some embodiments, the memory access system further comprises:
the configuration module is used for configuring a first weight corresponding to the bandwidth data, a second weight corresponding to the write delay data and a third weight corresponding to the read delay data, and sending the first weight, the second weight and the third weight to the main control module;
the master control module is further configured to calculate a score of each address mapping mode according to the first weight, the second weight, the third weight, the bandwidth data, the read delay data and the write delay data, and select an address mapping mode with the highest score as a target address mapping mode when determining that the address mapping mode at the current moment is the last address mapping mode according to the jump probability.
In addition, to achieve the above object, the present application further provides an electronic device, including: a processor; and a memory arranged to store computer executable instructions which, when executed, cause the processor to perform the steps of the memory access method as described above.
Further, to achieve the above object, the present application also provides a computer-readable storage medium storing one or more programs, which when executed by an electronic device comprising a plurality of application programs, cause the electronic device to perform the steps of the memory access method as described above.
According to the method and the device, after the service access command is detected, the jump probability of the bandwidth data, the delay data and the address line is directly monitored in real time, then the target address mapping mode is determined according to the jump probability of the bandwidth data, the delay data and the address line, and then the target address mapping mode is operated to finish the access of the service access command to the memory, so that the bank conflict in the memory can be avoided under the condition that the change rule of the address is not known, the access bandwidth of the memory is reduced, the phenomenon that the access efficiency of the memory is reduced is caused, and the target address mapping mode is searched for in the most motion according to the jump probability of the bandwidth data, the delay data and the address line, so that the page hit probability when the memory is accessed can be improved, the memory bandwidth is further improved, and the access efficiency of the memory is improved.
Drawings
FIG. 1 is a flow chart of a first embodiment of a memory access method of the present application;
FIG. 2 is a flow chart of a second embodiment of a memory access method according to the present application;
FIG. 3 is a system frame diagram of a third embodiment of a memory access system of the present application;
FIG. 4 is a system frame diagram of a fourth embodiment of a memory access system of the present application;
FIG. 5 is a flow chart of the memory operation in the memory access method of the present application.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| 10 | Memory access system | 100 | Main control module |
| 200 | Target monitoring module | 300 | Address mapping module |
| 400 | Configuration module | 500 | Data interface |
| 210 | Bandwidth monitoring module | 220 | Time delay monitoring module |
| 230 | Jump monitoring module |
The implementation, functional features and advantages of the present application will be further described with reference to the accompanying drawings in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is correspondingly changed.
In the present application, unless explicitly specified and limited otherwise, the terms "coupled," "secured," and the like are to be construed broadly, and for example, "secured" may be either permanently attached or removably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In addition, descriptions such as those related to "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in this application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
Referring to fig. 1, the present application provides a memory access method, which is applied to a memory access system in a first embodiment of the memory access method, including:
step S10, monitoring real-time bandwidth data, delay data and jump probability of all address lines after detecting a service access command;
because of certain uncertainty of the address change rule of the data packet of the read-write memory, the efficiency of accessing the memory by the network burst data packet cannot be improved. According to JEDEC protocol, if two adjacent commands access different row of the same bank, then the row corresponding to the current bank needs to be closed, then the row needing to be accessed later is opened, and the access bandwidth of the memory is greatly reduced due to the occurrence of the condition (bank conflict); in addition, when a command for accessing the memory frequently switches bank and row, memory access efficiency is reduced due to limitation of tFAW (timing parameter) timing. Therefore, in this embodiment, the memory access manner is optimized to improve the probability of Page Hit, and improve the access bandwidth of the memory, so as to improve the access efficiency of the memory.
In addition, in a scenario, the embodiment may be applied to a scenario where the external memory handles the burst data packet, so as to improve the efficiency of accessing the burst data packet to the memory in the network.
In this embodiment, the service access command may be an access command to a storage space according to a service requirement, and the service access command may be a read operation and a write operation to a specific storage area in the memory. And the service access command may include a read command and a write command, or a read command.
In this embodiment, when the memory access system is initialized by power-up, the evaluation weight information of the bandwidth data and the delay data is written into the main control module in the memory access system through the configuration interface. The memory access system comprises a main control module, a configuration module, an address mapping module, a bandwidth monitoring module, a delay monitoring module and a jump monitoring module. And then, starting the service of the Ethernet data packet entering the memory, namely, the memory can receive the service access command sent by the processor, monitor the bandwidth data, delay data and jump probability of all address lines corresponding to the service access command in real time through the bandwidth monitoring module, the delay monitoring module and the jump monitoring module, and then send the bandwidth data, the delay data and the jump probability of all address lines to the main control module for corresponding control. The bandwidth data comprises an ideal bandwidth, an actual bandwidth and a utilization ratio calculated according to the actual bandwidth and the ideal bandwidth. The delay data includes read delay data and write delay data. The read latency data may be latency data when a read command is executed. The write latency data may be latency data when executing a write command. The transition probability may be a flip probability of the address line being flipped. And the address lines in this embodiment may be provided in plural, such as 16 address lines, 20 address lines. The memory is provided with a plurality of storage intervals, and each storage interval is provided with a corresponding address. Wherein the memory may be a double rate memory.
Step S20, determining a target address mapping mode according to the bandwidth data, the delay data and the jump probability;
the main control module in the memory access system calculates the score corresponding to each address mapping mode according to the bandwidth data, the delay data, the adjustment probability and the corresponding weight set in advance, selects the address mapping scheme with the highest score from the scores, and takes the address mapping scheme with the highest score as the target address mapping scheme. Wherein the address mapping scheme includes an address mapping mode. The address mapping pattern in the highest scoring address mapping scheme may be referred to as the target address mapping pattern.
In addition, because the lengths of the access addresses or the order in which the service access commands are issued may be different in different service access commands, if all the service access commands adopt the same address mapping mode, a large number of bank conflicts may occur, and the access efficiency of the memory is seriously affected. Therefore, in this embodiment, the adaptive manner is adopted to improve the Page Hit probability by using different address mapping modes, so as to further improve the access efficiency of the memory. The address mapping mode may be set according to the transition probabilities of all address lines. And the address mapping pattern may be a mapping rule or policy that maps access addresses to memory.
And step S30, the target address mapping mode is operated to finish the access of the business access command to the memory.
After the target address mapping mode is determined by the main control module in the memory access system, the target address mapping mode can be directly executed by the address mapping module so as to complete the access of the business access command to the memory.
In one scenario, the memory access system is powered on and initialized, bandwidth and delayed evaluation weight information is written into the main control module through the configuration interface, the service of the Ethernet data packet entering the memory is started, and bandwidth data, delay data and hopping probability of all address lines corresponding to the service access command are monitored in real time through the bandwidth monitoring module, the delay monitoring module and the hopping monitoring module and sent to the main control module. And the main control module calculates the score under the default address mapping mode according to the bandwidth data, the delay data and the weights corresponding to the bandwidth data and the delay data. And when the default address mapping mode is not the last address mapping mode, setting a new address mapping mode according to the jump probability, namely mapping the address with low jump probability to row, and mapping the bit with low jump probability to column, bank and bank group positions. And then the new address mapping mode is sent to the address mapping module. After receiving the new address mapping mode, the address mapping module blocks the memory to receive the write command, and after executing all the read commands in the memory, the address mapping module switches the address mapping rule according to the new address mapping mode, and after switching, stops blocking the memory to receive the write command, and opens the write command channel, so that the Ethernet data packet can enter the memory again.
Further, to assist understanding of the memory access principle in the present embodiment, the following is exemplified.
For example, as shown in fig. 5, after memory access is started, the configuration module configures the weights of bandwidth and delay data, then starts an ethernet packet into the memory service, and then monitors the bandwidth data, delay data and jump probability corresponding to the memory service. And sending the bandwidth data, the delay data and the jump probability to a main control module, detecting whether the current address mapping mode is the last address mapping mode according to the bandwidth data, the delay data and the jump probability by the main control module, if not, calculating a score corresponding to the address mapping mode operated at the current moment by the main control module according to the bandwidth data, the delay data and weight information corresponding to the bandwidth data and the delay data, generating a new address mapping mode according to the jump probability, and sending the new address mapping mode to the address mapping module for execution. The memory will again monitor bandwidth data, delay data and transition probabilities as new address mapping modes are run. However, if the current address mapping mode is the last address mapping mode, selecting the address mapping mode with the highest score from the scores corresponding to the address mapping modes as the optimal address mapping mode (i.e. the target address mapping mode), and outputting the optimal address mapping mode to the address mapping module for execution until the execution is finished.
In this embodiment, after a service access command is detected, the jump probabilities of bandwidth data, delay data and address lines are directly monitored in real time, then a target address mapping mode is determined according to the jump probabilities of the bandwidth data, delay data and address lines, and then the target address mapping mode is operated to complete the access of the service access command to the memory, so that bank conflicts in the memory can be avoided under the condition that the change rule of the address is not known, the access bandwidth of the memory is reduced, the phenomenon that the access efficiency of the memory is reduced occurs, and the target address mapping mode is searched for in a most movable mode according to the jump probabilities of the bandwidth data, the delay data and the address lines, so that the page hit probability when the memory is accessed can be improved, the memory bandwidth is further improved, and the access efficiency of the memory is improved.
Further, based on the first embodiment of the present invention, a second embodiment of the memory access method of the present application is proposed, referring to fig. 2, in this embodiment, step S20 of the embodiment, the step of determining the target address mapping mode according to the bandwidth data, the delay data and the transition probability is refined, which includes:
Step a, determining a first weight corresponding to the bandwidth data, a second weight corresponding to the write delay data and a third weight corresponding to the read delay data;
in the present embodiment, the delay data includes read delay data and write delay data. Therefore, the first weight corresponding to the bandwidth data, the second weight corresponding to the write delay data and the third weight corresponding to the read delay data can be set in advance through a configuration module in the memory access system. And the sum of the first weight, the second weight, and the third weight is 100%. In this embodiment, the user may adjust the first weight, the second weight, and the third weight according to his own needs.
Step b, calculating a first product between the first weight and the bandwidth data, a second product between the second weight and the write delay data, and a third product corresponding to the third weight and the read delay data, and taking the sum of the first product, the second product and the third product as a score corresponding to an address mapping mode;
and c, determining a target address mapping mode according to the score and the jump probability.
When the first weight, the second weight and the third weight are determined, and bandwidth data, write delay data and read delay data are collected, the score corresponding to the address mapping mode of the memory running at the current moment can be calculated. For example, if the first weight is m, the second weight is n, the third weight o, the bandwidth data u, the write latency data is v, and the read latency data is w, the score result corresponding to the address mapping mode may be: result=m×u+n×v+o×w.
In this embodiment, in a certain period of time, the score corresponding to each address mapping mode generated by the access of the service access command to the memory can be calculated according to the above formula.
In this embodiment, all possible address mapping modes may be determined according to the hopping probability, and the highest score among the scores corresponding to the address mapping modes is determined, where the address mapping mode corresponding to the highest score is used as the target address mapping mode.
In this embodiment, corresponding weights are set for the bandwidth data, the write delay data and the read delay data respectively, then scores corresponding to the address mapping modes are calculated based on the set weights, the bandwidth data, the write delay data and the read delay data, and then the target address mapping modes are determined according to the scores and the jump probabilities, so that accuracy and effectiveness of the obtained target address mapping modes are guaranteed.
Further, the step of determining a target address mapping mode according to the score and the jump probability comprises the following steps:
step d, determining all address mapping modes corresponding to the jump probability;
and e, after the address mapping mode at the current moment is the last address mapping mode in the address mapping modes, determining the score corresponding to each address mapping mode, and selecting the address mapping mode with the highest score as a target address mapping mode.
In this embodiment, all address mapping patterns that determine possible existence need to be constructed according to the transition probability of each address line. After determining all the address mapping modes, determining whether the address mapping mode of the memory at the current moment is the last address mapping mode in all the address mapping modes, and after determining that the address mapping mode at the current moment is the last address mapping mode, selecting the address mapping mode with the highest score as the target address mapping mode according to the scores corresponding to all the address mapping modes.
In this embodiment, by determining all address mapping modes corresponding to the jump probability, and selecting the address mapping mode with the highest score as the target address mapping mode when determining that the address mapping mode at the current moment is the last address mapping mode, the accuracy and the effectiveness of the obtained target address mapping mode are ensured.
Further, after the step of determining all address mapping modes corresponding to the hopping probabilities, the method includes:
step f, after the address mapping mode at the current moment is the other address mapping modes except the last address mapping mode in the address mapping modes, determining a first jump probability which is larger than a preset threshold value in the jump probabilities and a second jump probability which is smaller than or equal to the preset threshold value in the jump probabilities;
Step g, mapping the address corresponding to the second jump probability to a row in a memory, and mapping the bit corresponding to the first jump probability to a bank and a column in the memory to obtain the latest address mapping mode;
and h, operating the latest address mapping mode, and executing the step of monitoring the real-time bandwidth data, delay data and jump probability of all address lines.
In this embodiment, when it is determined that the address mapping pattern at the current time is not the last address mapping pattern but other address mapping patterns, a new address mapping pattern can be constructed according to the hopping probability. Wherein the other address mapping pattern is an address mapping pattern other than the last address mapping pattern, such as the penultimate address mapping pattern.
When the latest address mapping mode is constructed, a probability threshold of the hopping probability can be set first and used as a preset threshold, the hopping probability of the hopping probability corresponding to each address line, which is larger than the preset threshold, is used as a first hopping probability, and the hopping probability which is smaller than or equal to the preset threshold is used as a second hopping probability. And then mapping the address corresponding to the second jump probability to a row (row) in the memory, and mapping the bit corresponding to the first jump probability to a bank and a column in the memory to obtain the latest address mapping mode. And then running the latest address mapping mode through an address mapping module in the memory access system, and then monitoring bandwidth data, delay data and jump probability of the memory when running the latest address mapping mode, so as to calculate the score corresponding to the latest address mapping mode.
In this embodiment, when the address mapping mode at the current time is not the last address mapping mode, the latest address mapping mode is constructed according to the jump probability, and then the operation and monitoring are performed to calculate the score corresponding to the latest address mapping mode until the target address mapping mode is selected. Thereby ensuring the accuracy and the effectiveness of the target address mapping mode selected subsequently.
Further, the step of running the target address mapping mode includes:
step x, determining a read command and a write command in the service access command;
and step y, the blocking memory receives the write command, runs the target address mapping mode after the memory executes the read command, performs address mapping rule switching, and allows the memory to receive the write command after the address mapping rule switching is completed.
In this embodiment, after receiving a new address mapping scheme, the address mapping module in the memory access system blocks the memory from receiving a write command in a service access command, and performs address mapping rule switching after all read commands in the service access command are executed. After the switching is completed, the write command channel is opened to enable the memory to receive the write command, so that the purpose that the Ethernet data packet can enter the memory again is achieved.
In this embodiment, the memory is blocked to receive the write command in the service access command, and after all the read commands in the service access command are executed, the address mapping rule is switched according to the target address mapping mode, and then the read commands are executed, so that the effective access of the service access command to the memory is ensured, and the access efficiency is improved.
In addition, in a scenario, the present application further proposes a memory access system, and in a third embodiment of the memory access system of the present application, referring to fig. 3, the memory access system 10 includes a main control module 100, a target monitoring module 200 and an address mapping module 300 respectively connected to the main control module;
the target monitoring module 200 is configured to monitor real-time bandwidth data, delay data, and transition probabilities of all address lines, and send the bandwidth data, the delay data, and the transition probabilities to the main control module 100;
the main control module 100 is configured to determine a target address mapping mode according to the received bandwidth data, the delay data, and the hopping probability, and send the target address mapping mode to the address mapping module 300;
the address mapping module 300 is configured to execute the target address mapping mode, and complete access of the received service access command to the memory according to the executed target address mapping mode.
In one scenario in this embodiment, the memory access system may be the memory access system in the first embodiment and the second embodiment.
In the present embodiment, the memory access system 10 may further be provided with a data interface 500, and the data interface 500 is connected to the target monitoring module 200 and the address mapping module 300, respectively. And after initiating the traffic of the ethernet packet into the memory, the target monitoring module 200 monitors the operation of the memory through the data interface 500. The target monitoring module 200 may acquire monitored bandwidth data, delay data and transition probabilities of all address lines through the data interface 500, and then send the monitored bandwidth data, delay data and transition probabilities to the main control module 100. In this embodiment, the transition probabilities of all address lines need to be acquired.
In addition, the main control module 100 determines whether the default address mapping mode at the current time in the memory is the last address mapping mode. And when it is determined that the address mapping mode is the last address mapping mode, one address mapping mode with the highest score is selected from all address mapping modes as the target address mapping mode, and is sent to the address mapping module 300 to be executed. However, if the default address mapping mode at the current time is not the last address mapping mode, a new address mapping mode is set according to the jump probability, and is executed through the address mapping module 300, the new address mapping mode is monitored through the target monitoring module 200, the score corresponding to the new address mapping mode is calculated through the main control module 100 until the memory runs the last address mapping mode, the score corresponding to the last address mapping mode is calculated by the main control module 100, and then one address mapping mode with the highest score is selected from all scores as the target address mapping mode.
Each time the service access command accesses the memory, a plurality of addresses are generated according to the message length corresponding to the service access command, and a plurality of address mapping modes can be set according to different mapping rules. And when the memory is accessed by the service access command, the ethernet packet will also enter the memory's service.
And when the address mapping mode is set, the setting can be performed according to the jump probability monitored in real time. At this time, in addition to setting according to the hopping probability, in a scenario, address mapping may be performed according to a preset address mapping rule.
In this embodiment, a main control module, a target monitoring module and an address mapping module are set in a memory access system, and the target monitoring module sends monitored bandwidth data, delay data and jump probability to the main control module, so that the main control module determines a target address mapping mode and executes the target address mapping mode, and accesses to a memory are sequentially completed, so that bank conflicts in the memory can be avoided under the condition that an address change rule is not known, the access bandwidth of the memory is reduced, the phenomenon that the access efficiency of the memory is reduced occurs, and the target address mapping mode is searched for in a most movable mode according to the bandwidth data, the delay data and the jump probability of an address line, so that the page hit probability when the memory is accessed can be improved, the memory bandwidth is further improved, and the access efficiency of the memory is improved.
Further, based on the above-mentioned third embodiment of the present application, a fourth embodiment of the memory access system of the present application is proposed, and referring to fig. 4, the target monitoring module 200 includes:
the bandwidth monitoring module 210 is configured to calculate an ideal bandwidth according to a monitoring time period and a memory operating frequency, determine an actual bandwidth according to a monitored size and number of burst data packets, calculate a bandwidth utilization according to the actual bandwidth and the ideal bandwidth, and send the bandwidth utilization as bandwidth data to the main control module 100.
In this embodiment, the bandwidth monitoring module 210 may monitor the bandwidth data of the memory, and the bandwidth monitoring module 210 is respectively connected to the data interface 500 and the main control module 100, and the bandwidth monitoring module 210 monitors the actual bandwidth through the data interface 500. In one scenario, the bandwidth monitoring module 210 may monitor the data bandwidth in different monitoring periods, and take the data bandwidth as the actual bandwidth, and determine the actual bandwidth by calculating the size and number of read/write bursts. And calculating an ideal bandwidth according to the monitoring time and the working frequency of the memory, wherein the ideal bandwidth can be obtained by multiplying the speed of the single address line and the bit width of the single address line. Then dividing the actual bandwidth by the ideal bandwidth to obtain the bandwidth utilization, and sending the bandwidth utilization as bandwidth data to the main control module 100.
In this embodiment, by setting the bandwidth monitoring module 210 in the target monitoring module 200, bandwidth data is acquired by the bandwidth monitoring module 210, so that the validity of the acquired bandwidth data is ensured.
Further, the target monitoring module 200 further includes:
the delay monitoring module 220 is configured to determine read delay data and write delay data in the monitoring period, take a ratio between preset standard delay data and the read delay data as read delay data, take a ratio between the standard delay data and the write delay data as write delay data, and send the read delay data and the write delay data as delay data to the main control module 100.
In this embodiment, the delay data of the memory can be monitored by the delay monitor module 220, and since the service access memory generally includes both read and write operations. The delay data in this embodiment may include delay data of a read operation and delay data of a write operation. Such as read latency data and write latency data.
And the delay monitoring module 220 is respectively connected with the data interface 500 and the main control module 100, and the delay monitoring module 220 monitors delay data through the data interface 500. In one scenario, the delay monitor module 220 needs to acquire the standard delay time set in advance, then acquire the read delay data and the write delay data in the monitor period, calculate the ratio between the standard delay data and the read delay data, use the ratio as the read delay data, and similarly calculate the ratio between the standard delay data and the write delay data, and use the ratio as the write delay data. The read latency data and the write latency data are then transmitted to the main control module 100 as latency data. And the order of sending the read latency data and the write latency data is not limited in this embodiment.
In this embodiment, by setting the delay monitoring module 220 in the target monitoring module 200, the read delay data and the write delay data are obtained by the delay monitoring module 220, the read delay data and the write delay data are determined according to the standard delay data, and then the read delay data and the write delay data are used as the delay data, thereby ensuring the accuracy of the obtained delay data.
Further, the target monitoring module 200 further includes:
the transition monitoring module 230 is configured to determine transition probabilities of all address lines in the monitoring period, sort the transition probabilities, and send the sorted transition probabilities to the master control module 100.
In this embodiment, the jump monitoring module 230 may monitor the jump probabilities of all address lines in the memory, determine the jump probabilities of all address lines in the monitoring period, and then order the address lines, where the ordering rule may be to order the address lines from big to small. Finally, all the sequenced hopping probabilities are sent to the main control module 100.
The jump monitoring module 200 is connected with the data interface 500 and the main control module 100 respectively, and monitors and acquires the jump probability through the data interface 500. The monitoring period may be a period of system default settings.
In this embodiment, the jump monitoring module 230 is set in the target monitoring module 200, and the jump probabilities of all address lines are monitored by the jump monitoring module 230 and sent to the main control module 100, so that the accuracy and the effectiveness of the jump probabilities obtained by the main control module 100 are ensured.
Further, the memory access system 10 further includes:
a configuration module 400, configured to configure a first weight corresponding to the bandwidth data, a second weight corresponding to the write latency data, and a third weight corresponding to the read latency data, and send the first weight, the second weight, and the third weight to the master control module 100;
the master control module 100 is further configured to calculate a score of each address mapping mode according to the first weight, the second weight, the third weight, the bandwidth data, the read delay data, and the write delay data, and select, when determining that the address mapping mode at the current time is the last address mapping mode according to the jump probability, the address mapping mode with the highest score as the target address mapping mode.
In this embodiment, when other modules in the memory do not start to work, the configuration module 400 may be started first, and each parameter, such as a first weight of the configuration bandwidth data, a second weight corresponding to the write delay data, and a third weight corresponding to the read delay data, may be set by the configuration module 400, and sent to the main control module 100. Wherein the sum of the first weight, the second weight and the third weight is 100%.
The main control module receives each configuration data, such as a first weight, a second weight and a third weight, sent by the configuration module 400; the bandwidth utilization rate sent by the bandwidth monitoring module 210 is received; the read delay proportion and the write delay proportion sent by the delay monitoring module 220 are received; after receiving the hopping probability sent by the hopping monitor module 200, the score of each address mapping mode can be calculated, and when the address mapping mode at the current moment is the last address mapping mode, the address mapping mode with the highest score is selected from the scores as the target address mapping mode. It should be noted that, when the memory runs in different address mapping modes, the bandwidth data, delay data and hopping probability acquired by the target monitoring module 200 may be the same or different, which is not limited herein.
In this embodiment, the configuration module is set in the memory access system, and the configuration module sets weights for the bandwidth data, the write delay data and the read delay data in the main control module, so that the main control module can determine the target address mapping mode more accurately.
In addition, the invention also provides electronic equipment, which comprises: a memory, a processor, and a memory access program stored on the memory; the processor is configured to execute the memory access program to implement the steps of the embodiments of the memory access method described above.
The present invention also provides a computer-readable storage medium storing one or more programs executable by one or more processors for implementing the steps of the above-described memory access method embodiments.
The specific implementation of the computer readable storage medium of the present invention is substantially the same as the above embodiments of the memory access method, and will not be described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (12)
1. A memory access method, applied to a memory access system, comprising:
Monitoring real-time bandwidth data, delay data and jump probability of all address lines after detecting a service access command;
determining a target address mapping mode according to the bandwidth data, the delay data and the jump probability;
and operating the target address mapping mode to finish the access of the business access command to the memory.
2. The memory access method of claim 1, wherein the delay data comprises read delay data and write delay data, and wherein the determining the target address mapping pattern based on the bandwidth data, the delay data, and the transition probability comprises:
determining a first weight corresponding to the bandwidth data, a second weight corresponding to the write delay data and a third weight corresponding to the read delay data;
calculating a first product between the first weight and the bandwidth data, a second product between the second weight and the write delay data, and a third product corresponding to the third weight and the read delay data, and taking the sum of the first product, the second product and the third product as a score corresponding to an address mapping mode;
And determining a target address mapping mode according to the score and the jump probability.
3. The memory access method of claim 2, wherein the step of determining a target address mapping pattern based on the score and the transition probability comprises:
determining all address mapping modes corresponding to the jump probability;
and after the address mapping mode at the current moment is the last address mapping mode in the address mapping modes, determining the score corresponding to each address mapping mode, and selecting the address mapping mode with the highest score as a target address mapping mode.
4. The memory access method of claim 2, wherein after the step of determining all address mapping patterns corresponding to the transition probabilities, comprising:
after the address mapping mode at the current moment is the other address mapping modes except the last address mapping mode in the address mapping modes, determining a first jump probability which is larger than a preset threshold value in the jump probabilities and a second jump probability which is smaller than or equal to the preset threshold value in the jump probabilities;
mapping the address corresponding to the second jump probability to a row in a memory, and mapping the bit corresponding to the first jump probability to a bank and a column of the memory to obtain the latest address mapping mode;
And running the latest address mapping mode, and executing the step of monitoring the real-time bandwidth data, delay data and jump probability of all address lines.
5. The memory access method of claim 1, wherein the step of running the target address mapping mode comprises:
determining a read command and a write command in the service access command;
and the blocking memory receives the write command, runs the target address mapping mode after the memory executes the read command, performs address mapping rule switching, and allows the memory to receive the write command after the address mapping rule switching is completed.
6. A memory access system, comprising: the main control module is respectively connected with the target monitoring module and the address mapping module;
the target monitoring module is used for monitoring real-time bandwidth data, delay data and hopping probabilities of all address lines and sending the bandwidth data, the delay data and the hopping probabilities to the main control module;
the main control module is used for determining a target address mapping mode according to the received bandwidth data, the delay data and the jump probability, and sending the target address mapping mode to the address mapping module;
The address mapping module is used for executing the target address mapping mode, and completing the access of the received service access command to the memory according to the executed target address mapping mode.
7. The memory access system of claim 6, wherein the target monitoring module comprises:
the bandwidth monitoring module is used for calculating ideal bandwidth according to the monitoring time period and the working frequency of the memory, determining actual bandwidth according to the size and the number of the monitored burst data packets, calculating bandwidth utilization rate according to the actual bandwidth and the ideal bandwidth, and sending the bandwidth utilization rate as bandwidth data to the main control module.
8. The memory access system of claim 7, wherein the target monitoring module comprises:
the delay monitoring module is used for determining read delay data and write delay data in the monitoring time period, taking the ratio between preset standard delay data and the read delay data as read delay data, taking the ratio between the standard delay data and the write delay data as write delay data, and sending the read delay data and the write delay data as delay data to the main control module.
9. The memory access system of claim 8, wherein the target monitoring module comprises:
the jump monitoring module is used for determining the jump probability of all address lines in the monitoring time period, sequencing the jump probabilities and sending the sequenced jump probabilities to the main control module.
10. The memory access system of claim 9, further comprising:
the configuration module is used for configuring a first weight corresponding to the bandwidth data, a second weight corresponding to the write delay data and a third weight corresponding to the read delay data, and sending the first weight, the second weight and the third weight to the main control module;
the master control module is further configured to calculate a score of each address mapping mode according to the first weight, the second weight, the third weight, the bandwidth data, the read delay data and the write delay data, and select an address mapping mode with the highest score as a target address mapping mode when determining that the address mapping mode at the current moment is the last address mapping mode according to the jump probability.
11. An electronic device, comprising: a processor; and a memory arranged to store computer executable instructions which, when executed, cause the processor to perform the steps of the memory access method of any of claims 1-5.
12. A computer readable storage medium storing one or more programs, which when executed by an electronic device comprising a plurality of application programs, cause the electronic device to perform the steps of the memory access method of any of claims 1-5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211196077.1A CN117827702A (en) | 2022-09-28 | 2022-09-28 | Memory access method and system, electronic device and computer readable storage medium |
| PCT/CN2023/084365 WO2024066256A1 (en) | 2022-09-28 | 2023-03-28 | Memory access method and system, electronic device, and computer-readable storage medium |
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| CN202211196077.1A CN117827702A (en) | 2022-09-28 | 2022-09-28 | Memory access method and system, electronic device and computer readable storage medium |
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| CN108959105B (en) * | 2017-05-17 | 2023-12-22 | 深圳市中兴微电子技术有限公司 | Method and device for realizing address mapping |
| CN111858396B (en) * | 2020-07-27 | 2023-07-28 | 福州大学 | Memory self-adaptive address mapping method and system |
| CN114816263A (en) * | 2020-09-18 | 2022-07-29 | 星宸科技股份有限公司 | Storage access method and intelligent processing device |
| CN112463700B (en) * | 2020-11-06 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Method and device for controlling AXI bus bandwidth |
| CN113590508B (en) * | 2021-09-30 | 2022-02-11 | 沐曦科技(北京)有限公司 | Dynamic reconfigurable memory address mapping method and device |
| US20220179797A1 (en) * | 2022-02-28 | 2022-06-09 | Intel Corporation | Memory transaction queue bypass based on configurable address and bandwidth conditions |
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