CN117812853A - Preparation method of multilayer circuit board and multilayer circuit board - Google Patents

Abstract

The application provides a multilayer circuit board and a preparation method thereof. The preparation method comprises the following steps: providing a circuit board, wherein the circuit board comprises at least two non-bending areas and a bending area positioned between the two non-bending areas, each non-bending area is provided with a circuit layer, and the circuit layer comprises a connecting pad; attaching a dielectric layer on the circuit board, and forming a plurality of blind holes on the dielectric layer to expose a plurality of connecting pads; filling conductive paste into each blind hole to obtain a first conductive paste block electrically connected with the connecting pad; and after bending the bending areas, pressing the bending areas, so that the first conductive paste blocks positioned on the same side in the two adjacent non-bending areas are combined, and the dielectric layers positioned on the same side are combined to obtain the multilayer circuit board. The preparation method of the multilayer circuit board provided by the application can be used for preparing the interconnection structure with high aspect ratio (thickness-to-diameter ratio), and has the advantages of shorter flow and simple process.

Description

Preparation method of multilayer circuit board and multilayer circuit board

Technical Field

The present disclosure relates to the field of circuit board manufacturing, and in particular, to a method for manufacturing a multilayer circuit board and a multilayer circuit board manufactured by the same.

Background

The multilayer circuit board includes a plurality of wiring layers and a plurality of substrate layers alternately stacked, and any wiring layers are electrically connected by an interconnection structure penetrating the substrate layers. The interconnect structure is typically formed by: and drilling a through hole on the substrate layer, and electroplating the through hole to form the interconnection structure. When the substrate layer is thick, limited to electroplating capability, interconnect structures with high aspect ratios (thickness to diameter ratios) are generally made in two ways. Firstly, electroplating a bump on the surface of a connecting pad, pressing a substrate layer with a larger thickness on the bump to form a blind hole exposing the bump, electroplating the blind hole to form a conductive hole, and forming an interconnection structure by the conductive hole and the bump together. In the second mode, the upper surface of the substrate layer with the larger thickness is drilled to form blind holes, then the lower surface of the substrate layer is drilled to form grooves, the blind holes are communicated with the grooves to form X-shaped through holes, and then the X-shaped through holes are electroplated to form an interconnection structure. However, in the first mode, multiple electroplating is needed, and the manufacturing flow is long; in the second mode, the double-sided blind hole drilling is high in alignment precision, and the complexity of the process is increased.

Disclosure of Invention

In view of this, the present application provides a method for preparing a multilayer circuit board with a short manufacturing process and a simple process, and the multilayer circuit board prepared by the method.

The first aspect of the present application provides a method for manufacturing a multilayer circuit board, including the steps of:

providing a circuit board, wherein the circuit board comprises at least two non-bending areas and a bending area positioned between the two non-bending areas, each non-bending area is provided with a circuit layer, and the circuit layer comprises a connecting pad;

attaching a dielectric layer on the circuit board, and forming a plurality of blind holes on the dielectric layer to expose a plurality of connecting pads;

filling conductive paste into each blind hole to obtain a first conductive paste block electrically connected with the connecting pad;

and after bending the bending areas, pressing the bending areas, so that the first conductive paste blocks positioned on the same side in the two adjacent non-bending areas are combined, and the dielectric layers positioned on the same side are combined to obtain the multilayer circuit board.

A second aspect of the present application provides a multilayer circuit board comprising a multilayer circuit board, each layer of circuit board comprising a circuit layer having a connection pad. Two layers of dielectric layers are clamped between every two adjacent layers of circuit boards, the connecting pads on every two adjacent layers of circuit boards are connected through an interconnection structure penetrating through the two layers of dielectric layers, the interconnection structure comprises two first conductive paste blocks connected with the connecting pads on the two layers of circuit boards and a second conductive paste block clamped between the two first conductive paste blocks, and the joint surface between the two layers of dielectric layers and the joint surface between the first conductive paste block and the second conductive paste block are not on the same plane.

According to the circuit board, the plurality of first conductive paste blocks are arranged on the circuit board, after the circuit board is bent, the two first conductive paste blocks are combined to form the interconnection structure with the high aspect ratio (thickness-diameter ratio), electroplating is not needed in the forming process of the interconnection structure, the process is shortened, double-sided drilling is not needed, the alignment difficulty is reduced, and the process technology is simplified.

Drawings

Fig. 1 is a schematic cross-sectional view of a copper-clad plate according to an embodiment of the present application.

Fig. 2 is a schematic cross-sectional view of the copper-clad plate shown in fig. 1 after forming conductive holes therein.

Fig. 3 is a schematic cross-sectional view of a circuit board according to an embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional view of the circuit board shown in fig. 3 after a dielectric layer is attached and blind holes are formed.

Fig. 5 is a schematic cross-sectional view of the dielectric layer of fig. 4 after forming a trench therein.

Fig. 6 is a schematic cross-sectional view of the blind via of fig. 5 after forming a first conductive paste.

Fig. 7 is a schematic cross-sectional view of the second conductive paste after forming the partial blind via shown in fig. 6.

Fig. 8 is a schematic cross-sectional view of the circuit board shown in fig. 7 after bending and pressing.

Fig. 9 is a schematic cross-sectional view of the multi-layer circuit board shown in fig. 8 with the bending region removed.

Description of the main reference signs

Circuit board 10

Substrate layer 11

Line layer 12

Conductive hole 13

Bending region 110

Non-inflection region 120

Copper-clad plate 101

Copper foil layer 102

Connection pad 121

Dielectric layer 20

First surface 201

Blind hole 21

Grooving 22

First conductive paste 31

Second surface 310

Second conductive paste 32

Third surface 320

Dry film 60

The following detailed description will further illustrate embodiments of the present application in conjunction with the above-described figures.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the present application belong. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the examples of the application.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear) in the embodiments of the present application are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are correspondingly changed.

In addition, descriptions such as those related to "first," "second," and the like in this application are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.

Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate configurations) of the present application. Thus, differences in the shapes of the illustrations as a result, of manufacturing processes and/or tolerances, are to be expected. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are merely schematic in nature and their shapes are not intended to illustrate the actual shape of a device and are not intended to limit the scope of the present application.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without collision.

Referring to fig. 1 to 9, an embodiment of the present application provides a method for manufacturing a multi-layer circuit board 100, which includes the following steps.

In step S10, referring to fig. 3, a circuit board 10 is provided.

Along the thickness direction (vertical direction in the drawing) of the wiring board 10, the wiring board 10 includes a base material layer 11 and a wiring layer 12 provided on the base material layer 11. The circuit layer 12 may be disposed on one surface or two opposite surfaces of the substrate layer 11. In this embodiment, the circuit layer 12 is disposed on two opposite surfaces of the base material layer 11 and is electrically connected through the conductive via 13 penetrating the base material layer 11.

Along the extending direction (horizontal direction in the drawing) of the circuit board 10, the circuit board 10 includes a bending region 110 and at least two non-bending regions 120. The bending region 110 is used for bending the circuit board 10 in a subsequent step, and the non-bending region 120 is laminated to form a multi-layer structure. The bending region 110 is located between two adjacent non-bending regions 120, and the number of the bending regions 110 and the non-bending regions 120 can be set according to actual needs. The extending direction of the circuit board 10 may be a width direction or a length direction of the circuit board and is perpendicular to the thickness direction of the circuit board 10. In this embodiment, the number of inflection zones 110 is 2, and the number of non-inflection zones 120 is 3. In the present embodiment, the circuit pattern of the circuit layer 12 is only disposed in the non-bending region 120, and the non-bending region 120 is only composed of the substrate layer 11. In other embodiments, the trace pattern of the trace layer 12 may also be disposed in the inflection region 110.

In this embodiment, the material of the base material layer 11 is a flexible resin layer, that is, the circuit board 10 is a flexible circuit board. The flexible resin layer includes at least one of Polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polythylene Naphthalate, PEN).

In other embodiments, the substrate layer 11 may be formed by combining a plurality of regions with different hardness, for example, the substrate layer 11 in the bending region 110 is made of a flexible resin layer, and the substrate layer 11 in the non-bending region 120 is made of a rigid insulating material, for example, a prepreg comprising glass fiber and epoxy resin. That is, the wiring board 10 is a rigid-flex wiring board.

Step S10 specifically includes the following steps S11-S13.

As shown in fig. 1, in step S11, a copper-clad laminate 101 is provided, which includes a substrate layer 11 and copper foil layers 102 disposed on opposite surfaces of the substrate layer 11. In other embodiments, the copper foil layer 102 may be disposed on only one surface of the substrate layer 11.

In some embodiments, the copper-clad plate 101 is formed by: a seed layer is formed on the surface of the base material layer 11 by adhesion, deposition, or the like, and then a copper plating layer is formed on the seed layer by electroplating, the seed layer and the copper plating layer constituting the copper foil layer 102.

As shown in fig. 2, in step S12, conductive holes 13 are formed in the copper-clad laminate 101, and the conductive holes 13 penetrate through the base material layer 11 and are connected to the two copper foil layers 102.

Specifically, step S12 includes: a through hole is formed in the copper-clad laminate 101, and the through hole is electroplated and filled to form the conductive hole 13. The through holes can be formed by laser drilling, mechanical drilling, water jet cutting, punching and the like.

As shown in fig. 3, in step S13, the copper foil layer 102 is fabricated to form the circuit layer 12, thereby obtaining the circuit board 10.

The wiring layer 12 may be formed through an image transfer process and an etching process, or through an additive plating process. The circuit layer 12 includes a plurality of connection pads 121 located in the non-inflection region 120.

In step S20, referring to fig. 4, a dielectric layer 20 is attached to the circuit layer 12, and a plurality of blind vias 21 are formed on the dielectric layer 20 to expose the plurality of connection pads 121, respectively.

The dielectric layer 20 covers the wiring layer 12 and a portion of the surface of the substrate layer 11 exposed in the wiring layer 12. The dielectric layer 20 includes a first surface 201 facing away from the wiring board 10. The blind via 21 penetrates through the first surface 201 of the dielectric layer 20 and extends to the connection pad 121 to expose a portion of the surface of the connection pad 121 facing away from the substrate layer 11. Blind holes 21 may be formed by laser drilling, mechanical drilling, die cutting, etching, and the like.

In some embodiments, the cross-sectional width of the blind hole 21 gradually decreases from a side facing away from the connection pad 121 toward a side near the connection pad 121. I.e. the blind hole 21 has the greatest cross-sectional width at the side facing away from the connection pad 121.

The material of the dielectric layer 20 may be a flexible insulating material, such as a flexible resin, or may be a rigid insulating material, such as a prepreg containing glass fiber and epoxy resin. In this embodiment, the material of the dielectric layer 20 is a photosensitive flexible material such as photosensitive polyimide, photosensitive film (CVL), etc.

In step S30, referring to fig. 5, a slot 22 is formed on the dielectric layer 20 to expose the bending region 110 of the circuit board 10.

In this embodiment, the slot 22 penetrates the first surface 201 of the dielectric layer 20 and extends to the substrate layer 11 to expose a portion of the surface of the substrate layer 11. The slots 22 may also extend in the width direction of the circuit board 10 (inward or outward of the page in the figures) to completely separate adjacent inflection zones 120. The slots 22 may be formed by laser drilling, mechanical drilling, die cutting, etching, and the like. By providing the slots 22, the material layer in the bending region 110 is reduced, facilitating bending of the bending region 110 in a subsequent step. When the material of the dielectric layer 20 is a flexible insulating material, the step S30 may be omitted.

In step S40, referring to fig. 6, the blind holes 21 are filled with conductive paste, and the first conductive paste 31 electrically connected to the connection pads 121 is obtained by curing.

The first conductive paste 31 includes a second surface 310 facing away from the connection pad 121, the second surface 310 being recessed inward relative to the first surface 201 of the dielectric layer 20. In some embodiments, the second surface 310 has a recess depth of 10 to 30 μm with respect to the first surface 201 of the dielectric layer 20, i.e., a distance between the first surface 201 and the second surface 310 in the thickness direction of the circuit board 10 is 10 to 30 μm. In other embodiments, the second surface 310 of the first conductive paste 31 may be flush with or protrude from the first surface 201 of the dielectric layer 20.

In some embodiments, step S40 specifically includes: the blind via 21 is filled with a conductive paste, so that the blind via 21 is filled with the conductive paste, wherein the surface of the conductive paste facing away from the connection pad may be flush with or protrude from the first surface 201 of the dielectric layer 20, and after curing, a portion of the conductive paste is removed by laser or etching to recess the remaining conductive paste in the first surface 201 of the dielectric layer 20, thereby obtaining the first conductive paste block 31. In other embodiments, the blind via 21 may be filled with a conductive paste directly recessed in the first surface 201 of the dielectric layer 20, and the first conductive paste 31 is obtained after curing.

In some embodiments, in the thickness direction of the circuit board 10, the width of the first conductive paste 31 gradually decreases from the second surface 310 toward the connection pad 121, that is, the width of the second surface 310 is the maximum width of the first conductive paste 31. In other embodiments, the first conductive paste 31 may also have a uniform width in the thickness direction of the wiring board 10.

The conductive paste may be filled into the blind holes 21 by printing, coating, or the like.

The conductive paste may be tin paste, copper paste, etc. In this embodiment, the conductive paste is a solder paste.

In step S50, referring to fig. 7, the partial blind holes 21 are filled with the conductive paste again, and the second conductive paste 32 electrically connected to the corresponding first conductive paste 31 is obtained after curing.

Wherein, in two adjacent non-bending regions 120, at least one blind hole 21 in one non-bending region 120 is filled with conductive paste to obtain a second conductive paste block 32, and at least one blind hole 21 in the other non-bending region 120 is not filled with conductive paste. That is, in the adjacent two non-bending regions 120, the first conductive paste mass 31 and the second conductive paste mass 32 are provided in at least one blind hole 21 in one non-bending region 120, and only the first conductive paste mass 31 is provided in at least one blind hole 21 in the other non-bending region 120. In this embodiment, in two adjacent non-bending regions 120, all the blind holes 21 in one non-bending region 120 are filled with the conductive paste to obtain the second conductive paste block 32, and all the blind holes 21 in the other non-bending region 120 are not filled with the conductive paste again. In other embodiments, a portion of the blind via 21 in each non-inflection region 120 is filled with conductive paste to obtain a second conductive paste bump 32, while another portion is not filled with conductive paste again.

The second conductive paste 32 includes a third surface 320 facing away from the first conductive paste 31, the third surface 320 protruding outwardly relative to the first surface 201 of the dielectric layer 20. In some embodiments, the protruding height of the third surface 320 of the second conductive paste 32 with respect to the first surface 201 of the dielectric layer 20 is 0 to 5 μm greater than the recessed depth of the second surface 310 of the first conductive paste 31 with respect to the first surface 201 of the dielectric layer 20, i.e., the distance between the third surface 320 and the first surface 201 is 0 to 5 μm greater than the distance between the second surface 310 and the first surface 201 in the thickness direction of the circuit board 10. So designed, the second conductive paste 32 can be inserted into the corresponding blind hole 21 to be combined with the remaining first conductive paste 31 (the part of the first conductive paste 31 not connected with the second conductive paste 32) in the subsequent bending and pressing process.

In some embodiments, the maximum width of the second conductive paste 32 is the width of the third surface 320. The second conductive paste 32 may have a uniform or non-uniform width in the thickness direction of the circuit board 10.

Specifically, step S50 includes the steps of: a dry film 60 is attached to the first surface 201 of the dielectric layer 20, and the dry film 60 covers the blind holes 21. The dry film 60 may be classified into a photo-polymerization type dry film which hardens under light irradiation of a specific spectrum and changes from a water-soluble substance to a water-insoluble substance, and a photo-decomposition type dry film which is used in the present embodiment, in contrast. A plurality of openings are then formed in the dry film 60 to expose portions of the blind vias 21 and corresponding first conductive paste pieces 31. The exposed blind via 21 is then filled with a conductive paste to be connected to the first conductive paste block 31. And then fixing the conductive paste to obtain a second conductive paste block 32. Finally, the dry film 60 is removed to expose the remaining blind holes 21 and the corresponding first conductive paste pieces 31.

In step S60, referring to fig. 8, the bending region 110 is bent to laminate the plurality of non-bending regions 120, and then the second conductive paste 32 on the same side of the adjacent non-bending regions 120 is bonded to the first conductive paste 31 and the dielectric layer 20 on the same side is bonded to obtain the multi-layer circuit board 100.

In this embodiment, the two bending regions 110 are bent in opposite directions and then pressed to obtain the multi-layer circuit board 100 with six circuit layers 12.

After lamination, the first surfaces 201 of the dielectric layers 20 in the adjacent non-bending regions 120 are fused to form a dielectric layer having a larger thickness (being the thickness of two dielectric layers), and the two combined first conductive paste pieces 31 and the second conductive paste pieces 32 interposed therebetween form an interconnection structure penetrating through the dielectric layer, the interconnection structure having a high aspect ratio (thickness-to-diameter ratio) and electrically connecting the connection pads 121 of the adjacent circuit layers 12.

The first conductive paste 31 and the second conductive paste 32 are abutted through the second surface 310 and the third surface 320 which respectively have the largest cross-section width, so that the alignment difficulty after bending is reduced. After bending, the second conductive paste 32 is embedded into the blind hole 21 to be connected with the corresponding first conductive paste 31, so that the blind hole 21 can limit the flow of the conductive paste, and the phenomenon that the conductive paste flows onto the dielectric layer 20 during lamination is avoided.

In step S70, referring to fig. 9, the bending region 110 of the circuit board 10 is cut and removed.

Referring to fig. 9, a multi-layered circuit board 100 according to an embodiment of the present application includes a multi-layered circuit board 10, a multi-layered dielectric layer 20, and a plurality of interconnection structures. Each circuit board 10 includes a substrate layer 11 and a circuit layer 12 disposed on the substrate layer 11, and the circuit layer 12 includes a connection pad 121. The dielectric layer 20 is disposed on the substrate layer 11 and covers the circuit layer 12, wherein a portion of the dielectric layer 20 is disposed between the multi-layer circuit boards 10, and another portion of the dielectric layer 20 is disposed outside the multi-layer circuit board 100. Two dielectric layers 20 are sandwiched between each two adjacent circuit boards 10. The interconnection structure is buried in the two dielectric layers 20 between the adjacent two circuit boards 10 and connected to the connection pads 121 of the two circuit boards 10 to realize interconnection. The interconnect structure includes a first conductive paste block 31 connected to the connection pad 121 and a second conductive paste block 32 interposed between the two first conductive paste blocks 31. The bonding surface (second surface 310/third surface 320) between the first conductive paste 31 and the second conductive paste 32 and the bonding surface (first surface 201) between the two dielectric layers 20 are not on the same plane. According to the method, the plurality of first conductive paste blocks 31 are arranged on the circuit board 10, after the circuit board 10 is bent, the two first conductive paste blocks 31 are combined to form the interconnection structure with the high aspect ratio (thickness-to-diameter ratio), electroplating is not needed in the forming process of the interconnection structure, the flow is shortened, double-sided drilling is not needed, the surfaces with the largest section width of the two first conductive paste blocks 31 are abutted, the alignment difficulty is reduced, and the flow process is simplified.

In addition, by recessing the first conductive paste 31 on the first surface 201 of the dielectric layer 20 and protruding the second conductive paste 32 from the first surface 201 of the dielectric layer 20, the bonding surface (the first surface 201) between the first conductive paste 31 and the second conductive paste 32 (the second surface 310/the third surface 320) and the bonding surface (the first surface 201) between the dielectric layer 20 are not on the same plane in the subsequent lamination process, so as to avoid the conductive paste from overflowing to the dielectric layer.

Furthermore, the multi-layer circuit board 100 of the present application is formed by bending and pressing flexible circuits with uniform materials, and the expansion and contraction differences between the substrate layers 11 are small during pressing.

The foregoing description is of some embodiments of the present application, but is not limited to only those embodiments during actual application. Other variations and modifications of the present application, which are apparent to those of ordinary skill in the art, are intended to be within the scope of the present application.

Claims (10)

1. The preparation method of the multilayer circuit board is characterized by comprising the following steps of:

providing a circuit board, wherein the circuit board comprises at least two non-bending areas and bending areas positioned between the two non-bending areas, each non-bending area is provided with a circuit layer, and the circuit layer comprises a connecting pad;

attaching a dielectric layer on the circuit board, and forming a plurality of blind holes on the dielectric layer to expose a plurality of connection pads;

filling conductive paste into each blind hole to obtain a first conductive paste block electrically connected with the connecting pad;

and after bending the bending areas, pressing the bending areas, so that the first conductive paste blocks positioned on the same side in the two adjacent non-bending areas are combined, and the dielectric layers positioned on the same side are combined, thereby obtaining the multilayer circuit board.

2. The method of manufacturing a multilayer circuit board according to claim 1, wherein the dielectric layer includes a first surface facing away from the circuit layer, the blind via penetrates through the first surface, the first conductive paste block includes a second surface facing away from the connection pad, the second surface is recessed inward with respect to the first surface, and after the step of filling each blind via with the conductive paste to obtain the first conductive paste block electrically connected to the connection pad, the method of manufacturing a multilayer circuit board further includes the steps of:

filling conductive paste into part of the blind holes to obtain second conductive paste blocks electrically connected with corresponding first conductive paste blocks, wherein the blind holes in one of two adjacent non-bending areas are provided with the first conductive paste blocks and the second conductive paste blocks, the blind holes in the other two adjacent non-bending areas are provided with only the first conductive paste blocks, and the second conductive paste blocks comprise third surfaces facing away from the first conductive paste blocks, and the third surfaces protrude outwards relative to the first surfaces;

when the bending areas are subjected to bending and then are pressed, the first conductive paste blocks and the second conductive paste blocks which are positioned on the same side in the two adjacent non-bending areas are combined to combine the first conductive paste blocks positioned on the same side in the two adjacent non-bending areas.

3. The method of manufacturing a multilayer circuit board according to claim 2, wherein the protruding height of the third surface with respect to the first surface is 0 to 5 μm larger than the recessed depth of the second surface with respect to the first surface.

4. The method of manufacturing a multilayer circuit board according to claim 2, wherein the second surface has a recess depth of 10 to 30 μm with respect to the first surface.

5. The method of manufacturing a multi-layered circuit board according to claim 2, wherein the step of filling the conductive paste into the partial blind holes to obtain the second conductive paste pieces electrically connected to the corresponding first conductive paste pieces comprises the steps of:

attaching a dry film to the first surface, wherein the dry film covers a plurality of blind holes;

forming a plurality of openings on the dry film to expose a portion of the blind holes and corresponding first conductive paste pieces;

filling conductive paste into the exposed blind holes to obtain second conductive paste blocks electrically connected with the corresponding first conductive paste blocks;

the dry film is removed to expose the remaining blind vias and corresponding first conductive paste pieces.

6. The method of manufacturing a multilayer circuit board according to claim 2, wherein the width of the second surface is the maximum width of the first conductive paste, and the width of the third surface is the maximum width of the second conductive paste.

7. The method of manufacturing a multilayer circuit board according to claim 1, further comprising, after the step of attaching a dielectric layer on the wiring layer and forming a plurality of blind holes on the dielectric layer to expose a plurality of connection pads, the steps of: a trench is formed in the dielectric layer to expose the inflection region.

8. The method of manufacturing a multilayer circuit board according to claim 1, further comprising, after the step of "bending the bending region and then pressing it together", the steps of: and cutting and removing the bending area.

9. The utility model provides a multilayer circuit board, includes the multilayer circuit board, every layer circuit board including the circuit layer that has the connection pad, its characterized in that, it is equipped with two-layer dielectric layer to press from both sides between every adjacent two-layer circuit board, and the connection pad on every adjacent two-layer circuit board is connected through link up the interconnect structure of two-layer dielectric layer, interconnect structure include with two first conductive paste pieces that the connection pad on the two-layer circuit board is connected and press from both sides locate the second conductive paste piece between two first conductive paste pieces, the faying surface between two-layer dielectric layer with the faying surface between first conductive paste piece and the second conductive paste piece is not in the coplanar.

10. The multi-layer circuit board of claim 9, wherein a width of a surface of one of the first conductive paste pieces to which the second conductive paste piece is joined is a maximum width of the first conductive paste piece, and a width of a surface of the second conductive paste piece to which the other first conductive paste piece is joined is a maximum width of the second conductive paste piece.