CN117811568A - Circuit and method for controlling transistor - Google Patents

Abstract

The present disclosure relates to circuits and methods for controlling transistors. A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor with a second controllable threshold voltage. When the first voltage is smaller than the third voltage, a fourth control voltage larger than a fifth threshold voltage of the MOS transistor is applied to the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is less than the fifth voltage. The second voltage is equal to the first constant value between the first time and the second time, and is equal to the second variable value between the second time and the third time. The second value is equal to the sum of the first voltage and the sixth positive voltage. The third time corresponds to a time when the first voltage is inverted.

Description

Circuit and method for controlling transistor

Priority claim

The present application claims the benefit of priority from french patent application No.2209951 filed at 2022, 9 and 30, the contents of which are hereby incorporated by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to electronic devices and systems, and more particularly, to circuits and methods for controlling transistors, such as N-channel MOS-type transistors.

Background

In the field of electronics, it is common for some components to be associated with control circuitry so that they can operate optimally.

Transistors are often associated with control circuitry configured to apply a control voltage to a transistor control terminal.

It would be preferable to be able to at least partially improve some aspects of the transistor control circuit.

There is a need for more efficient transistor control circuits.

Transistor control circuitry is required to enable current leakage to be limited during state transitions of the transistor.

A self-powered control circuit for the transistor is required.

All or some of the disadvantages of the known transistor control circuits need to be addressed.

Disclosure of Invention

One embodiment provides a method for controlling an N-channel MOS transistor, the method comprising: comparing a first voltage between a drain and a source of the transistor to a second controllable threshold voltage; applying a fourth control voltage between the gate and source of the transistor that is greater than a fifth threshold voltage of the transistor when the first voltage is less than a third voltage; applying the fourth control voltage, which is smaller than the fifth threshold voltage of the transistor, between a gate and a source of the transistor when the first voltage is greater than the second voltage; wherein the second voltage: equal to a first constant value between a first time and a second time; and is equal to a second variable value between the second time and a third time; the second variable value is equal to a sum of the first voltage and a sixth positive voltage, wherein the third time corresponds to a time at which the first voltage is inverted.

According to one embodiment, the first constant value is about 0V.

According to one embodiment, the first period between the first time and the second time is a constant period corresponding to one third of a second period corresponding to one third of the entire period of the on period of the transistor.

According to one embodiment: applying a fourth control voltage between the gate and source of the transistor at a third value greater than a fifth threshold voltage of the transistor prior to a fourth time between the first time and the third time; and applying the fourth control voltage reduced to a fourth value between the gate and the source of the transistor between the fourth time and the third time.

According to one embodiment, between the fourth time and the third time, the fourth value is reached when the first voltage is equal to a seventh voltage.

According to one embodiment, the seventh voltage is equal to a factor multiplied by the third voltage, the third voltage representing a voltage level reached between the drain terminal and the source terminal of the transistor when the parasitic diode of the transistor is turned on.

According to one embodiment, the coefficient is between one third and two thirds.

According to an embodiment, the fourth time is between the second time and the third time.

Another embodiment provides a control circuit configured to implement the method as described above.

A further embodiment provides an electronic device comprising a control circuit as described above.

According to one embodiment, the device further comprises an N-channel MOS-type transistor and a driving circuit for said transistor.

A further embodiment provides an apparatus for converting a voltage comprising an apparatus as previously described.

According to one embodiment, the means for converting a voltage is a transformer switching converter.

According to one embodiment, the means for converting the voltage is an up-converter (up-converter).

According to one embodiment, the means for converting a voltage is a buck converter.

Drawings

The above features and advantages and others will be described in detail in the following description of particular embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:

fig. 1 very schematically illustrates in block diagram form a common embodiment of a control circuit for a transistor;

FIG. 2 schematically illustrates, in block diagram form, an example application of the embodiment of FIG. 1;

FIG. 3 schematically illustrates, in block diagram form, another example application of the embodiment of FIG. 1;

fig. 4 schematically illustrates in block diagram form a first more detailed embodiment of a control circuit for a transistor;

FIG. 5 illustrates a timing diagram representing the operation of the embodiment of FIG. 4;

FIG. 6 schematically illustrates an example implementation of a portion of the embodiment of FIG. 4;

fig. 7 schematically illustrates in block diagram form a second more detailed embodiment of a control circuit for a transistor;

FIG. 8 illustrates a block diagram representing a method for implementing the embodiment of FIG. 7;

FIG. 9 schematically illustrates an example implementation of a portion of the embodiment of FIG. 7; and

fig. 10 schematically illustrates in block diagram form a third more detailed embodiment of a control circuit for a transistor.

Detailed Description

In the various drawings, like features have been designated by like reference numerals. In particular, structural and/or functional features common among the various embodiments may have the same reference numerals and may have the same structural, dimensional, and material characteristics.

For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate elements other than conductors, and when referring to two elements being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

In the following disclosure, unless otherwise indicated, when reference is made to absolute positional qualifiers such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative positional qualifiers such as the terms "above", "below", "higher", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientations shown in the figures.

Unless specified otherwise, the terms "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

Fig. 1 very schematically illustrates in block diagram form an embodiment of an electronic device comprising a transistor 150 and its control circuit 100.

Transistor 150 is an isolated gate field effect transistor or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) type transistor (also referred to as a MOS type transistor). Further, more precisely, the transistor 150 is of an N-channel MOS type (also referred to as an NMOS transistor). Transistor 150 includes two conductive terminals and a control terminal. The first conductive terminal is the drain terminal of transistor 150 and is coupled (preferably connected) to drain node D. The second conductive terminal is the source terminal of transistor 150 and is coupled (preferably connected) to source node S. The control terminal of transistor 150 is the gate terminal of transistor 150 and is coupled (preferably connected) to gate node G. Further, like any MOS-type transistor, transistor 150 comprises a parasitic diode illustrated in fig. 1 by diode 151, the anode of which is coupled (preferably connected) to source node S and the cathode of which is coupled (preferably connected) to drain node D.

The control circuit 100 is a circuit coupled to the source S, drain D, and gate G nodes of the transistor 150, and enables the control voltage of the transistor to be provided between the gate node G and the source node S. The control circuit 100 includes a control unit 101 (or control circuit 101) and a drive circuit 102. The control circuit 100 has the particularity of being self-powered based on the voltage received between the drain terminal and the source terminal of the transistor 150. The control circuit 100 also has the specificity of self-controlling based on the voltage received between the drain terminal and the source terminal of the transistor 150.

The control unit 101 includes a logic circuit that enables several V-CMD control voltages to be provided to the driving circuit 102 and at least one power supply circuit that enables a power supply voltage VCC to be provided to the driving circuit 102. For this purpose, the control unit 101 is coupled (preferably connected) to nodes D, S and G of the transistor 150. The control unit may also receive one or more control voltages V-CTRL from the drive circuit 102. The control unit does not receive an external power supply voltage.

The driving circuit 102 is a circuit configured to supply a control voltage intended for controlling the operation of the transistor 150 between the nodes G and S based on the control voltage V-CMD supplied by the control unit 100.

An example application of the transistor 150 associated with the control circuit 100 will be described with respect to fig. 2 and 3. A detailed example of the control circuit 100 will be described with respect to fig. 4 to 10.

Fig. 2 illustrates an example embodiment of a transformer switching converter circuit 200 (also referred to as a flyback converter) using an apparatus of the type described with respect to fig. 1. In other words, the circuit 200 is a switching power supply using a transformer.

The circuit 200 comprises a primary stage 201 and a secondary stage 202 separated (galvanically isolated) by a transformer 203. More specifically, the transformer 203 is constituted by a first coil coupled to the primary stage 201 and a second coil coupled to the secondary stage 202.

The primary stage 201 includes, for example, an input voltage source S-IN that supplies an input voltage and an N-channel MOS transistor T1 associated with drive circuits T1-D (drivers). The voltage source S-IN comprises a first terminal coupled to one terminal of the first coil of the transformer 203 and a second terminal coupled (preferably connected) to a first reference node GND1 receiving a first reference potential. The transistor T1 is arranged to couple a second terminal of the first coil of the transformer, different from the first terminal, to the first reference node GND1. More specifically, the drain of transistor T1 is coupled (preferably connected) to the second terminal of the first coil of transformer 203, and the source of transistor T1 is coupled (preferably connected) to the first reference node GND1. The gate of transistor T1 receives a control voltage CMD_T1 from the drive circuits T1-D.

The secondary stage 202 includes a device 204 (MOS + driver), a capacitor C1 and a resistor R1, for example of the type described for fig. 1. The device 204 comprises a first terminal corresponding to the source terminal of the device of fig. 1 and coupled (preferably connected) with a first terminal of a second coil of the transformer 203. The device 204 includes a second terminal corresponding to the drain terminal of the device of fig. 1 and coupled (preferably connected) to the output node N1. The capacitor C1 and the resistor R1 are arranged in parallel between the node N1 and a second reference node GND2 receiving a second reference potential different from the first reference potential. The second terminal of the second coil of the transformer 203 is also coupled (preferably connected) to the second reference node GND2. Resistor R1 reflects the load placed at the output of circuit 200.

The operation of circuit 200 is a common operation of flyback converters. While the circuit 200 is operating, the circuit 200 has alternating two states.

IN a first state, the ON state, the transistor T1 is turned ON and the first winding of the transformer 203 is directly coupled to the input voltage source S-IN. This results in an increase of the magnetic flux in the transformer 203. The voltage at the second winding of the transformer is negative and the transistor of the device 204 is controlled such that it is not in an ON state. Then, the load R1 arranged between the node N1 and GND2 receives power from the capacitor C1.

In the second state, the OFF state, transistor T1 is controlled such that it is non-conductive and the transistor of device 204 is controlled to be conductive. The capacitor C1 is charged with the power stored in the transformer 203 and supplies the power to the load R1 arranged between the node N1 and GND.

Thus, to operate circuit 200, transistor T1 and the transistor of device 204 are controlled in opposite directions, typically by square wave signals of opposite phases.

Fig. 3 illustrates an example embodiment of a buck converter circuit 300 as a down-converter circuit using a device of the type described with respect to fig. 1. Typically, buck converter circuits are switching power supplies that convert a discrete voltage to another discrete voltage having a smaller value.

The circuit 300 includes: an input voltage source S-IN3; a P-channel MOS type transistor T3 associated with the driving circuit T3-D (driver); a device 302 (MOS + driver) of the type described for fig. 1; a coil B3; a capacitor C3; and a resistor R3.

An input voltage source S-IN3 is coupled between the source terminal of transistor T3 and a reference node GND3 (e.g., ground) that receives a reference potential. The driving circuits T3-D are configured to supply a control voltage CMD-T3 to the gate of the transistor T3.

The device 302 includes a first terminal corresponding to the drain terminal of the transistor included in the device 302, which is coupled (preferably connected) to the drain terminal of the transistor T3. The device 302 further comprises a second terminal corresponding to the source terminal of the transistor comprised in the device 302, which second terminal is coupled (preferably connected) to the reference node GND3. With this arrangement, the device 302 forms part of the secondary stage of the circuit 300.

Coil B3 includes a first terminal coupled (preferably connected) to the drain terminal of transistor T3 and a second terminal coupled (preferably connected) to output node N3. The capacitor C3 and the resistor R3 are arranged in parallel between the nodes N3 and GND3. Resistor R3 reflects the load placed at the output of circuit 200.

The operation of circuit 300 is a common operation of buck converters. While the circuit 200 is operating, the circuit 200 exhibits two states that alternate with each other.

IN the first state, said ON state, the transistor T3 is turned ON and the coil B3 is directly coupled to the input voltage source S-IN. This results in an increase in the magnetic flux in the coil B3. The voltage at device 302 is negative and the transistor of device 302 is controlled such that it is not ON. Then, the load R3 arranged between the node N3 and GND3 receives power from the capacitor C3.

In the second state, the OFF-state, transistor T3 is controlled such that it is non-conductive and the transistor of device 302 is controlled such that it is conductive. The electric power stored in the coil B3 is transferred to charge the capacitor C1, and electric power is supplied to the load R3 arranged between the node N3 and GND 3.

Thus, to operate circuit 300, transistor T3 and the transistor of device 302 are controlled in opposite directions, typically by square wave signals of opposite phases.

Fig. 4 illustrates, more finely in block diagram form, a first embodiment of an apparatus of the type of apparatus of fig. 1. More specifically, fig. 4 illustrates a first embodiment of an electronic device comprising a transistor 150 and a control circuit 400 of the type of transistor 150 described for the control circuit 100 of fig. 1.

Like the control circuit 100 of fig. 1, the control circuit 400 includes a drive circuit 401 (driver) that supplies a control voltage VGS4 to the transistor 150. For this purpose, the driving circuit 401 is coupled (preferably connected) to terminals G and S of the transistor 150. Further, the driving circuit 401 receives a power supply voltage VDD4 and several control voltages described in detail below.

The control circuit 400 also comprises other circuits, which all form part of a control unit 402 of the type of control unit 101 described with respect to fig. 1.

The control unit 402 includes a power supply circuit that delivers a power supply voltage VDD4 from a voltage present between the drain terminal D and the source terminal S of the transistor 150. The power supply circuit includes, for example: self-powered circuitry 404 (self-powered); a voltage regulator 405 (LDO) (linear low dropout circuit); an under-voltage lockout circuit 406 (UVLO).

The self-powered circuit 404 includes two inputs coupled (preferably connected) to terminals D and S and an output that supplies a supply voltage VDD 4. The voltage regulator 405 receives the power supply voltage VDD4 as an input and delivers the power supply voltage VCC4 having a smaller magnitude than the power supply voltage VDD4 as an output; this supply voltage VCC4 is used, for example, for supplying different circuits of the control unit 402 and also for supplying the drive circuit 401. The undervoltage lockout circuit 406 also receives the supply voltage VDD4 as an input and delivers the control voltage VUVLO as an output. The control voltage VUVLO is sent to the driving circuit 401 and is enabled to indicate whether the supply voltage VDD4 becomes too low to be supplied thereto. According to an example, if the power supply voltage VDD4 becomes smaller than the threshold voltage, the control voltage VUVLO then changes its state, and the driving circuit 401 may take this into account, so as to make, for example, the transistor 150 non-conductive, thus making the parasitic diode 151 conductive.

The control unit 402 further comprises circuitry for measuring a voltage, among: a measurement circuit 407 (VDS) coupled (preferably connected) to the D and S terminals of the transistor 150 for measuring the drain-source voltage of the transistor 150 and supplying as output a voltage VDS4 representative of the drain-source voltage of the transistor 150; and a measurement circuit 408 coupled (preferably connected) to the G and S terminals of the transistor 150 for measuring the gate-source voltage of the transistor 150 and supplying as output a voltage VGS4 representative of the gate-source voltage of the transistor 150.

The control unit 402 further comprises voltage comparison circuits 410 (Comp 2) and 411 (Comp 3), or circuits 410 and 411 for detecting a threshold by comparison.

The comparison circuit 410 receives the voltage VDS4 as an input and passes the comparison voltage VComp2 as an output. The comparison circuit 410 is configured to compare the value of the magnitude of the voltage VDS4 with a threshold voltage vth 4 that represents the voltage level between the D and S terminals of the transistor 150 when the parasitic diode 151 of the transistor 150 becomes conductive. This phenomenon occurs when the control voltage intended to render the transistor 150 non-conductive is driven at the gate, but the absolute value of the voltage measured between its drain and source terminals is too high due to the parasitic diode 151 being conductive.

The comparison circuit 411 receives the voltage VDS4 as an input and delivers the comparison voltage Vcomp1 as an output. The comparison circuit 411 is configured to compare the value of the magnitude of the voltage VDS4 with the voltage reg_vthoff4, thereby enabling the determination of the time at which the drain-source voltage of the transistor 150 is inverted. The function of the voltage Reg Vthoff4 will be described in more detail with respect to fig. 5.

According to one embodiment, the control unit 402 further comprises a generating circuit 412 for generating a voltage reg_vthoff4 and receiving as input the following voltages: a voltage VDS4; a voltage N (VDS 4) representing the on state of the transistor 150, more specifically, when the transistor is on, the voltage N (VDS 4) is in a high state, and when the transistor is off, the voltage N (VDS 4) is in a low state; a reset voltage Vrst4; and the reset voltage VrstPLL4 of other circuits of the control unit 402.

An example embodiment of the generation circuit 412 is described with respect to fig. 6.

The control unit 402 further includes a management circuit 413 (MNG) for managing the state of the transistor 150. The management circuit 413 receives as inputs the comparison voltages VComp2 and VComp3 and the output voltage N (VGPLL 4) of the other circuits of the control unit 402. The management circuit 413 delivers as outputs the voltages N (VDS 4) and Vrst4 and the control voltage Vset 4. The control voltage Vset4 has a function of transmitting a command to turn on the transistor 150 to the driving circuit 401, thereby turning on the on period of the transistor 150. The control voltage Vrst4 has a function of transmitting a command to turn off the transistor 150, that is, a command to stop turning on the transistor 150, and further a command to enable interruption of the on period of the transistor 150, to the driving circuit 401.

The control unit 402 further comprises a standby circuit 414 which receives the voltage VDS4 as input and passes as output the standby voltage VStby4 which is sent to the drive circuit 401.

The control unit 402 further includes a period adjustment circuit 415 (phase locked loop-PLL) that enables adjustment of the delay tdn4 according to the reference period tdoff 4. The circuit 415 receives the voltages Vset4, N (VDS 4) and the reset voltage Vrst4 as inputs, and passes the voltages N (VGPLL 4) and VrstPLL4 as outputs.

The control unit 402 further and finally includes a managing circuit 416 (kVGS MNG) of the level of the control voltage applied to the gate of the transistor 150. In this embodiment, the management circuitry 416 is optional. The management circuit 416 receives the voltage N (VGPLL 4) and the voltage VGS4 as inputs and passes as output the control voltage cmd_kvgs4 at the control voltage level of the transistor 150. The managing circuit 416 may further and optionally pass a control voltage Sup kVGS4 indicating that the control voltage of the transistor 150 reaches a set threshold.

Fig. 5 illustrates a timing diagram representing the operation of the embodiment described with respect to fig. 4 when used in a voltage conversion circuit of the type described with respect to fig. 2 and 3. The arrangement of fig. 4 is used more specifically as a transistor in the secondary stage of these voltage conversion circuits.

More specifically, fig. 5 illustrates the following timing diagram: a timing diagram of current ISD4 representing the current flowing through transistor 150 (i.e., the current between nodes S and D); a timing diagram of current IBD4 representing the current flowing through parasitic diode 151 of transistor 150; a timing diagram of the voltage VDS4 between the drain terminal and the source terminal of the transistor 150; a timing diagram of a threshold voltage reg_vthoff4 compared with the voltage VDS 4; a timing diagram of a threshold voltage VTHON4, wherein the threshold voltage VTHON4 corresponds to a threshold level driven at the on terminal of the transistor 150, whereby the parasitic diode 151 of the transistor 150 is considered to be on; a timing diagram of the control voltage Vset4 that causes the transistor 150 to turn on; a timing diagram of the control voltage Vsetdown4 inside the circuit 412; a timing diagram of the reset voltage VrstPLL4 of circuit 415; a timing diagram of a control voltage Vrst4 for interrupting the conduction of the transistor 150; a timing diagram of voltage VR5 within circuit 415; a timing diagram of control voltage Ving4 inside circuit 415; a timing chart of the voltage N (VDS 4) indicating the on state of the transistor 150; a timing chart of the voltage VGPLL4 corresponding to the inversion of the voltage N (VGPLL 4); a timing diagram of the control voltage VGtdoff4 inside the circuit 415; a timing chart representing the control voltage Vtdn4 inside the circuit 415 of the period tdn 4; a timing chart showing the control voltage Vtdoff4 inside the circuit 415 of the time period tdoff 4; a timing diagram of the control voltage VGS4 of transistor 150; and a timing diagram for the voltage kVGS4 of the managing circuit 416.

At an initial time t50, transistor 150 is controlled such that it is non-conductive. In other words, the voltage VGS4 is at a low level (i.e., in a state or level lower than the threshold voltage Vth of the transistor 150). Accordingly, the currents ISD4 and IBD4 flowing through the transistor 150 and its parasitic diode 151 are about zero (e.g., null), and the voltage VDS4 between the on terminals of the transistor 150 varies with the variation of the circuit in which the transistor 150 is arranged.

At an initial time 150, most of the control voltage is in a low state. More specifically, the voltages Vset4, vsetdown4, vrstPLL4, vrst4, VGPLL4, VGTdoff4, vtdoff4 are in a low state. The voltages VTHON4 and kVGS4 are constant threshold voltages, e.g., above zero. The threshold voltage reg_vthoff4 is in a constant state, for example, around 0V. The controllable threshold voltage Ving4 is at a value above zero. The voltage VR4 is a ramp voltage used by the regulator circuit 415, and is, for example, a value higher than zero in the initial state.

After time t50, at time t51, the on period of transistor 150 begins. In other words, at time t51, the on command is sent to the drive circuit 401 via the voltage Vset4 such that it causes the transistor 150 to be on. For this purpose, the driving circuit increases the voltage VGS4 up to a first value greater than the threshold voltage Vth of the transistor 150. Thus, the absolute values of voltage VDS4 and current ISD4 increase and exhibit a small swing before they stabilize as a ramp with the absolute value decreasing towards a zero value.

In addition, at the start of the on period of the transistor 150, the voltages N (VDS 4), VGPLL4, and VGtdoff4 become high states. The voltage VR4 becomes low, e.g., zero, and becomes less than the voltage Ving4.

After time t51, at time t52, the swing of voltage VDS4 and current ISD4 is deemed to end, and the matching of the controllable threshold voltage Reg_Vthoff4 may begin. According to an example, the period between times t51 and t52 is a period set when the device of the embodiment of fig. 4 is manufactured. According to an example, this period of time is equal to at least one third of the minimum period of the on period of transistor 150. When the control circuit 400 and the transistor 150 are used in one of the applications of fig. 1 or 2, the period of the on period is typically set by the switching frequency.

Thus, at time t52, voltage Vsetdown4 indicates that a match of controllable threshold voltage reg_vthoff4 may begin. The other control voltages are unchanged and voltage VR4 is still less than voltage Ving4.

The matching of the controllable threshold voltage reg_vthoff4 includes: during the entire on period of the transistor 150, i.e., until the time at which the voltage Vrst4 indicates the end of the on period, the constant voltage bias dfvref 4 (also referred to as the voltage dfvref 4) between the voltage reg_vthoff4 and the voltage VDS4 is driven by adjustment. According to an example, the value of the bias dVref4 is between 1 and 50mV, for example about 10mV. A circuit that enables the generation of the voltage Reg Vthoff4 is described with respect to fig. 6.

After time t52, at time t53, the voltage VR4 exceeds the value of the threshold voltage Ving4, and the circuit 415 is reset via the voltage VrstPLL4 that becomes a high state for a short period of time. As an example, circuit 415 may include a comparator circuit having voltages VR4 and Ving4 as inputs and supplying voltage VrstPLL4 as an output. According to an example, this reset may also be obtained by a state adjustment of the voltage VrstPLL 4. Then, a method of refining the value of the voltage Ving4 is started. The voltages Vtdn4 and Vtdoff4 become the high state.

In addition, at time t53, execution of the option function implemented by circuit 416 begins. This function enables the control voltage CMD-kVGS54 to be sent to the drive circuit so that the level of the control voltage VGS4 can be matched near the end of the on period of the transistor 150 and during the previously defined time period tdn 4. For this purpose, from time t53, the voltage VGS4 decreases up to a value kVGS4 between the threshold voltage Vth of the transistor 150 and the previous value of the voltage VGS4, which may be referred to as a high value VGS4max of the voltage VGS 4.

After time t53, at time t54, the voltages Vtdoff4 and VGtdoff4 become low states. The period between times t53 and t54 represents a reference period during which the parasitic diode 151 can be turned on.

At time t55, after the voltage Vrst4 becomes the high state, the voltage Vtdn4 becomes the low state. If time t55 is after time t54, then the value of threshold voltage Ving4 is then increased, and if time t55 is before time t54, then the value of threshold voltage Ving4 is then decreased.

In addition, at time t55, the voltage VDS4 between the D terminal and the S terminal of the transistor 150 starts to invert and becomes greater than the threshold voltage reg_vthoff4. This means that the on period of transistor 150 is complete. Then, the voltage Vrst4 quickly becomes a high state to notify the end of the on period, and the control voltage VGS4 is reduced so as to be smaller than the threshold voltage Vth of the transistor 150. Then, the voltage N (VDS 4) becomes a low state.

After time t55, at time t56, the conduction period is complete and the voltage VDS4 changes its sign, becoming positive in the case of fig. 5. If the voltage reg_vthoff4 remains constant at a value close to 0V (e.g., about 0V), the end of the on period will be detected only at time t56 and not at time t 55.

An advantage of this embodiment is that it enables to avoid excessive consumption of current at the end of the on period of the transistor 150. In practice, the end of the conduction period is indicated by the time at which the voltage VDS4 starts to invert. Once the voltage VDS4 is inverted, the parasitic diode 151 of the transistor 150 is non-conductive, but may cause current consumption due to its breakdown voltage, which may also be referred to as current leakage. By detecting the inversion as soon as possible, current consumption can be reduced.

Fig. 6 shows a circuit 500 representing an example embodiment of the circuit 412 described with respect to fig. 4.

As described with respect to fig. 4, circuit 500 receives voltages VDS4, N (VDS 4), and VrstPLL4 as inputs and passes threshold voltage reg_vthoff4 as an output. In addition, the circuit 500 receives a power supply voltage VCC4.

The circuit 500 comprises a first branch delivering a first internal control voltage vactive 5. The first branch receives: a voltage Vdiff5 corresponding to the difference between the voltage VDS4 measured at the drain and source of transistor 150 and the voltage reg_vthoff 4; a constant voltage dVref4; voltage N (VDS 4); a reset voltage VrstPLL4; and a power supply voltage VCC4.

The first branch comprises a capacitor C50 and a comparator circuit Comp51, the comparator circuit Comp51 receiving the voltage Vdiff5 at its inverting input and the voltage dfvref 4 at its non-inverting input. Capacitor C50 couples the non-inverting input of comparator circuit Comp51 to reference node GND, which receives a reference potential (e.g., ground). The capacitance value of the capacitor C50 enables the value of the voltage dfvref 4 to be set.

The first branch further comprises a logic gate AND51 of the AND (AND) type, also called AND gate AND51. A first input of the AND gate AND51 receives the voltage N (VD 51), AND a second input of the AND gate AND51 receives the output of the comparator circuit Comp 51.

The first branch further comprises a first logic gate NOR51 (or exclusive or gate NOR 51), a capacitor C51, a resistor R51 and a second exclusive or gate NOR52. The exclusive or gate NOR51 comprises a first input receiving the output of the AND gate AND51 AND a second input receiving the output of the exclusive or gate NOR52. Capacitor C51 couples the output of exclusive or gate NOR51 to both inputs of exclusive or gate NOR52. Resistor R51 couples the node receiving supply voltage VCC4 to the input of exclusive or gate NOR52. These components enable the formation of a voltage pulse generator. Those skilled in the art will know how to use another type of voltage pulse generator instead.

The first branch further and finally comprises an OR-type logic gate OR51 (also referred to as OR gate OR 51), a comparator circuit Comp52 and a flip-flop FF51. A first input of the OR gate OR51 receives the reset voltage VrstPLL4, and a second input of the OR gate OR51 receives the output of the exclusive OR gate NOR52. The non-inverting input of the comparator circuit Comp52 receives a voltage RegVthoff5, the value of which corresponds to a threshold taken by the voltage reg_thoff4 at the beginning of the on period of the transistor 150, as described with respect to fig. 5. An inverting input of the comparator circuit Comp52 is coupled to the reference node GND5 via a capacitor C52. The value of the capacitance of the capacitor C52 enables to set the value of the reference voltage vref_vthoff5 applied to the inverting input of the comparator circuit Comp52, which corresponds to the constant value taken by the voltage reg_thoff4 at the beginning of the on period described with respect to fig. 5. The flip-flop FF51 includes a control input S, a reset input R, a non-inverting output Q, and an inverting output NQ. The output of the OR gate 51 is coupled to the control input S of the flip-flop FF51, and the output of the comparator circuit Comp52 is coupled to the reset input R of the flip-flop FF51. The non-inverting output of flip-flop FF51 passes control voltage vactive 5.

The circuit 500 further comprises a second branch delivering a second internal control voltage vactive down5. The second branch receives voltage VCC4 and voltage Vrst5.

The second branch comprises a circuit D51 for increasing the time period or delay so as to enable setting of the period between times t51 and t 52. The circuit D51 receives as input an internal control signal Vthonok5 corresponding to the voltage Vset4 described with respect to fig. 4 and 5, which internal control signal is intended to be delayed to obtain the behaviour described with respect to fig. 5.

The second branch further comprises a first logic gate NOR53 (or exclusive or gate NOR 53), a capacitor C53, a resistor R52 and a second exclusive or gate NOR54. The exclusive or gate NOR53 includes a first input terminal receiving the output of the circuit D51 and a second input terminal receiving the output of the exclusive or gate NOR54. Capacitor C53 couples the output of exclusive or gate NOR53 to both inputs of exclusive or gate NOR54. Resistor R52 couples the node receiving supply voltage VCC4 to the input of exclusive or gate NOR54. These components enable the formation of a voltage pulse generator. Those skilled in the art will know how to use another type of voltage pulse generator instead.

The second branch further and finally comprises a flip-flop FF52, the flip-flop FF52 comprising a control input S, a reset input R, a non-inverting output Q and an inverting output NQ. An output of exclusive or gate NOR54 is coupled to a control input S of flip-flop FF52, and a reset input R of flip-flop FF52 receives a reset voltage Vrst4. The non-inverting output of flip-flop FF52 passes control voltage vactive down5.

The circuit 500 further and finally comprises two current sources CS51 and CS52 and a capacitor Cthoff5. The current source CS51 is controlled by the voltage vactive 5 and delivers a current Iup5 to the output node OUT5. Current source CS52 is controlled by voltage vactive down5 and delivers current Idown5 to output node OUT5. The capacitor Cthoff5 is arranged between the output node OUT5 and the reference node GND 5.

The operation of the circuit 500 is as follows. The voltage reg_vthoff is delivered by the discharge of the capacitor Cthoff5. The charging and discharging of the capacitor Cthoff5 is effected by current sources CS51 and CS52 and is thus controlled by voltages vaciveup 5 and vacivedown 5. Between times t51 and t52, the voltage reg_vthoff4 is constant. For this purpose, the current sources CS51 and CS52 are deactivated. During the remaining time (i.e. at least after time t 52) the voltage reg_vthoff4 is no longer constant, for which purpose the current source is started and the currents Iup5 and Idown5 supply the voltage Vdiff5. This is the voltage Vsetdown4 that causes the current sources CS51 and CS52 to activate.

The voltage vactive up5 enables the voltage reg_vthoff4 to be set to a reference value between times t51 and t52, and the voltage vactive down up5 enables the voltage reg_vthoff4 to be set for the rest of the on period of the transistor 150.

Fig. 7 illustrates in block diagram form and in a more elaborate manner a second embodiment of a device of the type of the device of fig. 1. More specifically, fig. 7 illustrates a second embodiment of an electronic device comprising a transistor 150 and a control circuit 700 for the transistor 150 of the type of control circuit 100 described with respect to fig. 1.

The control circuit 700 has the same elements as the control circuit 400 of fig. 4. These elements will not be described again, and only the differences between circuits 400 and 700 will be detailed.

Specifically, like the control circuit 100 of fig. 1 and the control circuit 400 of fig. 4, the control circuit 700 includes a driving circuit 401 (driver) that transfers the control voltage VGS4 to the transistor 150. For this purpose, the driving circuit 401 is coupled (preferably connected) to terminals G and S of the transistor 150. In addition, the driving circuit 401 receives a power supply voltage VDD4 and several control voltages described in detail below.

The control circuit 700 also comprises other circuits, which all form part of a control unit 702 of the type described for the control unit 101 of fig. 1 or for the control unit 402 of fig. 4.

Like the control unit 402 of fig. 4, the control unit 702 includes: a supply circuit consisting of circuits 404 (self-powered), 405 (LDO) and 406 (UVLO); a measurement circuit 407 (VDS) for measuring the drain-source voltage of the transistor 150; a comparison circuit 410 (Comp 2) and a comparison circuit 411 (Comp 3); a management circuit 413 (MNG); a standby circuit 414 (Stby); a time period adjustment circuit 415 (PLL).

Unlike the control unit 402, the control unit 702 includes a management circuit 703 (MNG) in place of the management circuit 413, and a circuit 704 (kVGS) for managing the level of the control voltage applied to the transistor 150 in place of the management circuit 416 and the circuit 408. The control unit 702 includes neither the comparison circuit 411 nor the generation circuit 412 of the voltage RegVthoff 4. Thus, in the present embodiment, the voltage VDS4 is compared with the constant reference value vref_vthoff5 set for fig. 6.

In addition, the comparison circuit 410 receives the voltage VDS4 as an input and delivers the comparison voltage VComp1 as an output. The comparison circuit 410 is configured to compare the magnitude of the voltage VDS4 to a threshold voltage VTHOFF-N (VDS 4). The comparison circuit enables the generation of the voltage N (VDS 4), and the turning-off of the driving transistor 150, which may occur when the voltage Vtdn4 is not generated, is performed in the case where the period of the on period of the transistor 150 is reduced.

According to one embodiment, the management circuit 704 receives the voltage N (VGPLL 4) as an input and passes as an output the control voltage cmd_kvgs4 of the control voltage level of the transistor 150. In addition, unlike the embodiment of fig. 4, the management circuitry 704 is not optional in the apparatus 700.

As described with respect to fig. 4 and 5, the managing circuit 704 enables control to be transferred to the driving circuit 401 such that it reduces the level of the control voltage VGS4 of the transistor 150 during the end of the on period, and more specifically such that it reduces to a second value kVGS4 closest to the threshold voltage of the transistor 150. However, the managing circuit 704 and the circuit 415 also enable information to be sent to the driving circuit such that it controls the level of the second value kVGS4 such that it is as close as possible to the threshold voltage Vth of the transistor 150. The value of the second value kVGS4 depends on the value of the current flowing through transistor 150. The more the current value decreases, the closer the value kVGS4 is to the threshold voltage Vth of the transistor 150 and vice versa. The operation of the management circuit 704 will be described with respect to fig. 8, and an example embodiment of the circuit 704 will be described with respect to fig. 9.

Fig. 8 is a block diagram representing a method of operation of the circuit 704 described with respect to fig. 7.

As described with respect to fig. 6, during the end of the on period of the transistor 150, the control voltage VGS4 may decrease to approach the threshold voltage Vth of the transistor 150.

In a first step 801 (voltage monitoring), the on period of the transistor 150 is ongoing and the voltages VDS4, VGS and VGPLL are monitored.

In step 802 (VGPLL 4 falls, VDS4< kVthon 7), voltage VGPLL exhibits a falling edge, and voltage VDS4 (absolute value) is less than threshold voltage kVthon7. As long as the two requirements are not met (no at the output N of the block in step 802), the next step is step 801, otherwise the next step is step 803 (VGS 4 reduced).

According to one embodiment, threshold voltage kVthon7 is set to the result of multiplying the coefficient k by threshold voltage VTHON4, which threshold voltage VTHON4 represents the threshold value that voltage VDS4 exceeds when parasitic diode 151 begins to conduct. The coefficient k is selected such that the control voltage VGS4 is smaller than the maximum voltage VGS4 of the transistor 150 but larger than the threshold voltage Vth and the current ISD4 remains flowing through the transistor 150 thus enabling to avoid the parasitic diode 151 from turning on. According to an example, the coefficient is between one third and two thirds.

In step 803, the control voltage VGS4 is reduced and the voltage VGS4 is still monitored. As long as the control voltage VGS4 is not equal to the threshold voltage kVthon7, the voltage VGS4 remains reduced.

In step 804 (vds4=kvthon7), the voltage VDS4 is greater than or equal to the threshold voltage kVthon7, and the next step (output Y (yes) of the block of step 804) is step 805, during which the voltage VGS4 remains constant (VGS 4=cste), and then the voltage VDS4 starts to decrease (absolute value). As previously mentioned, as long as the voltage VDS4 is not equal to the threshold voltage kVthon7 (output N of the block of step 804), the voltage VGS4 remains reduced.

An advantage of this embodiment is that the control voltage VGS4 is reduced near the end of the turn-on period of the transistor 150 so that leakage of recovery current during short-term turn-on of the parasitic diode 151 of the transistor 150 can be suppressed and sometimes avoided.

Fig. 9 illustrates a circuit 900, the circuit 900 representing an example embodiment of the circuit 704 described with respect to fig. 7 implemented in accordance with the operations described with respect to fig. 8.

As described with respect to fig. 7, circuit 900 receives voltages VDS4, vrstPLL4, vrst4 as inputs and passes control voltage cmd_kvgs4 as an output. In addition, the circuit 500 receives the control voltage Vtdn4 and the threshold voltage kVthon7 described with respect to fig. 5.

The circuit 900 includes a flip-flop FF91 that delivers as output the control voltage cmd_kvgs 4. The flip-flop FF91 includes a control input terminal S, a reset input terminal R, a non-inverting output terminal Q that passes the control voltage cmd_kvgs4, and an inverting output terminal NQ.

The circuit 900 also includes a resistor R91 and a capacitor C91. Resistor R91 receives voltage VrstPLL4 on a first terminal and its second terminal is coupled (preferably connected) to control input S of flip-flop FF91. The capacitor C91 comprises a first terminal coupled (preferably connected) to a reference node GND9 (e.g. ground) receiving a reference potential and a second terminal coupled (preferably connected) to a control input S of the flip-flop FF91.

The circuit 900 further AND finally comprises a comparator circuit Comp91, a capacitor C92, an AND-gate AND91 AND an OR-gate OR91. The comparator circuit Comp91 comprises an inverting input receiving the voltage VDS4 and a non-inverting input receiving the threshold voltage kVthon 7. The threshold voltage kVthon7 is set by the voltage across the terminals of capacitor C92. A first terminal of the capacitor C92 is coupled (preferably connected) to the non-inverting input of the comparator circuit Comp91, and a second terminal of the capacitor C92 is coupled (preferably connected) to the reference node GND9. The AND logic gate AND91 comprises a first terminal receiving the voltage Vtdn4 AND a second input coupled to an output of the comparator circuit Comp 91. The OR gate OR91 includes a first input to receive the voltage Vrst4 AND a second input coupled to an output of the AND gate AND 91. The output of OR gate OR91 is coupled to reset terminal R of flip-flop FF 91.

Fig. 10 illustrates, more precisely in block diagram form, a third embodiment of a device of the type of the device of fig. 1. More specifically, fig. 10 illustrates a third embodiment of an electronic device including a transistor 150 and its control circuit 1000.

This embodiment illustrates a combination of the embodiments of fig. 4 and 7. In other words, the control circuit 1000 implements the functions of the control circuit 400 of fig. 4 and the control circuit 700 of fig. 7. Thus, the control circuit 1000 has the same elements as the circuits 400 and 700. These elements will not be described again, and only differences between circuit 1000 and circuits 400 and 700 will be described in detail.

In particular, like the circuits 400 and 700, the control circuit 1000 includes a drive circuit 401 (driver) that transmits a control voltage VGS4 to the transistor 150. For this purpose, the driving circuit 401 is coupled (preferably connected) to terminals G and S of the transistor 150. In addition, the driving circuit 401 receives a power supply voltage VDD4 and several control voltages described in detail below.

The control circuit 1000 also comprises other circuits which all form part of a control unit 1002 of the type of the control unit 101, 402 or 702.

Like the control unit 402 of fig. 4 and the control unit 702 of fig. 7, the control unit 1002 includes: a supply circuit constituted by circuits 404 (self-powered), 405 (LDO) and 406 (UVLO), the circuit 405 delivering a supply voltage VCC4 that supplies all the circuits of the control unit 702 and the drive circuit 401; a measurement circuit 407 (VDS) of the drain-source voltage of the transistor 150; comparison circuits 410 (Comp 2) and 411 (Comp 3); a standby circuit 414 (Stby); a time period adjustment circuit 415 (PLL).

Like the control unit 402, the control unit 1002 includes a circuit 412 for generating a voltage reg_vthoff 4. According to an alternative not illustrated, the control unit 1002 may also comprise the comparison circuit 411 (Comp 3) described with respect to fig. 4.

Like the control unit 702, the control unit 1002 includes a management circuit 703 (MNG), and a circuit 704 (kVGS MNG) for managing the level of the control voltage applied to the transistor 150 instead of the management circuit 416.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of the embodiments can be combined and that other variations will readily occur to those skilled in the art.

Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the ability of those skilled in the art.

Claims (21)

1. A method for controlling an N-channel MOS transistor, comprising:

comparing a first voltage between a drain and a source of the N-channel MOS transistor with a second controllable threshold voltage and a third voltage;

applying a fourth control voltage between the gate and the source of the N-channel MOS transistor when the first voltage is less than a third voltage/the third voltage, the fourth control voltage being at a level greater than a fifth threshold voltage of the N-channel MOS transistor; and

applying the fourth control voltage between the gate and source of the N-channel MOS transistor when the first voltage is greater than the second controllable threshold voltage, the fourth control voltage being at a level less than the fifth threshold voltage of the transistor;

Wherein the second controllable threshold voltage is equal to a first constant value between a first time and a second time; and is equal to a second variable value between the second time and a third time;

the second variable value is equal to a sum of the first voltage and a sixth positive voltage; and is also provided with

Wherein the third time corresponds to a time at which the first voltage is inverted.

2. The method of claim 1, wherein the first constant value is about 0V.

3. The method of claim 1, wherein a first period between the first time and the second time is a constant period corresponding to one third of a second period corresponding to one third of an entire period of an on period of the N-channel MOS transistor.

4. The method of claim 1, further comprising:

applying the fourth control voltage of a third value greater than a fifth threshold voltage of the transistor before a fourth time between the first time and the third time; and

and applying a fourth control voltage reduced to a fourth value between the fourth time and the third time.

5. The method of claim 4, wherein between the fourth time and the third time, the fourth value is reached when the first voltage is equal to a seventh voltage.

6. The method of claim 5, wherein the seventh voltage is equal to a factor multiplied by the third voltage, the third voltage representing a voltage level between a drain terminal and a source terminal of the N-channel MOS transistor that is reached when a parasitic diode of the N-channel MOS transistor is turned on.

7. The method of claim 6, wherein the coefficient is between one third and two thirds.

8. The method of claim 4, wherein the fourth time is between the second time and the third time.

9. A control circuit configured to implement the method of claim 1.

10. An electronic device comprising the control circuit of claim 9.

11. The apparatus of claim 10, further comprising the N-channel MOS transistor and a drive circuit for the N-channel MOS transistor.

12. An apparatus for converting a voltage comprising the apparatus of claim 10.

13. The apparatus of claim 12, the apparatus being a transformer switching converter.

14. The apparatus of claim 12, the apparatus being an up-converter type converter.

15. The apparatus of claim 12, the apparatus being a buck converter.

16. A method for controlling an N-channel MOS transistor, comprising:

comparing a drain-source voltage of the N-channel MOS transistor with a first threshold voltage, wherein the first threshold voltage corresponds to an inversion of the drain-source voltage;

comparing the drain-source voltage of the N-channel MOS transistor with a second threshold voltage, wherein the second threshold voltage represents a voltage level between a drain terminal and a source terminal of the N-channel MOS transistor when a parasitic diode of the N-channel MOS transistor becomes conductive; and

applying a control voltage to a gate of the N-channel MOS transistor;

wherein the control voltage is greater than a threshold voltage of the N-channel MOS transistor when the drain-source voltage is less than the second threshold voltage;

wherein the control voltage is less than a threshold voltage of the N-channel MOS transistor when the drain-source voltage is greater than the first threshold voltage;

wherein the first threshold voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time; and is also provided with

Wherein the third time corresponds to a time at which the drain-source voltage is inverted.

17. The method of claim 16, wherein the second variable value is equal to a sum of the drain-source voltage and a positive voltage.

18. The method of claim 16, further comprising applying a control voltage of a value greater than a threshold voltage of the N-channel MOS transistor prior to a fourth time between the first time and the third time.

19. The method of claim 18, further comprising reducing the control voltage between the fourth time and the third time.

20. A control circuit configured to implement the method of claim 16.

21. An electronic device comprising the control circuit of claim 20.