CN117811537A - Unequal tracking loop filter, circuit and system - Google Patents

Unequal tracking loop filter, circuit and system Download PDF

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Publication number
CN117811537A
CN117811537A CN202410015048.3A CN202410015048A CN117811537A CN 117811537 A CN117811537 A CN 117811537A CN 202410015048 A CN202410015048 A CN 202410015048A CN 117811537 A CN117811537 A CN 117811537A
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circuit
multiplication unit
pole
signal
zero
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CN117811537B (en
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韩文霞
鲍立
曹磊
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Shanghai Xianji Semiconductor Technology Co ltd
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Shanghai Xianji Semiconductor Technology Co ltd
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Abstract

The application provides an unequal tracking loop filter, a circuit and a system, wherein the unequal tracking loop filter supports two circuit forms, namely a low-order filter and a high-order filter, and circuit parameters of pole circuits and zero circuits in the low-order filter and the high-order filter are related to a time interval between current sampling and last sampling, so that the circuit parameters are updated according to the time interval, and the system can still keep stable convergence under different input sampling frequencies. Further, the higher order filter in the present application can track acceleration, and thus there is no tracking error associated with acceleration.

Description

Unequal tracking loop filter, circuit and system
Technical Field
The application relates to the technical field of filtering, in particular to the technical field of motors, and particularly relates to an unequal tracking loop filter, a circuit and a system.
Background
In the technical field of motor control, a tracking loop filter is often required to track and filter the position of a motor to obtain position, speed and acceleration information, and the function can be efficiently realized by using an application specific integrated circuit. In existing products (such as the AD2S1210 series of ADI in the united states), a Type II tracking loop filter is used, but the input sampling frequency is fixed and the system cannot be kept stable under unequal sampling inputs. Further, the existing filter cannot track the acceleration, and there is a tracking error related to the acceleration.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a tracking loop filter for solving the technical problem that the sampling frequency of the current tracking loop filter input is fixed, and the system cannot be kept stable when sampling input is not equal.
To achieve the above and other related objects, a first aspect of the present application provides an unequal tracking loop low-order filter, which includes a feedback circuit, and further includes a speed difference calculation module, a pole and zero circuit, a first integrator module of a first type, and a first integrator module of a second type, which are sequentially connected in series; the input signal of the low-order filter of the unequal tracking loop is a current position signal and supports unequal input; the feedback circuit is used for feeding back a predicted position signal, and the predicted position signal is subtracted from the current position signal to obtain a corresponding error; the speed difference calculation module is used for increasing the error and calculating to obtain a corresponding speed difference; the pole and zero circuit update circuit parameters according to the time interval between the current sampling and the last sampling, and are used for filtering the input speed difference; the first integrator module is used for receiving the filtered speed difference and integrating the speed difference to obtain a corresponding speed signal; the second type first integrator module is used for receiving the speed signal and performing integral processing on the speed signal to obtain a corresponding position signal; the speed signal output by the first integrator module of the first type and the position signal output by the first integrator module of the second type are transmitted back to the feedback circuit for generating the predicted position signal.
In some embodiments of the first aspect of the present application, the predicted position signal is represented as follows:
P prediction ＝P+VT；
Wherein P is Prediction Representing a predicted position signal; p represents the tracked position signal; v represents the tracked velocity signal; t is the time interval between the current sample and the last sample.
In some embodiments of the first aspect of the present application, the pole and zero circuits are comprised of pole circuits and zero circuits in series in sequence; the circuit parameters of the pole circuit and the zero circuit are both related to the time interval between the current sample and the last sample, so that the circuit parameters are updated according to the time interval.
In some embodiments of the first aspect of the present application, the structure of the pole circuit comprises: multiplication unit B 0 Multiplication unit B 1 An addition unit; multiplication unit B 0 Multiplication unit B 1 All are connected with an addition unit; multiplication unit B 0 The speed difference output by the input speed difference calculation module is represented as B by a multiplicand 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit B 1 Input pole circuit output signal at last sampling time, multiplicand is B 1 The method comprises the steps of carrying out a first treatment on the surface of the The adding unit is used for adding the multiplying unit B 0 And multiplication unit B 1 Is added up.
In some embodiments of the first aspect of the present application, the multiplication unit B 0 Multiplier B of (2) 0 Multiplication unit B 1 Multiplier B of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant.
In some embodiments of the first aspect of the present application, the zero circuit includes: multiplication unit A 0 Multiplication unit A 1 A subtracting unit; multiplication unit A 0 Multiplication unit A 1 Are all connected with a subtraction unit; multiplication unit A 0 Input pole circuit output signal, multiplicand of A 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit A 1 Input signal of the zero circuit at last sampling, multiplicand is A 1 The method comprises the steps of carrying out a first treatment on the surface of the The subtracting unit is used for multiplying unit A 0 And multiplication unit A 1 Is subtracted from the output signal of (a).
In some embodiments of the first aspect of the present application, the multiplication unit A 0 Multiplier A of (2) 0 Multiplication unit A 1 Multiplier A of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
To achieve the above and other related objects, a second aspect of the present application provides an unequal tracking loop high order filter comprising: the unequal tracking loop high-order filter comprises a feedback circuit, and further comprises an acceleration difference calculation module, a first class second integrator module, a pole and zero circuit, a second class second integrator module, a zero circuit and a second class third integrator module which are sequentially connected in series; the input signal of the unequal tracking loop high-order filter is a current position signal and supports unequal input; the feedback circuit is used for feeding back a predicted position signal, and the predicted position signal is subtracted from the current position signal to obtain a corresponding error; the acceleration difference calculation module is used for increasing the error and calculating to obtain a corresponding acceleration difference; the pole and zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling and is used for filtering the received acceleration signal; the second integrator module is used for receiving the acceleration signals after the filtering processing and carrying out integration processing on the acceleration signals to obtain corresponding speed signals; the zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling, and is used for receiving the speed signal and filtering the speed signal to obtain a filtered speed signal; the second class third integrator module is used for receiving the filtered speed signal and performing integration processing on the speed signal to obtain a corresponding position signal; the filtered acceleration signals output by the pole and zero circuits, the filtered speed signals output by the zero circuits and the position signals output by the second type third integrator module are transmitted back to the feedback circuit for generating the predicted position signals of the predicted position signals to update the predicted position signals of circuit parameters.
In some embodiments of the second aspect of the present application, the predicted position signal is represented as follows:
wherein P is Prediction Representing a predicted position signal; p represents the tracked position signal; v represents the tracked velocity signal; t is the time interval between the current sample and the last sample; a represents the tracked acceleration signal.
In some embodiments of the second aspect of the present application, the pole and zero circuits are comprised of pole circuits and zero circuits in series in sequence; the circuit parameters of the pole circuit and the zero circuit are both related to the time interval between the current sample and the last sample, so that the circuit parameters are updated according to the time interval.
In some embodiments of the second aspect of the present application, the structure of the pole circuit includes a multiplication unit B 0 Multiplication unit B 1 An addition unit; multiplication unit B 0 Multiplication unit B 1 All are connected with an addition unit; multiplication unit B 0 Input acceleration signal, multiplicand is B 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit B 1 Input pole circuit output signal at last sampling time, multiplicand is B 1 The method comprises the steps of carrying out a first treatment on the surface of the The adding unit is used for adding the multiplying unit B 0 And multiplication unit B 1 And adding.
In some embodiments of the second aspect of the present application, the multiplication unit B 0 Multiplier B of (2) 0 Multiplication unit B 1 Multiplier B of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant.
In some embodiments of the second aspect of the present application, the zero circuit includes: multiplication unit A 0 Multiplication unit A 1 A subtracting unit; multiplication unit A 0 Multiplication unit A 1 Are all connected with a subtraction unit; multiplication unit A 0 Input pole circuit output signal, multiplicand of A 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit A 1 Input signal of the zero circuit at last sampling, multiplicand is A 1 The method comprises the steps of carrying out a first treatment on the surface of the The subtracting unit is used for multiplying unit A 0 And multiplication unit A 1 Is subtracted from the output signal of (a).
In some embodiments of the second aspect of the present application, the multiplication unit A 0 Multiplier A of (2) 0 Multiplication unit A 1 Multiplier A of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
To achieve the above and other related objects, a third aspect of the present application provides a pole and zero circuit comprising a pole circuit and a zero circuit connected in series; the circuit parameters in the pole circuit and the zero circuit are related to the time interval between the current sampling and the last sampling;
multiplier B of two multiplication units in the pole circuit 0 And B 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant;
multiplier a of two multiplication units in the zero circuit 0 And A 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
To achieve the above and other related objects, a fourth aspect of the present application provides an unequal tracking loop filter system including an unequal tracking loop low order filter, and/or an unequal tracking loop high order filter.
As described above, the unequal tracking loop filter, circuit and system of the present application have the following beneficial effects: the zero circuit and the pole circuit used by the low-order filter and the high-order filter are related to the time interval between the current sampling and the last sampling, and the circuit parameters in the zero circuit and the pole circuit can calculate new values each time according to the time interval between the current sampling and the last sampling, so that the system can still keep stable convergence under different input sampling frequencies. Further, the higher order filter in the present application can track acceleration, and thus there is no tracking error associated with acceleration.
Drawings
Fig. 1 is a schematic diagram of a low-order filter of an unequal tracking loop according to an embodiment of the disclosure.
Fig. 2 is a schematic circuit diagram of a low-order filter of an unequal tracking loop according to an embodiment of the disclosure.
Fig. 3A shows a schematic diagram of a pole circuit in an embodiment of the present application.
Fig. 3B is a schematic diagram of a zero circuit according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a structure of an unequal tracking loop high-order filter according to an embodiment of the disclosure.
Fig. 5 is a schematic circuit diagram of an unequal tracking loop high-order filter according to an embodiment of the disclosure.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
To solve the above-mentioned problems in the background art, the present invention provides an unequal tracking loop filter X. Meanwhile, in order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be further described in detail by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:
<1> circuit zero: the points at which the numerator of the circuit transfer function is zero, i.e. the frequency points at which the transfer function is made zero. In the frequency domain, the zero point corresponds to a zero value of the transfer function.
<2> circuit pole: the point at which the denominator of the circuit transfer function is zero, i.e. the frequency point at which the transfer function is infinity. In the frequency domain, the poles correspond to the extrema of the transfer function.
The embodiment of the invention provides an unequal tracking loop filter, a circuit and a system, wherein the unequal tracking loop filter supports two circuit forms, namely a low-order filter and a high-order filter. With respect to implementation of the unequal tracking loop filter, exemplary implementation scenarios of the unequal tracking loop low-order filter and high-order filter will be described separately.
Referring to fig. 1, a schematic diagram of a low order filter of an unequal tracking loop in an embodiment of the invention is shown. The error of the low-order filter provided by the embodiment of the invention tends to 0 under the constant speed, and tracking error can exist under the condition of acceleration.
In the embodiment of the present invention, the differential tracking loop low-order filter 100 includes a feedback circuit 101, and further includes a speed difference calculation module 102, a pole-based and zero-based circuit (including a pole circuit 103A and a zero circuit 103B), a first integrator module 104 of a first type, and a first integrator module 105 of a second type, which are sequentially connected in series.
The input signal of the low-order filter of the unequal tracking loop is a current position signal and supports unequal input; the feedback circuit 101 is configured to feed back a predicted position signal, where the predicted position signal is subtracted from the current position signal to obtain a corresponding error. The speed difference calculation module 102 is configured to increase the error and calculate a corresponding speed difference. And the pole and zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling and is used for filtering the input speed difference. The first integrator module 104 is configured to receive the filtered speed difference and integrate the speed difference to obtain a corresponding speed signal; the second class of first integrator modules 105 receives the velocity signal and integrates it to obtain a corresponding position signal. Wherein the speed signal output by the first integrator module 104 of the first type and the position signal output by the first integrator module 105 of the second type are transmitted back to the feedback circuit 101 for generating the predicted position signal.
The circuit configuration of the unequal tracking loop low-order filter shown in fig. 2 is further explained below. It should be understood that the graphic representation of the cone pattern in the figure shows multiplication and the arrow direction shows the flow direction of the data. I represents an input terminal and O represents an output terminal. P represents the tracked position signal and V represents the tracked velocity signal. T represents the time interval between the current sample and the last sample.
The feedback circuit 101 specifically includes: a multiplication unit and an addition unit; the multiplier of the multiplication unit is the time interval T between the current sampling and the last sampling; the input end of the multiplication unit is connected with the output end of the first type integrator module, and the output end of the multiplication unit is connected with the input end of the addition unit; the input end of the adding unit is also connected with the output end of the second type integrator module; the output signal of the adding unit is input as the predicted position signal to a subtracting unit, which is also input with the current position signal, the subtracted signal being the error.
The predicted position signal may be expressed as follows:
P prediction =p+vt; (equation 1)
Wherein P is Prediction Representing a predicted position signal; p is the output signal of the second type integrator module, representing the tracked position signal; v is the output signal of the first type integrator module, representing the tracked speed signal; t is the time interval between the current sample and the last sample.
The speed difference calculation module 102 comprises a multiplication unit K and a multiplication unit 1/T; the multiplier of the multiplication unit K is the gain K, and the multiplier of the multiplication unit 1/T is the inverse 1/T of the time interval between the current sampling and the last sampling. Thus, the error is multiplied by the gain K and divided by T to obtain the velocity difference delta V.
The pole and zero circuits are formed by pole circuit 103A and zero circuit 103B in series. For ease of understanding by those skilled in the art, pole and zero circuits are shown in fig. 3A and 3B, respectively, for illustration.
In FIG. 3A, a specific structure of the pole circuit includes a multiplication unit B 0 Multiplication unit B 1 An addition unit; multiplication unit B 0 Multiplication unit B 1 All are connected with an addition unit; multiplication unit B 0 The speed difference delta V output by the input speed difference calculation module 102 is multiplied by B 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit B 1 Input pole circuit output signal at last sampling time, multiplicand is B 1 The method comprises the steps of carrying out a first treatment on the surface of the The adding unit is used for adding the multiplying unit B 0 And multiplication unit B 1 Is added up.
The Z-domain representation H (Z) of the transfer function of the pole circuit is as follows:
y(n)＝B 0 *x(n)+B 1 * y (n-1); (equation 2 a)
Z(y)＝B 0 *Z(x)+B 1 *Z -1* Z (y); (equation 2 b)
Z(y)*(1-Z -1* B 1 )＝Z(x)*B 0 The method comprises the steps of carrying out a first treatment on the surface of the (equation 2 c)
Wherein Z is -1* Z (y) represents the Z-domain representation of the output signal of the pole circuit at the last sample.
The formula for the transfer function in the Z domain for a pole circuit with a dc gain of 1 is as follows:
wherein b represents a Z-domain pole, G DC Indicating the dc gain.
The transfer function of the above equation 3 is converted from the Z domain to the S domain by performing bilinear inverse transformation, specifically, by using the conversion equation of the following equation 4, the transfer function of the S domain shown in equation 5 is obtained by substituting equation 4 into equation 3 and performing calculation, specifically, as follows:
let the denominator of H(s) be 0 (i.e., H(s) = infinity) pole frequency f p The following are provided:
pole time constant t p The method comprises the following steps:
according to the above formulas 1-8, and mapping the formulas 2d and 3, B can be obtained 0 、B 1 The correlation with the time interval T between the current and last samples is as follows:
in FIG. 3B, the specific structure of the zero circuit includes a multiplication unit A 0 Multiplication unit A 1 Subtracting unit, multiplying unit A 0 The multiplier is coefficient A 0 The input end of the power supply is connected with an output signal of the pole circuit, and the output end of the power supply is connected with the subtracting unit; multiplication unit A 1 The multiplier is coefficient A 1 The input end is connected with an input signal of the zero circuit during last sampling, and the output end is connected with the subtracting unit; the result of the subtraction by the subtracting unit is output as an output signal.
The Z-domain representation H (Z) of the transfer function of the zero circuit is as follows:
y(n)＝A 0 *x(n)-A 1 * x (n-1); (equation 10 a)
Z(y)＝A 0 *Z(x)-A 1 *Z(x)*Z -1 ＝Z(x)*(A 0 -A 1 *Z -1 ) The method comprises the steps of carrying out a first treatment on the surface of the (equation 10 b)
Wherein Z (x) is Z -1 Representing the Z-domain representation of the input signal at the last sampling of the zero circuit.
The formula for the transfer function in the Z domain corresponding to the zero circuit with a dc gain of 1 is as follows:
wherein a represents Z domain zero point, G DC Indicating the dc gain.
The transfer function of the above equation 10c may be converted from the Z domain to the S domain by performing bilinear inverse transformation, specifically, by using the conversion equation of the following equation 12, substituting equation 12 into equation 10 and performing calculation to obtain the transfer function of the S domain shown in equation 13, which is specifically as follows:
zero frequency f for the molecule of H(s) to be 0 (i.e., H(s) =0) z The following are provided:
zero time constant t z The method comprises the following steps:
according to the above formulas 10-16, and mapping the formulas 10c and 11, A can be obtained 0 、A 1 The correlation with the time interval T between the current and last samples is as follows:
it should be noted that, in the embodiment of the present invention, the circuit parameter a of the pole circuit and the zero circuit 0 、A 1 、B 0 、B 1 Each sampling is associated with a sampling interval T from which a new value is calculated, which is no longer fixed. In the present invention, to cope with the unequal characteristics of some motor encoders, the zero and pole in the present invention are fixed, but the circuit parameter A 0 、A 1 、B 0 、B 1 A new value is calculated each time according to the time interval T between the current input and the last input, so that stable convergence of the system can be maintained under different input sampling frequencies.
The first type first integrator module 104 is an integral 0 circuit, and specifically includes an adding unit, where the adding unit uses an output signal based on the pole and zero circuit 103 as one input signal, and uses an output signal of the first type first integrator module 104 during the last sampling as another input signal, and a result obtained by adding is output as an output signal, specifically as follows:
y (n) =x (n) +y (n-1); (equation 18 a)
Z(y)＝Z(x)+Z -1* Z (y); (equation 18 b)
The second type first integrator module 105 is an integral 1 circuit, and specifically includes a multiplication unit and an addition unit, the multiplication unit uses the output signal of the first type first integrator module 104 as an input signal, the addition unit uses the output signal of the multiplication unit as one of the input signals, and uses the output signal of the second type first integrator module 105 during the last sampling as another input signal, and the addition result is output as an output signal, where specifically:
y (n) =x (n) ×t+y (n-1); (equation 19 a)
Z(y)＝Z(x)*T+Z -1 * Z (y); (equation 19 b)
As can be seen from the above equation 19c, this transfer function is associated with the sampling interval T. It is worth emphasizing here again that: to cope with the unequal nature of some motor encoders, the zero and pole in the present invention are fixed, circuit parameter A 0 、A 1 、B 0 、B 1 A new value is calculated each time according to the time interval T between the current input and the last input, so that stable convergence of the system can be maintained under different input sampling frequencies.
In the above, an embodiment of the present invention is explained in detail with respect to an unequal tracking loop low-order filter. Hereinafter, an unequal tracking loop high order filter in an embodiment of the invention will be further described.
As shown in fig. 4, a schematic diagram of the structure of an unequal tracking loop high order filter in an embodiment of the invention is shown. The error of the high-order filter provided by the embodiment of the invention tends to 0 under constant acceleration.
In the embodiment of the present invention, the differential tracking loop high-order filter 400 includes a feedback circuit 401, and further includes a feedback circuit 401 acceleration difference calculation module 402, a first type second integrator module 403, a pole and zero circuit (including a pole circuit 404A and a zero circuit 404B), a second type second integrator module 405, a zero circuit 406, and a second type third integrator module 407, which are sequentially connected in series.
The feedback circuit 401 is configured to feed back a predicted position signal, where the predicted position signal is subtracted from the current position signal to obtain a corresponding error predicted position signal. The acceleration difference calculating module 402 is configured to increase the error and calculate a corresponding acceleration difference. The first second integrator module 403 is configured to receive the acceleration difference and integrate the acceleration difference to obtain a corresponding acceleration signal. The pole and zero circuits are used to receive and filter the acceleration signal. The second integrator module 405 is configured to receive the filtered acceleration signal and integrate the filtered acceleration signal to obtain a corresponding velocity signal. The zero circuit 406 is configured to receive and filter the velocity signal to obtain a filtered velocity signal. The second class of third integrator modules 407 is configured to receive the filtered velocity signal and integrate the velocity signal to obtain a corresponding position signal. The filtered acceleration signal output by the zero circuit 404B, the filtered velocity signal output by the zero circuit 406, and the position signal output by the second type third integrator module 407 are returned to the feedback circuit 401 to generate a predicted position signal.
The circuit configuration of the unequal tracking loop higher order filter shown in fig. 5 is further explained below. It should be understood that the graphic representation of the cone pattern in the figure shows multiplication and the arrow direction shows the flow direction of the data. I represents an input terminal and O represents an output terminal. P represents the tracked position signal, V represents the tracked velocity signal, and a represents the tracked acceleration. T represents the time interval between the current sample and the last sample.
The feedback circuit 401 specifically includes: two multiplication units and an addition unit; the multiplier of one multiplication unit is the time interval T between the current sampling and the last sampling, and the multiplier of the multiplication unit is connected with the filtered speed signal output by the zero circuit 406; the multiplier of the other multiplication unit is T 2 2, which is connected to the filtered acceleration signal output by the pole-based and zero circuit 404; output signals of two multiplication unitsThe other input signal of the adding unit is the position signal output by the third integrator module 407 of the second class, and the signal obtained by adding is taken as a predicted position signal; the subtracting unit inputs the current position signal and the predicted position signal, respectively, and the subtracted signal is output as a corresponding error.
The predicted position signal may be expressed as follows:
wherein P is Prediction Representing a predicted position signal; p is the output signal of the second type integrator module, representing the tracked position signal; v is an output signal of a filtering module based on a zero circuit, and represents a tracking speed signal; t is the time interval between the current sample and the last sample; a is an output signal of a filtering module based on a zero circuit, and represents tracked acceleration.
The acceleration difference calculation module 402 includes a multiplication unit K and a multiplication unit 1/T 2 The method comprises the steps of carrying out a first treatment on the surface of the The multiplier of the multiplication unit K is gain K, and the multiplication unit is 1/T 2 The multiplier of (2) is 1/T of the inverse square of the time interval between the current and last samples 2 . Thus, the error signal is multiplied by the gain K and divided by T 2 The speed difference delta a can then be obtained.
The first type second integrator module 403 includes an adding unit, the adding unit uses the output signal of the acceleration difference calculating module 402 as one input signal, and uses the output signal of the first type second integrator module 403 during the last sampling as another input signal, and the result obtained by adding is output as an output signal, where the specific formulas are the same as formulas 18 a-18 c above, and can be referred to.
Pole and zero circuit 404 includes pole circuit 404A and zero circuit 404B, which are identical to the circuit structures shown in fig. 2, 3A, and 3B above, and are not described in detail herein. It should be understood that the pole and zero based circuit usage in the low order filter is to filter the velocity difference and the pole and zero based circuit usage in the high order filter is to filter the acceleration signal.
The second integrator module 405 of the second type comprises an addition unit and a multiplication unit, the multiplier of which is the sampling interval T. The adding unit takes the output signal of the multiplying unit as one path of input signal, and takes the output signal of the second integrator module 405 in the last sampling as the other path of input signal, and the result obtained by adding is output as the output signal, and the calculation process and the calculation mode are the same as the formulas 19 a-19 c above, and are not repeated here.
The zero circuit 406 is identical to the zero circuits in the pole and zero circuit 404, and the circuit structures of the two are the same, but the input signal and the output signal have different adaptability, and are not described herein.
The second type third integrator module 407 has the same circuit structure as the second type integrator module in the low-order filter, and the calculation process and calculation mode are the same as those of formulas 19 a-19 c above, except that the input signal and the output signal have different adaptability, and are not described here again.
The parameters mentioned above are specifically the gain K and zero point time constant t z Constant t at pole p The system parameters may be configured and in the implementation, recommended availability parameters are shown in the following table (which is for illustration only and not for limitation):
filter type Gain K Zero time constant t z Pole time constant t p
Low order filter 256 1ms 50us
High order filter 2*256*256 1ms 50us
Preferably, the first type integrator module, the second type integrator module, the zero circuit and the pole circuit are multiplexing modules in the low-order filter and the high-order filter. That is, the first type integrator module, the second type integrator module, the zero circuit, and the pole circuit are required in the process of composing the low order filter and the high order filter, and thus can be shared as multiplexing resources in the low order filter and the high order filter. Further, the low-order filter and the high-order filter share a multiplier in multiplication operation, an adder in addition operation, a subtractor in subtraction operation, and pipeline multiplexing. Because the data operation of the filter is many, the resource consumption is large, so the invention optimizes the data operation and greatly saves the resource.
Embodiments of the present invention also provide a pole and zero circuit comprising a pole circuit and a zero circuit connected in series; the circuit parameters in the pole and zero circuits are both related to the time interval between the current and last samples.
It should be noted that, in the pole and zero circuit provided in the embodiments of the present invention, the pole circuit and the zero circuit are described in detail in the foregoing embodiments, and are not described herein again.
The embodiment of the invention also provides an unequal tracking loop filtering system, which comprises the unequal tracking loop low-order filter and the unequal tracking loop high-order filter provided in the embodiment.
Preferably, the unequal tracking loop low order filter and the unequal tracking loop high order filter share not only a pole circuit and a zero circuit but also an integrator and a feedback circuit, and also the multiplication unit K and the multiplication unit 1/T and so on. By contrast, the components that can be shared in the non-isochronous tracking loop low-order filter and the non-isochronous tracking loop high-order filter are shared, so that the circuit resources can be greatly saved and the cost can be reduced.
It should be noted that, in the unequal tracking loop filtering system provided by the embodiment of the present invention, the low-order filter and the high-order filter are both described in detail above, and are not described herein again.
In summary, the present application provides an unequal tracking loop filter, a circuit and a system, where a zero circuit and a pole circuit used by a low-order filter and a high-order filter in the present application are both related to a time interval between a current sampling and a last sampling, and circuit parameters in the zero circuit and the pole circuit each time calculate a new value according to the time interval between the current sampling and the last sampling, so that the system still can keep stable convergence under different input sampling frequencies. Further, the higher order filter in the present application can track acceleration, and thus there is no tracking error associated with acceleration. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims (16)

1. A non-isochronous tracking loop low order filter comprising:
the unequal tracking loop low-order filter comprises a feedback circuit, a speed difference calculation module, a pole and zero circuit, a first integrator module of a first type and a first integrator module of a second type which are sequentially connected in series;
the input signal of the low-order filter of the unequal tracking loop is a current position signal and supports unequal input; the feedback circuit is used for feeding back a predicted position signal, and the predicted position signal is subtracted from the current position signal to obtain a corresponding error; the speed difference calculation module is used for increasing the error and calculating to obtain a corresponding speed difference; the pole and zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling and is used for filtering the input speed difference; the first integrator module is used for receiving the filtered speed difference and integrating the speed difference to obtain a corresponding speed signal; the second type first integrator module is used for receiving the speed signal and performing integral processing on the speed signal to obtain a corresponding position signal; the speed signal output by the first integrator module of the first type and the position signal output by the first integrator module of the second type are transmitted back to the feedback circuit for generating the predicted position signal.
2. The unequal tracking loop low order filter of claim 1, wherein the predicted position signal is represented as follows:
P prediction ＝P+VT；
Wherein P is Prediction Representing a predicted position signal; p represents the tracked position signal; v represents the tracked velocity signal; t is the time interval between the current sample and the last sample.
3. The unequal tracking loop low order filter of claim 1, wherein the pole and zero circuits are comprised of pole circuits and zero circuits in series; the circuit parameters of the pole circuit and the zero circuit are both related to the time interval between the current sample and the last sample, so that the circuit parameters are updated according to the time interval.
4. The unequal tracking loop low order filter of claim 3, wherein the structure of the pole circuit comprises: multiplication unit B 0 Multiplication unit B 1 An addition unit; multiplication unit B 0 Multiplication unit B 1 All are connected with an addition unit;
multiplication unit B 0 The speed difference output by the input speed difference calculation module is represented as B by a multiplicand 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit B 1 Input pole circuit output signal at last sampling time, multiplicand is B 1 The method comprises the steps of carrying out a first treatment on the surface of the The adding unit is used for adding the multiplying unit B 0 And multiplication unit B 1 Is added up.
5. The differential tracking loop low-order filter according to claim 4, wherein the multiplying unit B 0 Multiplier B of (2) 0 Multiplication unit B 1 Multiplier B of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant.
6. The unequal tracking loop low order filter of claim 4, wherein the zero circuit structure comprises: multiplication unit A 0 Multiplication unit A 1 A subtracting unit; multiplication unit A 0 Multiplication unit A 1 Are all connected with a subtraction unit;
multiplication unit A 0 Input pole circuit output signal, multiplicand of A 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit A 1 Input signal of the zero circuit at last sampling, multiplicand is A 1 The method comprises the steps of carrying out a first treatment on the surface of the The subtracting unit is used for multiplying unit A 0 And multiplication unit A 1 Is carried out by the output signal of (2)And (5) subtracting.
7. The unequal tracking loop low order filter of claim 6, wherein the multiplication unit a 0 Multiplier A of (2) 0 Multiplication unit A 1 Multiplier A of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
8. An unequal tracking loop high order filter comprising:
the unequal tracking loop high-order filter comprises a feedback circuit, and further comprises an acceleration difference calculation module, a first class second integrator module, a pole and zero circuit, a second class second integrator module, a zero circuit and a second class third integrator module which are sequentially connected in series;
the input signal of the unequal tracking loop high-order filter is a current position signal and supports unequal input; the feedback circuit is used for feeding back a predicted position signal, and the predicted position signal is subtracted from the current position signal to obtain a corresponding error; the acceleration difference calculation module is used for increasing the error and calculating to obtain a corresponding acceleration difference; the first class second integrator module is used for receiving the acceleration difference and carrying out integration processing on the acceleration difference so as to obtain a corresponding acceleration signal; the pole and zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling and is used for filtering the received acceleration signal; the second integrator module is used for receiving the acceleration signals after the filtering processing and carrying out integration processing on the acceleration signals to obtain corresponding speed signals; the zero circuit updates circuit parameters according to the time interval between the current sampling and the last sampling, and is used for receiving the speed signal and filtering the speed signal to obtain a filtered speed signal; the second class third integrator module is used for receiving the filtered speed signal and performing integration processing on the speed signal to obtain a corresponding position signal; the filtered acceleration signals output by the pole and zero circuits, the filtered speed signals output by the zero circuits and the position signals output by the second type third integrator module are transmitted back to the feedback circuit for generating the predicted position signals.
9. The unequal tracking loop higher order filter of claim 8, wherein the predicted position signal is represented as follows:
wherein P prediction represents a predicted position signal; p represents the tracked position signal; v represents the tracked velocity signal; t is the time interval between the current sample and the last sample; a represents the tracked acceleration signal.
10. The unequal tracking loop higher order filter of claim 8 wherein the pole and zero circuits are comprised of pole and zero circuits in series; the circuit parameters of the pole circuit and the zero circuit are both related to the time interval between the current sample and the last sample, so that the circuit parameters are updated according to the time interval.
11. The unequal tracking loop higher order filter of claim 10 for circuit parameter updates, wherein the structure of the pole circuit comprises a multiplication unit B 0 Multiplication unit B 1 An addition unit; multiplication unit B 0 Multiplication unit B 1 All are connected with an addition unit;
multiplication unit B 0 Input acceleration signal, multiplicand is B 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit B 1 Input pole circuit output signal at last sampling time, multiplicand is B 1 The method comprises the steps of carrying out a first treatment on the surface of the The adding unit is used for adding the multiplying unit B 0 And multiplication unit B 1 And adding.
12. The unequal tracking loop higher order filter of claim 11, wherein the multiplication unit B 0 Multiplier B of (2) 0 Multiplication unit B 1 Multiplier B of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant.
13. The unequal tracking loop higher order filter of claim 10 wherein the configuration of the zero circuit of the pole and zero circuits comprises: multiplication unit A 0 Multiplication unit A 1 A subtracting unit; multiplication unit A 0 Multiplication unit A 1 Are all connected with a subtraction unit;
multiplication unit A 0 Input pole circuit output signal, multiplicand of A 0 The method comprises the steps of carrying out a first treatment on the surface of the Multiplication unit A 1 Input signal of the zero circuit at last sampling, multiplicand is A 1 The method comprises the steps of carrying out a first treatment on the surface of the The subtracting unit is used for multiplying unit A 0 And multiplication unit A 1 Is subtracted from the output signal of (a).
14. The unequal tracking loop higher order filter of claim 13, wherein the multiplication unit a 0 Multiplier A of (2) 0 Multiplication unit A 1 Multiplier A of (2) 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
15. A pole and zero circuit comprising a pole circuit and a zero circuit connected in series; the circuit parameters in the pole circuit and the zero circuit are related to the time interval between the current sampling and the last sampling; wherein:
multiplier B of two multiplication units in the pole circuit 0 And B 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is p Is a pole time constant;
multiplier a of two multiplication units in the zero circuit 0 And A 1 The manner of associating the time interval T between the current and last samples includes:
wherein t is z Is a zero point time constant.
16. An unequal tracking loop filter system comprising an unequal tracking loop low order filter as claimed in any of claims 1 to 7 and an unequal tracking loop high order filter as claimed in any of claims 8 to 14.
CN202410015048.3A 2024-01-04 Unequal tracking loop filter, circuit and system Active CN117811537B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234984A (en) * 2020-10-30 2021-01-15 麦歌恩电子(上海)有限公司 Multi-order tracking loop circuit and control method thereof
CN112350726A (en) * 2020-10-30 2021-02-09 重庆睿歌微电子有限公司 Interpolation system and method based on second-order tracking loop

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234984A (en) * 2020-10-30 2021-01-15 麦歌恩电子(上海)有限公司 Multi-order tracking loop circuit and control method thereof
CN112350726A (en) * 2020-10-30 2021-02-09 重庆睿歌微电子有限公司 Interpolation system and method based on second-order tracking loop

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