CN117810905A - Quick self-recovery circuit and method for BUCK converter short-circuit protection - Google Patents

Quick self-recovery circuit and method for BUCK converter short-circuit protection Download PDF

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Publication number
CN117810905A
CN117810905A CN202410034943.XA CN202410034943A CN117810905A CN 117810905 A CN117810905 A CN 117810905A CN 202410034943 A CN202410034943 A CN 202410034943A CN 117810905 A CN117810905 A CN 117810905A
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China
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circuit
signal
short
trigger
buck converter
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陈海进
晁慧
景为平
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Nantong University
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Nantong University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/06—Details with automatic reconnection
    • H02H3/066—Reconnection being a consequence of eliminating the fault which caused disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a quick self-recovery circuit and a method for BUCK converter short-circuit protection, wherein the circuit comprises a voltage comparator, a sampling clock generation circuit, an asynchronous reset counter circuit, an auxiliary starting circuit and a short-circuit judgment signal generation circuit; generating a voltage comparison signal based on a feedback voltage and a reference voltage of the converterSCP1, and willSCP1 as a three-way input; first path of input short circuit judgment signal generating circuit for generating short circuit judgment signalSCP，SCPWhen the voltage is high, short circuit is indicated; the second path is input into a sampling clock generating circuit, generates a clock signal and inputs the clock signal into an asynchronous reset counter circuit; the third path of input auxiliary starting circuit generates a reset signal，SCPWhen 1 is high level, the reset signal is high level, an asynchronous reset counter is adopted to count the clock signal, and when the count reaches 3, the output signal is turned to low level, so that the output signal is forced to be low levelSCPAt low level, the output voltage of the converter is forced to rise, so that the converter is recovered to be normal.

Description

Quick self-recovery circuit and method for BUCK converter short-circuit protection
Technical Field
The invention relates to a quick self-recovery circuit and a method for short-circuit protection of a BUCK converter, and belongs to the technical field of short-circuit protection.
Background
BUCK switching converters are widely used in various electronic systems with high efficiency. For electronic products, a power chip is indispensable and bears the heavy duty of the whole system operation. The power chip needs to be provided with various protection circuits to ensure the safe operation of the power chip in an abnormal environment, and short circuit protection is one of the protection circuits. When a short circuit occurs, an excessive current flows through the circuit, which can cause damage to the chip. Therefore, it is necessary to add a short-circuit protection circuit.
When a short circuit occurs, the short circuit current easily causes damage to the chip. In addition to controlling the short circuit current, the recovery capability of the circuit is also important when the short circuit fault is eliminated. At present, the main current method is to re-power or re-enable the chip after the short circuit condition is removed, so as to release the short circuit locking state, and the chip can only work again. This method does not have self-recovery capability. When the short circuit is removed, the chip start-up speed is significantly slowed down. In an extreme case, when the starting current is greater than the maximum current limit, the converter enters a latch state.
Most short-circuit protection circuit improvements aim to reduce the output current at the time of short circuit and reduce power consumption. The problem of circuit recovery capability after the short circuit condition is removed is often ignored. For the short circuit detection circuit, as shown in FIG. 1, the prior art will feed back the voltage V FB And a preset voltage value, generating a comparison signal through a voltage comparator. And then the comparison signal and the enabling signal are output through an AND gate, so that a short circuit detection judgment signal can be obtained. The technology reduces the design cost of the chip to a certain extent. However, after the short-circuit fault is eliminated, the output voltage VOUT is likely to be unable to return to a normal value, and the circuit enters a deadlock state and cannot trip.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: a fast self-recovery circuit and method for BUCK converter short-circuit protection is provided, which forces a short-circuit judgment signal by using an asynchronous counter function to force the output voltage to rise rapidly. After the short circuit is released, the circuit can resume normal operation in time.
The invention adopts the following technical scheme for solving the technical problems:
the fast self-recovery circuit for BUCK converter short-circuit protection comprises a voltage comparator, a sampling clock generation circuit, an asynchronous reset counter circuit, an auxiliary starting circuit and a short-circuit judgment signal generation circuit;
the voltage comparator is used for generating a voltage comparison signal SCP1 based on the feedback voltage and the reference voltage of the BUCK converter, and taking the voltage comparison signal SCP1 as three-way input; the first path is input to the input end of the short circuit judgment signal generating circuit, the short circuit judgment signal SCP is generated by the short circuit judgment signal generating circuit, when the short circuit judgment signal SCP is at a high level, namely SCP1 is at a high level, the short circuit is generated by the BUCK converter, and when the short circuit judgment signal SCP is at a low level, namely SCP1 is at a low level, the short circuit is not generated by the BUCK converter; the second path is input to the input end of the sampling clock generating circuit, the sampling clock generating circuit generates a clock signal and inputs the clock signal to the clock input end of the asynchronous reset counter circuit; the third path is input to the input end of the auxiliary starting circuit, the auxiliary starting circuit generates a reset signal, when SCP1 is in a high level, the reset signal is in a high level, and triggers the asynchronous reset counter circuit to start working, when counting to 3, SCP is forced to be in a low level, so that the output voltage of the BUCK converter is forced to rise, and the BUCK converter is restored to a normal working state; when SCP1 is low level, the reset signal is low level, the asynchronous reset counter circuit enters a blocking state, and the asynchronous reset counter circuit is started again until a short circuit occurs.
As a preferred embodiment of the circuit of the present invention, the asynchronous reset counter circuit includes a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, a NAND gate NAND AND a second AND gate AND2; the clock input end of the first trigger D1 is connected with the clock signal CLK generated by the sampling clock generating circuit, and the input end D of the first trigger D1 is connected with the output end of the first trigger D1The input end D of the first trigger D1 is also connected with the clock input end of the second trigger D2, and the output end Q of the first trigger D1 1 A first input end of the NAND gate and an output end Q of the second trigger D2 2 The output end of the NAND gate NAND is connected with the first input end of a second AND gate AND2, the reset end of the third trigger D3 is connected with the second input end of the second AND gate AND2, AND the output ends of the second AND gate AND2 are respectively connected with the reset ends of the first trigger D1 AND the second trigger D2; the input end D of the second trigger D2 is connected with the output end +.>The input end D of the second trigger D2 is also connected with the clock input end of the third trigger D3, and the input end D of the third trigger D3 is connected with the output end +.>The output signal of the third flip-flop D3 is SCPSTART.
As a preferred embodiment of the circuit according to the present invention, the sampling clock generating circuit includes a first AND gate AND1, the output signal SCP1 of the voltage comparator is connected to a first input terminal of the first AND gate AND1, the output signal SCPSTART of the third flip-flop D3 is connected to a second input terminal of the first AND gate AND1, AND the first AND gate AND1 generates the clock signal CLK AND is connected to a clock input terminal of the asynchronous reset counter circuit.
As a preferred scheme of the circuit, the auxiliary starting circuit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a resistor R, a capacitor C, a diode and a first schmitt trigger circuit; after passing through the first inverter INV1 and the second inverter INV2 in sequence, the output signal SCP1 of the voltage comparator obtains a first output signal, the first output signal is connected with the positive electrode of the capacitor C after passing through the resistor R, the negative electrode of the capacitor C is grounded, the first output signal is also connected with the positive electrode of the diode, the negative electrode of the diode is connected with the positive electrode of the capacitor C, the negative electrode of the diode is also connected with the input end of the first schmitt trigger circuit, the output end of the first schmitt trigger circuit is connected with the input end of the third inverter INV3, and the output end of the third inverter INV3 generates a reset signal as an asynchronous reset signal of the third trigger D3.
As a preferred scheme of the circuit of the present invention, the short circuit judging signal generating circuit comprises a third AND gate AND3 AND a fourth AND gate AND4, the output signal SCP1 of the voltage comparator is connected with the first input end of the third AND gate AND3, the output signal of the third trigger D3 is SCPSTART connected with the second input end of the third AND gate AND3, the third AND gate AND3 generates the output signal C connected with the second input end of the fourth AND gate AND4, the first input end of the fourth AND gate AND4 is connected with the enable signal ENP, AND the fourth AND gate AND4 outputs the short circuit judging signal SCP AND the short circuit judging signal
A quick self-recovery method for BUCK converter short-circuit protection is specifically as follows:
comparing the feedback voltage of the BUCK converter with a reference voltage by utilizing a voltage comparator, generating a voltage comparison signal SCP1, and generating a short circuit judgment signal SCP according to the SCP1 to judge whether the BUCK converter is short-circuited;
when SCP is high level, it indicates that the BUCK converter is short-circuited, the asynchronous reset counter circuit counts the clock signal CLK, when the count reaches n, the asynchronous reset counter circuit forces the short-circuit judgment signal SCP to switch from high level to low level, thus forcing the output voltage of the BUCK converter to rise, and promoting the BUCK converter to recover to normal working state; n is a positive integer greater than 2;
when SCP is low, it indicates that BUCK converter has not short circuit, and the asynchronous reset counter circuit enters into blocking state, and BUCK converter works normally.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
the invention uses the asynchronous reset counter function to force the short circuit judgment signal by improving the short circuit detection circuit, so as to force the output voltage to rise rapidly. After the short circuit is released, the circuit can resume normal operation in time. The improved circuit only acts when in short circuit, and has no influence on the whole circuit. The working efficiency of the circuit in a complex environment is improved, and the reliability of the circuit is higher.
Drawings
Fig. 1 is a diagram of a conventional short-circuit protection detection circuit;
FIG. 2 is a short circuit protection circuit diagram of a BUCK converter with fast recovery capability;
FIG. 3 is a simulated waveform diagram of a soft start and output short-circuited intermittent oscillator circuit;
FIG. 4 is a simulation waveform diagram of a conventional short-circuit protection detection circuit;
fig. 5 is a simulated waveform diagram of a short-circuit protection circuit designed according to the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The invention aims to solve the problems that after the short circuit condition disappears, a circuit cannot be recovered and the recovery time is long, and provides a quick self-recovery method for the short circuit protection of a BUCK converter, which comprises the following steps:
comparing the feedback voltage of the BUCK converter with a reference voltage by utilizing a voltage comparator, generating a voltage comparison signal SCP1, and generating a short circuit judgment signal SCP according to the SCP1 to judge whether the BUCK converter is short-circuited;
when SCP is high level, it indicates that the BUCK converter is short-circuited, the asynchronous reset counter circuit counts the clock signal CLK, when the count reaches n, the asynchronous reset counter circuit forces the short-circuit judgment signal SCP to switch from high level to low level, thus forcing the output voltage of the BUCK converter to rise, and promoting the BUCK converter to recover to normal working state; n is a positive integer greater than 2, typically 3; if the value is too small, the system is not stable yet, and the circuit cannot make correct judgment in a short time. The larger the value is, the longer the circuit can be recovered to normal working time. The maximum value does not exceed 10.
When SCP is low, it indicates that BUCK converter has not short circuit, and the asynchronous reset counter circuit enters into blocking state, and BUCK converter works normally.
Based on the above method, the present invention proposes a fast self-recovery circuit for short-circuit protection of a BUCK converter, as shown in fig. 2, comprising: the device comprises a voltage comparator, a sampling clock generating circuit, an asynchronous reset counter circuit, an auxiliary starting circuit and a short circuit judging signal generating circuit. So that the circuit can be restored to a normal operating state in a short time after the short-circuit condition is released. The method comprises the following steps:
(1) The voltage comparison signal SCP1 generated by the voltage comparator is divided into three paths of inputs, wherein the first path is connected with the input end of the short circuit judgment signal generation circuit, the second path is connected with the input end of the sampling clock generation circuit, and the third path is connected with the input end of the auxiliary starting circuit. The auxiliary starting circuit mainly comprises a first inverter INV1, a second inverter INV2, an RC circuit, a diode, a first Schmitt trigger circuit and a third inverter INV3.SCP1 improves the carrying capacity through a first inverter INV1 and a second inverter INV2, and shapes and filters signals to obtain smoother output signals. The signal is connected to the resistor R and the anode of the diode. The negative electrode of the diode, the positive electrode of the resistor and the capacitor, and the input terminal of the schmitt trigger are connected to the point D. The output end of the schmitt trigger is connected with the input end of the third inverter INV3 to generate a Reset signal Reset3. As an asynchronous reset signal for the D3 flip-flop.
The invention designs an auxiliary starting circuit composed of a diode, RC and Schmitt trigger, which is mainly used for generating a D trigger reset signal. According to the unidirectional conduction characteristics of the diode. When the SCP1 is inputted with a high potential, the circuit is short-circuited, the diode is in a conductive state, and the capacitor C is charged through the diode. When the SCP1 input is low, the circuit is not shorted, the diode is in an off state, and the capacitor C is discharged through the resistor R. And generating a charge-discharge waveform through a charge-discharge loop. The square pulse with steep edges is generated by turning over and filtering through a Schmitt trigger. This signal is connected to the input terminal of the third inverter INV3, generating the inverted pulse signal Reset3. When Reset3 is low, the Reset is active and the D1, D2, D3 flip-flops do not operate. The design makes the short circuit judging signal SCP not be triggered by mistake and maintain in low level state in the period of no short circuit. The capacitance charging time formula is as follows:
the formula of the capacitor discharging time is as follows: v (V) c (t)＝Ve -t/RC
Wherein V is i For the voltage signal generated by SCP1, V C Is the positive voltage of the capacitor C. The on voltage of the diode is 0.7V. During the charge and discharge of the capacitor, the default initial value of the capacitor voltage is 0V. The choice of an appropriate RC configuration determines the rate of charge and discharge. And has a critical influence on the waveform switching speed of the schmitt trigger.
(2) The sampling clock signal is generated by a first AND gate AND1, the voltage comparison signal SCP1 being connected to a first input of AND1, AND the SCPSTART signal being connected to a second input of AND 1. The CLK signal is generated by the first AND gate AND1, AND is connected to the clock input terminal of the first flip-flop D1 for outputting the sampling clock.
(3) The D1, D2 and D3 flip-flops designed by the invention are D flip-flops with asynchronous reset low level effect. The input end D of the D1 trigger is connected with the output end of the D1 triggerThe signal is connected to the CP end of the D2 trigger and used as the input clock signal of the D2 trigger. Output terminal Q of D1 trigger 1 A first input terminal of the NAND gate is connected with the output terminal Q of the D2 trigger 2 The second input end of the NAND gate NAND is connected, the output end of the NAND gate NAND signal is connected with the first input end of the second AND gate AND2, AND the reset end of the D3 trigger is connected with the second input end of the second AND gate AND 2. Signal output of AND2The reset terminals of the D1 and D2 triggers are terminated. The input end D of the D2 trigger is connected with the output end of the D2 trigger>The signal is connected to the CP end of the D3 trigger and used as the input clock signal of the D3 trigger. The input end D of the D3 trigger is connected with the output end of the D3 trigger>The output signal is SCPSTART.
The invention designs an asynchronous Reset counter circuit, which has the main function that when the circuit is in a normal state, a voltage comparison signal SCP1 is in a low level, and Reset3 is in a low level. The D3 trigger receives the reset signal, the circuit output signal SCPSTART is high level, D1, D2 and D3 enter a blocking state, and the circuit does not work in a normal state. When the circuit is short-circuited, the output voltage VOUT decreases and the feedback voltage V FB < 0.33V. The voltage comparison signal SCP1 is high and Reset3 is high, the circuit enters a short protection period and the D1, D2, D3 flip-flops are open. The D1, D2 flip-flops begin counting. If and only if Q 2 、Q 1 At the same time, when the value is 1, the D3 trigger obtains a rising edge, and SCPSTART is turned to be low level. When the short circuit condition is eliminated, the signal can force SCP to be low level, so that the output voltage VOUT is forced to rise, and the circuit is promoted to be restored to a normal working state in a short time. When the voltage comparison signal SCP1 is low, reset3 is low and the counter circuit again enters a lockout state. Until the next short circuit occurs and then opens again.
According to the design method, after the short circuit is released, the circuit can be restored to a normal working state in a short time.
(4) The short-circuit determination signal generation circuit mainly includes a third AND gate AND3 AND a fourth AND gate AND4. The voltage comparison signal SCP1 is connected to the first input of the third AND gate AND3, AND the output signal SCPSTART of the D3 flip-flop is connected to the second input of the third AND gate AND 3. The third AND gate AND3 generates an output signal C, the enable signal ENP is connected to the first input end of the fourth AND gate AND4, AND the signal C is connected to the second end of the fourth AND gate AND4An input terminal. The short circuit judgment signals SCP AND AND are output through a fourth AND gate AND4
(5) The input end VM of the short circuit detection circuit is connected with a feedback voltage signal of the BUCK converter, and the input end VP is connected with a preset voltage comparison signal 330mv. The output end Z of the short circuit detection circuit is connected with the end of the oscillation circuit ENP2 and the end of the discontinuous conduction time module ADJN, and the output end ZN of the short circuit detection circuit is connected with the end of the oscillation circuit EN. The output end VO of the oscillating circuit is connected with the end VP of the discontinuous conduction time module.
When the VM signal is less than VP, the circuit is shorted. The comparator outputs a short circuit alarm signal SCP at a high level, en=0, enp2=1, and the intermittent oscillator is started to oscillate. The soft start voltage vsaw_st is discharged to zero during the trigger inverter into sleep. When the sleep time is over, a new soft start period is triggered to start the output. During the short circuit, the process is repeated. Due to the soft start that is open in a short circuit condition, the inductor current will quickly reach the current limit threshold. Thus, the converter starts the hiccup mode, during which the switching frequency is reduced to the original 1/4. Once the short circuit condition is eliminated, the frequency will return to normal. When the output is not shorted, en=1, enp2=0, the intermittent oscillator performs a soft start function, and the output finally stops at a high level state. The simulation short circuit condition So v signal disappears in the dormancy period, and the circuit automatically resumes all normal states. The simulation data mainly comprises: output voltage VOUT, short-circuit switch signal Sov, short-circuit detection judgment signal SCP, and soft start enable signalSoft start signal vsaw_st, inductor current signal PLUS, switching signal LX. The simulation test is shown in fig. 3.
The validity of the present invention is verified as follows. The experimental environment is cadence6.1.8, and a short circuit detection method is provided based on a COT control mode. In the conventional short-circuit protection detection circuit, an enable signal ENP and a voltage comparison signal SCP1 are passed through an and gate, and a logic judgment signal SCP is outputted. In this way, when the short circuit condition So v signal disappears during hiccup, the output voltage is liable to fall into a low state, and the comparator constantly performs a comparison cycle. The circuit cannot resume normal operation in time. As shown in fig. 4, the simulation data mainly include: the output voltage signal VOUT, the short-circuit switching signal So v, the voltage comparison signal SCP1, the short-circuit detection judgment signal SCP, the soft start signal vsaw_st, and the switching signal LX.
When a short circuit fault occurs, the invention utilizes the function of the asynchronous counter circuit to force the output voltage to climb after the short circuit condition is released. Therefore, no matter where the short circuit condition So v signal disappears, the circuit can return to the normal working state in time. As shown in fig. 5, the simulation data mainly include: the output voltage signal VOUT, the short-circuit switching signal So v, the voltage comparison signal SCP1, the short-circuit detection judgment signal SCP, the soft start signal vsaw_st, and the switching signal LX. Through comparison of fig. 4 and 5, it was found that the improved circuit was able to rise the output voltage to a normal value in a short time after the short circuit was removed. The invention has the advantage of long recovery time and no recovery.
The result shows that the invention mainly improves the short circuit detection circuit. By adding the digital circuit, the forced execution of the short circuit detection signal is realized, and the phenomenon that the circuit is long in recovery time and cannot recover after the short circuit condition is eliminated is solved. The circuit stability is improved, and the reliability of the system is improved.
The working process of the quick self-recovery circuit for BUCK converter short-circuit protection is as follows:
comparing the feedback voltage of the BUCK converter with a reference voltage by using a voltage comparator, generating a voltage comparison signal SCP1, and taking the voltage comparison signal SCP1 as three paths of input;
the first path is input to a short circuit judgment signal generation circuit, the short circuit judgment signal SCP is generated by the short circuit judgment signal generation circuit, when the short circuit judgment signal SCP is at a high level, namely SCP1 is at a high level, the short circuit is generated by the BUCK converter, and when the short circuit judgment signal SCP is at a low level, namely SCP1 is at a low level, the short circuit judgment signal SCP is not generated by the BUCK converter, namely the BUCK converter is in a normal working state;
the second path is input to a sampling clock generating circuit, the sampling clock generating circuit generates a clock signal and inputs the clock signal to an asynchronous reset counter circuit;
the third path is input to an auxiliary starting circuit, the auxiliary starting circuit generates a reset signal, when SCP1 is in a high level, the reset signal is in a high level, and triggers the asynchronous reset counter circuit to start working, when the count is up to 3, SCP is forced to be in a low level, so that the output voltage of the BUCK converter is forced to rise, and the BUCK converter is restored to a normal state; when SCP1 is low level, the reset signal is low level, the asynchronous reset counter circuit enters a blocking state and is started again until a short circuit occurs;
when SCP1 is high level, the reset signal is high level, the first trigger D1, the second trigger D2 and the third trigger D3 are opened, the first trigger D1 and the second trigger D2 start to count, if and only if Q 1 And Q 2 When the voltage is 1, the third trigger D3 obtains a rising edge, SCPSTART is turned to be low level, SCPSTART forces SCP to be low level, so that the output voltage of the BUCK converter is forced to rise, and the BUCK converter is promoted to recover to a normal working state; when SCP1 is low level, the reset signal is low level, the asynchronous reset counter circuit enters a blocking state, and the asynchronous reset counter circuit is started again until a short circuit occurs.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims (6)

1. The fast self-recovery circuit for the BUCK converter short-circuit protection is characterized by comprising a voltage comparator, a sampling clock generation circuit, an asynchronous reset counter circuit, an auxiliary starting circuit and a short-circuit judgment signal generation circuit;
the voltage comparator is used for generating a voltage comparison signal SCP1 based on the feedback voltage and the reference voltage of the BUCK converter, and taking the voltage comparison signal SCP1 as three-way input; the first path is input to the input end of the short circuit judgment signal generating circuit, the short circuit judgment signal SCP is generated by the short circuit judgment signal generating circuit, when the short circuit judgment signal SCP is at a high level, namely SCP1 is at a high level, the short circuit is generated by the BUCK converter, and when the short circuit judgment signal SCP is at a low level, namely SCP1 is at a low level, the short circuit is not generated by the BUCK converter; the second path is input to the input end of the sampling clock generating circuit, the sampling clock generating circuit generates a clock signal and inputs the clock signal to the clock input end of the asynchronous reset counter circuit; the third path is input to the input end of the auxiliary starting circuit, the auxiliary starting circuit generates a reset signal, when SCP1 is in a high level, the reset signal is in a high level, and triggers the asynchronous reset counter circuit to start working, when counting to 3, SCP is forced to be in a low level, so that the output voltage of the BUCK converter is forced to rise, and the BUCK converter is restored to a normal working state; when SCP1 is low level, the reset signal is low level, the asynchronous reset counter circuit enters a blocking state, and the asynchronous reset counter circuit is started again until a short circuit occurs.
2. The fast self-recovery circuit for BUCK converter short-circuit protection according to claim 1, wherein the asynchronous reset counter circuit includes a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, a NAND gate NAND AND a second AND gate AND2; the clock input end of the first trigger D1 is connected with the clock signal CLK generated by the sampling clock generating circuit, and the input end D of the first trigger D1 is connected with the output end of the first trigger D1The input end D of the first trigger D1 is also connected with the clock input end of the second trigger D2, and the output end Q of the first trigger D1 1 A first input end of the NAND gate and an output end Q of the second trigger D2 2 The second input end of the NAND gate is connected with the output end of the NAND gate, the first input end of the second AND gate AND2 is connected with the reset end of the third trigger D3, the second input end of the second AND gate AND2 is connected with the output end of the second AND gate AND2 respectivelyReset ends of the trigger D1 and the second trigger D2; the input end D of the second trigger D2 is connected with the output end +.>The input end D of the second trigger D2 is also connected with the clock input end of the third trigger D3, and the input end D of the third trigger D3 is connected with the output end +.>The output signal of the third flip-flop D3 is SCPSTART.
3. The fast self-recovery circuit for short-circuit protection of a BUCK converter according to claim 2, wherein the sampling clock generating circuit includes a first AND gate AND1, the output signal SCP1 of the voltage comparator is connected to a first input terminal of the first AND gate AND1, the output signal SCPSTART of the third flip-flop D3 is connected to a second input terminal of the first AND gate AND1, the first AND gate AND1 generates the clock signal CLK connected to a clock input terminal of the asynchronous reset counter circuit.
4. The fast self-recovery circuit for BUCK converter short-circuit protection according to claim 3, wherein the auxiliary start-up circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a resistor R, a capacitor C, a diode, and a first schmitt trigger circuit; after passing through the first inverter INV1 and the second inverter INV2 in sequence, the output signal SCP1 of the voltage comparator obtains a first output signal, the first output signal is connected with the positive electrode of the capacitor C after passing through the resistor R, the negative electrode of the capacitor C is grounded, the first output signal is also connected with the positive electrode of the diode, the negative electrode of the diode is connected with the positive electrode of the capacitor C, the negative electrode of the diode is also connected with the input end of the first schmitt trigger circuit, the output end of the first schmitt trigger circuit is connected with the input end of the third inverter INV3, and the output end of the third inverter INV3 generates a reset signal as an asynchronous reset signal of the third trigger D3.
5. The circuit as claimed in claim 4, wherein the short-circuit judging signal generating circuit comprises a third AND gate AND3 AND a fourth AND gate AND4, the output signal SCP1 of the voltage comparator is connected to the first input terminal of the third AND gate AND3, the output signal SCPSTART of the third trigger D3 is connected to the second input terminal of the third AND gate AND3, the output signal C generated by the third AND gate AND3 is connected to the second input terminal of the fourth AND gate AND4, the first input terminal of the fourth AND gate AND4 is connected to the enable signal ENP, the fourth AND gate AND4 outputs the short-circuit judging signal SCP AND
6. A quick self-recovery method for BUCK converter short-circuit protection is characterized by comprising the following steps:
comparing the feedback voltage of the BUCK converter with a reference voltage by utilizing a voltage comparator, generating a voltage comparison signal SCP1, and generating a short circuit judgment signal SCP according to the SCP1 to judge whether the BUCK converter is short-circuited;
when SCP is high level, it indicates that the BUCK converter is short-circuited, the asynchronous reset counter circuit counts the clock signal CLK, when the count reaches n, the asynchronous reset counter circuit forces the short-circuit judgment signal SCP to switch from high level to low level, thus forcing the output voltage of the BUCK converter to rise, and promoting the BUCK converter to recover to normal working state; n is a positive integer greater than 2;
when SCP is low, it indicates that BUCK converter has not short circuit, and the asynchronous reset counter circuit enters into blocking state, and BUCK converter works normally.
CN202410034943.XA 2024-01-10 2024-01-10 Quick self-recovery circuit and method for BUCK converter short-circuit protection Pending CN117810905A (en)

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