CN117809727A

CN117809727A - Dynamic random access memory test method and device

Info

Publication number: CN117809727A
Application number: CN202211166635.XA
Authority: CN
Inventors: 章恒嘉
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2024-04-02
Also published as: WO2024060405A1

Abstract

The disclosure provides a method and a device for testing a dynamic random access memory, and relates to the technical field of memories. The dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a memory capacitor and a first transistor NMOS transistor, a first polar plate of the memory capacitor of each memory cell is electrically connected with a drain electrode of a corresponding first transistor, and a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate, and the method comprises the following steps: charging the storage capacitor of each memory cell by applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each memory cell, the first voltage being higher than the second voltage; after the storage capacitor of each storage unit is charged for a preset time, the storage unit is read to carry out aging test on the dynamic random access memory. The method can avoid the loss of related circuits caused by the adoption of the instruction actions of activating, writing and precharging by the writing background in the burn-in test.

Description

Dynamic random access memory test method and device

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a method and a device for testing a dynamic random access memory.

Background

Burn-in testing of dynamic random access memory (Dynamic Random Access Memory, DRAM) chips eliminates early failures by controlling the operating state of the chip and applying temperature stresses. The aging test vector is mainly used for increasing the test stress in the part, improving the aging efficiency and promoting the abnormal phenomenon of the device to eliminate unqualified products in early stage.

The vector of the capacitor burn-in test part of the DRAM chip needs to be written into the background. In the related art, when writing the background, activation (Active) is performed on a Word Line (WL) basis, and after each Word Line is activated, writing (Write) is performed on a Bit Line (BL) basis, and then Precharge (Precharge) is performed after each Bit Line is written, so that the activation of the next Word Line is performed, so that the circuit loss involved in these instruction actions is greater than the capacitance, which may result in insufficient aging efficiency of the DRAM capacitance, and some devices such as WL circuit, BL circuit, sense Amplifier (SA) circuit or other circuits may be advanced to enter the loss failure period.

As described above, how to reduce the loss of WL, BL, SA, and other circuits due to the writing background in the capacitor burn-in test is a problem to be solved.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and therefore it may include information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a method and a device for testing a dynamic random access memory, which can reduce the loss of circuits such as WL, BL, SA and the like caused by writing background at least to a certain extent in a capacitor burn-in test.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to an aspect of the present disclosure, there is provided a dynamic random access memory test method, including: the dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a memory capacitor and a first transistor, the first transistor is an NMOS transistor, a first polar plate of the memory capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate, and the method comprises the following steps: charging the storage capacitance of each memory cell by applying a first voltage to the substrate and a second voltage to a second plate of the storage capacitance of each memory cell, the first voltage being higher than the second voltage; and after the storage capacitor of each storage unit is charged for a preset time, reading the storage units to perform aging test on the dynamic random access memory.

According to an embodiment of the present disclosure, by applying a first voltage across the substrate and a second voltage across the second plate of each storage capacitor, comprising: transmitting a first input signal to an input terminal of a voltage switching circuit to switch a voltage applied to the substrate from a third voltage to the first voltage and to switch a voltage applied to a second plate of each storage capacitor from a fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter and a second inverter, an input terminal of the first inverter being connected to an input terminal of the second inverter; transmitting a first input signal to an input terminal of a voltage switching circuit to switch a voltage applied to the substrate from a third voltage to the first voltage and to switch a voltage applied to a second plate of each storage capacitor from a fourth voltage to the second voltage, comprising: the first input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the third voltage to the first voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

According to an embodiment of the present disclosure, after a storage capacitor of each storage cell is charged for a predetermined period of time, performing a read operation on each storage cell includes: after the storage capacitors of the respective storage cells are charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage and to switch the voltage applied to the second plate of the respective storage capacitors from the second voltage to the fourth voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter and a second inverter, the first inverter and the second inverter sharing an input; transmitting a second input signal to an input terminal of the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the third voltage and to switch a voltage applied to a second plate of each storage capacitor from the second voltage to the fourth voltage, comprising: the second input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the first voltage to the third voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.

According to an embodiment of the present disclosure, the method further comprises: obtaining the area sizes of the plurality of storage units; a voltage difference between a first voltage and a second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.

According to still another aspect of the present disclosure, there is provided a dynamic random access memory test device including: the dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a memory capacitor and a first transistor, the first transistor is an NMOS transistor, a first polar plate of the memory capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate, and the device comprises: the control module is used for charging the storage capacitor of each storage unit by applying a first voltage on the substrate and applying a second voltage on the second polar plate of the storage capacitor of each storage unit, and the first voltage is higher than the second voltage; and the test module is used for reading the storage units after the storage capacitors of the storage units are charged for a preset time so as to carry out aging test on the dynamic random access memory.

According to an embodiment of the disclosure, the control module is further configured to: transmitting a first input signal to an input terminal of a voltage switching circuit to switch a voltage applied to the substrate from a third voltage to the first voltage and to switch a voltage applied to a second plate of each storage capacitor from a fourth voltage to the second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter and a second inverter, an input terminal of the first inverter being connected to an input terminal of the second inverter; the control module is further configured to: the first input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the third voltage to the first voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

According to an embodiment of the disclosure, the control module is further configured to: after the storage capacitors of the respective storage cells are charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage and to switch the voltage applied to the second plate of the respective storage capacitors from the second voltage to the fourth voltage.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter and a second inverter, the first inverter and the second inverter sharing an input; the control module is further configured to: the second input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the first voltage to the third voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.

According to an embodiment of the present disclosure, the apparatus further comprises: the determining module is further used for obtaining the area sizes of the storage units; a voltage difference between a first voltage and a second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.

According to still another aspect of the present disclosure, there is provided a dynamic random access memory test apparatus including a dynamic random access memory to be tested and a voltage switching circuit, wherein: the dynamic random access memory to be tested comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a memory capacitor and a first transistor, the first transistor is an NMOS transistor, a first polar plate of the memory capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, and a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate; the voltage switching circuit comprises a first output end and a second output end, wherein the first output end of the voltage switching circuit is electrically connected with the substrate and used for applying a first voltage to the substrate, the second output end of the voltage switching circuit is electrically connected with the second polar plate of each storage capacitor and used for applying a second voltage to the second polar plate of each storage capacitor, and the first voltage is higher than the second voltage so as to charge the storage capacitor of each storage unit.

According to an embodiment of the disclosure, the voltage switching circuit includes a first inverter and a second inverter, an input terminal of the first inverter is connected to an input terminal of the second inverter, an output terminal of the first inverter is the first output terminal, and an output terminal of the second inverter is the second output terminal.

According to an embodiment of the disclosure, the first inverter and the second inverter are CMOS transistors.

According to an embodiment of the disclosure, a drain electrode of the NMOS transistor and a drain electrode of the PMOS transistor of the first inverter are connected to the first output terminal, an input voltage of a source electrode of the PMOS transistor of the first inverter is the first voltage, and an input voltage of a source electrode of the NMOS transistor of the first inverter is the third voltage; the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor of the second inverter are connected with the second output end, the input voltage of the source electrode of the PMOS transistor of the second inverter is the second voltage, the input voltage of the source electrode of the NMOS transistor of the second inverter is the fourth voltage, and the fourth voltage is higher than the third voltage; the input end of the first inverter and the input end of the second inverter are used for receiving a first input signal so as to enable the PMOS transistor of the first inverter and the PMOS transistor of the second inverter to be conducted, and the NMOS transistor of the first inverter and the NMOS transistor of the second inverter to be cut off.

According to an embodiment of the disclosure, the input terminal of the first inverter and the input terminal of the second inverter are further configured to receive a second input signal to turn off the PMOS transistor of the first inverter and the PMOS transistor of the second inverter, and to turn on the NMOS transistor of the first inverter and the NMOS transistor of the second inverter.

According to an embodiment of the disclosure, a drain electrode of the NMOS transistor and a drain electrode of the PMOS transistor of the first inverter are connected to the first output terminal, an input voltage of a source electrode of the NMOS transistor of the first inverter is the first voltage, and an input voltage of a source electrode of the PMOS transistor of the first inverter is the third voltage; the drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor of the second inverter are connected with the second output end, the input voltage of the source electrode of the NMOS transistor of the second inverter is the second voltage, the input voltage of the source electrode of the PMOS transistor of the second inverter is the fourth voltage, and the fourth voltage is higher than the third voltage; the input end of the first inverter and the input end of the second inverter are used for receiving a first input signal so as to enable the NMOS transistor of the first inverter and the NMOS transistor of the second inverter to be conducted, and the PMOS transistor of the first inverter and the PMOS transistor of the second inverter to be cut off.

According to an embodiment of the disclosure, the input terminal of the first inverter and the input terminal of the second inverter are further configured to receive a second input signal to turn off the NMOS transistor of the first inverter and the NMOS transistor of the second inverter, and turn on the PMOS transistor of the first inverter and the PMOS transistor of the second inverter.

According to an embodiment of the present disclosure, the first output terminal of the voltage switching circuit is electrically connected to the substrate through a connection plug.

According to still another aspect of the present disclosure, there is provided an electronic apparatus including: a memory, a processor, and executable instructions stored in the memory and executable in the processor, the processor implementing any of the methods described above when executing the executable instructions.

According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement any of the methods described above.

According to the method for testing the dynamic random access memory, the first voltage is applied to the substrate electrically connected with the P-type silicon substrate of the first transistor of each memory cell, the second voltage lower than the first voltage is applied to the second electrode plate of each memory capacitor electrically connected with the drain electrode of the corresponding first transistor, the memory capacitor of each memory cell is charged, then after the memory capacitor of each memory cell is charged for a preset time period, the memory cells are read to conduct the aging test on the dynamic random access memory, and the word line activation, bit line writing and precharge command actions adopted in the writing test background in the capacitor aging test in the related art can be replaced, so that loss of circuits involved in the command actions due to the writing background is avoided.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 illustrates a flow chart of a write background operation.

Fig. 2 shows a graph of the relationship between failure period and failure rate of a device.

Fig. 3 shows a schematic diagram of a DRAM architecture in an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a side view of a wafer in the DRAM array shown in fig. 3.

FIG. 5 illustrates a flow chart of a method of dynamic random access memory testing in an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a voltage switching circuit, according to an example embodiment.

Fig. 7 is a schematic diagram of another voltage switching circuit shown according to an example embodiment.

Fig. 8 is a flowchart of another dynamic random access memory test method according to the embodiments shown in fig. 5 to 7.

Fig. 9 is a flow chart illustrating a writing background according to fig. 8.

Fig. 10 is a flow chart of a read operation according to the one shown in fig. 8.

FIG. 11 illustrates a block diagram of a dynamic random access memory test device in an embodiment of the disclosure.

FIG. 12 illustrates a block diagram of another dynamic random access memory test device in an embodiment of the disclosure.

Fig. 13 shows a schematic structural diagram of an electronic device in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, apparatus, steps, etc. In other instances, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise. The symbol "/" generally indicates that the context-dependent object is an "or" relationship.

In the present disclosure, unless explicitly specified and limited otherwise, terms such as "connected" and the like are to be construed broadly and, for example, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The aging test eliminates early failure by controlling the working state of the chip and applying temperature stress. The aging test can be classified into static aging, dynamic aging and aging test. Static aging refers to providing voltage only to the circuit power supply terminal and no aging vector is provided to the signal input pin, so that the internal transistor is basically not inverted. The testing in aging refers to sampling the electrical parameters of the circuit in the dynamic aging process, and completing all or part of functional tests in the aging process. Dynamic burn-in refers to providing a circuit supply voltage and a burn-in vector to enable the circuit to perform a certain function during burn-in and to enable transistors within the circuit to flip. The aging test vector is mainly used for increasing the test stress in the part, improving the aging efficiency and promoting the abnormal phenomenon of the device to eliminate unqualified products in early stage.

The capacitor burn-in Test part vector of the DRAM chip needs to be written to the background, and Active, write, precharge instruction action is adopted to activate WL successively or activate a large number of WL simultaneously through Design For Test (DFT) in the related art, and fig. 1 is a flowchart illustrating an operation of writing to the background. As shown in fig. 1, taking an example that a memory array is connected with X word lines and Y bit lines, the current word line is activated (S102), and "1" is written into each bit line after each word line is activated (S104), and when "1" is written, the time for n (n is a positive integer) chips to unselected (Device Deselected, DES) instructions (S106) is waited, wherein the DES instructions are instructions defined in a DRAM command truth table. Then, after the Y bit lines are written in (S107), the current word line is precharged (S108), and the next word line is activated to traverse the X word lines (S109). This results in the circuit loss involved in these command actions being greater than the capacitance, which in turn results in insufficient DRAM capacitance burn-in efficiency, but early entry of the loss failure period for some devices.

Fig. 2 is a graph showing a relationship between a failure period and a failure rate of a device, and as shown in fig. 2, a method of writing a background in a burn-in test adopted by the related art may cause a DRAM capacitor to remain in an early failure period, and a part of the device, such as a WL circuit, a BL circuit, a Sense Amplifier (SA) circuit, or other circuits, has entered a loss failure period.

Therefore, the present disclosure provides a method for testing a dynamic random access memory, in which a first voltage is applied to a substrate electrically connected to a P-type silicon substrate of a first transistor of each memory cell, and a second voltage lower than the first voltage is applied to a second electrode plate of each memory capacitor electrically connected to a drain electrode of a corresponding first transistor, so as to charge the memory capacitor of each memory cell, and then after the memory capacitor of each memory cell is charged for a predetermined period of time, a read operation is performed on each memory cell to perform a burn-in test on the dynamic random access memory, so that the method can replace word line activation, bit line writing, and precharge command actions used in a write test background in a capacitor burn-in test in the related art, thereby avoiding loss of circuits involved in the command actions due to the write background.

Fig. 3 shows an exemplary DRAM architecture 30 to which the dynamic random access memory test method or dynamic random access memory test apparatus of the present disclosure may be applied, with the DRAM architecture 30 being illustrated as the dynamic random access memory to be tested in an embodiment of the present disclosure.

The architecture 30 of the dynamic random access memory to be tested may include a plurality of memory cells, two memory cells 3062 and 3064 are shown in fig. 3, referring to fig. 4, a memory capacitor 4062, a memory capacitor 4064 and drains 4082 and 4084 thereof are connected to two NMOS transistors (i.e. a first transistor) through NC (Node Contact), respectively, the two transistors share a source 3066, the memory capacitor 4062 and the transistor connected thereto form a memory cell 3062 together, and the memory capacitor 4064 and the transistor connected thereto form a memory cell 3064 together. The two NMOS transistors share a source 3066 to BL 304 and the two transistors have gates 4086 and 4088 to WL 306. The memory cell array of fig. 3 may be disposed on the substrate 402 of fig. 4.

Fig. 4 is a schematic diagram of a side view of a memory cell in the DRAM array shown in fig. 3. Referring to fig. 3, fig. 4 shows a side cross-sectional view of a group 306 of memory cells sharing two sources 3066. A common Top Cell Plate (TCP) 404 (i.e., a second Plate) of the storage capacitor 4062 and the storage capacitor 4064, and the voltage applied to the TCP 404 is a second voltage V2; the lower plates (i.e., first plates) of the storage capacitors 4062 and 4064 are connected to the drains 4082 and 4084 of the two transistors, respectively, through NC, and P-type silicon substrates (also referred to as P-wells) of the two transistors are disposed on the substrate 402 to be electrically connected to the substrate, so that the storage capacitors 4062 and 4064 are electrically connected to the substrate through PN junctions of the two transistors.

In some embodiments, a connection plug 410 may be provided that is electrically connected to the substrate 402, and a first voltage V1 may be applied to the substrate 402, i.e., to the bottom plates of the storage capacitors 4062 and 4064, through the connection plug 410. Shallow trench isolation (Shallow Trench Isolation, STI) is provided between the connection plug 410 and the PN junction.

In some embodiments, a voltage switching circuit may be provided for changing the voltage applied to the substrate 402 and the voltage applied to the TCP 404, for example, a first output terminal of the voltage switching circuit is electrically connected to the substrate 402 through the connection plug 410, the voltage applied to the substrate 402 is switched from a third voltage to a first voltage higher than the third voltage, and the voltage applied to the TCP 404 is switched from a fourth voltage higher than the third voltage to a second voltage lower than the first voltage, and the storage capacitor 4062 and the storage capacitor 4064 are charged.

It should be understood that the number of memory cells in fig. 3 is merely illustrative. There may be any number of memory cells, as desired for implementation.

FIG. 5 is a flow chart illustrating a method of dynamic random access memory testing, according to an exemplary embodiment. The method shown in fig. 5 may be applied to a plurality of memory cells shown in fig. 3 and 4, for example.

Referring to fig. 5, a method 50 provided by an embodiment of the present disclosure may include the following steps.

In step S502, the storage capacitor of each memory cell is charged by applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each memory cell, the first voltage being higher than the second voltage.

In some embodiments, a voltage switching circuit may be disposed in electrical communication with the substrate, and the voltage switching circuit may be configured to switch a voltage applied to the substrate from a third voltage to a first voltage and to switch a voltage applied to the second plate of each storage capacitor from a fourth voltage to a second voltage by sending a first input signal to an input terminal of the voltage switching circuit, wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage. The specific embodiments can be seen with reference to fig. 6 and 7.

In some embodiments, the voltage difference between the first voltage and the second voltage used in the burn-in test may be determined according to the manufacturing process.

In some embodiments, the voltage difference between the first voltage and the second voltage may be determined by integrating the factors of the number of memory cells, i.e. the area where the memory cells to be subjected to the burn-in test are located, and the specific embodiments may refer to fig. 8 and 9.

In step S504, after the storage capacitor of each storage unit is charged for a predetermined period of time, a read operation is performed on each storage unit to perform a burn-in test on the dynamic random access memory.

In some embodiments, after the voltage applied to the substrate is switched from the third voltage to the first voltage and the voltage applied to the second plate of each storage capacitor is switched from the fourth voltage to the second voltage, a read operation is performed on each memory cell bit line and word line after waiting for a preset number of command clocks (tCK), for example, the duration of n DES commands, to perform a burn-in test on the dynamic random memory. The specific embodiments can be seen with reference to fig. 8 and 9.

According to the method for testing the dynamic random access memory, the first voltage is applied to the substrate electrically connected with the P-type silicon substrate of the first transistor of each memory cell, the second voltage lower than the first voltage is applied to the second electrode plate of each memory capacitor electrically connected with the drain electrode of the corresponding first transistor, the memory capacitor of each memory cell is charged, then after the memory capacitor of each memory cell is charged for a preset time period, the memory cells are read to conduct the aging test on the dynamic random access memory, and the word line activation, bit line writing and precharge command actions adopted in the writing test background in the capacitor aging test in the related art can be replaced, so that loss of circuits involved in the command actions due to the writing background is avoided. And the time of activating, writing and precharging instruction actions is saved while the test coverage rate of the capacitor in the related technology is reached, the time of writing the background in the capacitor aging test item is shortened, and the test efficiency is improved.

Fig. 6 is a schematic diagram of a voltage switching circuit, according to an example embodiment. The voltage switching circuit shown in fig. 6 may be used to apply a voltage to the substrate 402 in fig. 4 and a voltage to the TCP 404, implementing the method shown in fig. 5.

As shown in fig. 6, the voltage switching circuit may include a first output 6042 and a second input 6044, the first output 6042 of the voltage switching circuit being electrically connected to the substrate 402 and the second input 6044 being electrically connected to the TCP 404. The voltage switching circuit may include a first inverter and a second inverter, where an input terminal of the first inverter is connected to an input terminal of the second inverter, and is configured to receive the input signal 602, an output terminal of the first inverter is a first output terminal 6042, and an output terminal of the second inverter is a second output terminal 6044.

The first inverter and the second inverter may be CMOS (Complementary Metal Oxide Semiconductor ) transistors, the drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the first output end 6042 of the voltage switching circuit, the input voltage of the source of the NMOS transistor M2 of the first inverter is the third voltage V3, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the first voltage V1.

In some embodiments, the third voltage V3 may be a normal substrate operating voltage, for example, may be ground (0V); the first voltage V1 may be a high voltage, for example, VDD (operating voltage inside the device).

The drain of the NMOS transistor M3 and the drain of the PMOS transistor M4 of the second inverter are connected to the second output end 6044, the input voltage of the source of the PMOS transistor M4 of the second inverter is the second voltage V2, the input voltage of the source of the NMOS transistor M3 of the second inverter is the fourth voltage V4, and the fourth voltage V4 is higher than the third voltage V3.

In some embodiments, the fourth voltage V4 may be a TCP normal operating voltage, for example, vcc (supply voltage of the circuit)/2; the second voltage V2 may be a low voltage, for example Vss (circuit common ground voltage).

Referring to fig. 6, an input signal 602 sent to an input terminal of a first inverter may be a low-level first input signal, so that an NMOS transistor M2 of the first inverter and an NMOS transistor M3 of the second inverter are turned off, and a PMOS transistor M1 of the first inverter and a PMOS transistor M4 of the second inverter are turned on, thereby implementing a first voltage V1 applied to a substrate and a second voltage V2 applied to a TCP, that is, applying a high voltage difference between upper and lower plates of each storage capacitor, and thus implementing a charge of the storage capacitor of each storage cell.

In some embodiments, the input signal 602 sent to the input terminal of the first inverter may be the second input signal with a high level, so that the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned off, and the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned on, so that the third voltage V3 is applied to the substrate, and the fourth voltage V4 is applied to the TCP, and the storage capacitor of each memory cell is stopped from being charged.

By sending a switch between the first input signal and the second input signal to the first inverter input, a switch between applying the first voltage V1 and the third voltage V3 to the substrate and a switch between applying the second voltage V2 and the fourth voltage V4 to the TCP can be achieved.

Fig. 7 is a schematic diagram of another voltage switching circuit shown according to an example embodiment. The voltage switching circuit shown in fig. 7 may be used to apply a voltage to the substrate 402 in fig. 4 and a voltage to the TCP404, implementing the method shown in fig. 5.

As shown in fig. 7, the voltage switching circuit may include a first output 7042 and a second input 7044, the first output 7042 of the voltage switching circuit being electrically connected to the substrate 402 and the second input 7044 being electrically connected to the TCP 404. The voltage switching circuit may include a first inverter and a second inverter, where an input terminal of the first inverter is connected to an input terminal of the second inverter, and is configured to receive the input signal 702, and an output terminal of the first inverter is a first output terminal 7042, and an output terminal of the second inverter is a second output terminal 7044.

The first inverter and the second inverter may be CMOS transistors, the drain of the NMOS transistor M2 and the drain of the PMOS transistor M1 of the first inverter are connected to the first output end 7042 of the voltage switching circuit, the input voltage of the source of the NMOS transistor M2 of the first inverter is the first voltage V1, and the input voltage of the source of the PMOS transistor M1 of the first inverter is the third voltage V3.

The drain of the NMOS transistor M3 and the drain of the PMOS transistor M4 of the second inverter are connected to the second output terminal 7044, the input voltage of the source of the PMOS transistor M4 of the second inverter is the fourth voltage V4, the input voltage of the source of the NMOS transistor M3 of the second inverter is the second voltage V2, and the fourth voltage V4 is higher than the third voltage V3.

Referring to fig. 7, an input signal 702 transmitted to an input terminal of a first inverter may be a high-level first input signal, so that an NMOS transistor M2 of the first inverter and an NMOS transistor M3 of the second inverter are turned on, and a PMOS transistor M1 of the first inverter and a PMOS transistor M4 of the second inverter are turned off, thereby realizing application of a first voltage V1 to a substrate and application of a second voltage V2 to TCP, that is, applying a high voltage difference between upper and lower plates of each storage capacitor, and thus realizing charging of storage capacitors of each storage cell.

In some embodiments, the input signal 702 sent to the input terminal of the first inverter may be the second input signal with a low level, so that the PMOS transistor M1 of the first inverter and the PMOS transistor M4 of the second inverter are turned on, and the NMOS transistor M2 of the first inverter and the NMOS transistor M3 of the second inverter are turned off, thereby applying the third voltage V3 to the substrate, and applying the fourth voltage V4 to the TCP, and stopping charging the storage capacitor of each memory cell.

Referring to fig. 8, a method 80 provided by an embodiment of the present disclosure may include the following steps.

In step S802, the area sizes of a plurality of memory cells are obtained.

In some embodiments, the area size of the plurality of memory cells may be, for example, a product of a number of rows and a number of columns of an array of memory cells made up of the plurality of memory cells.

In step S804, a voltage difference between the first voltage and the second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.

In some embodiments, the area of the memory cells to be subjected to the burn-in test may be positively correlated with the voltage difference between the first voltage and the second voltage, and the larger the area of the plurality of memory cells, the larger the voltage difference between the first voltage and the second voltage.

In step S806, a first input signal is sent to an input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the third voltage to the first voltage, and to switch the voltage applied to the second plate of each storage capacitor from the fourth voltage to the second voltage.

In some embodiments, the switching of the voltage applied to the substrate and the voltage applied to the TCP may be implemented using the voltage switching circuit shown in fig. 6 or fig. 7, and specific implementations may refer to fig. 6 and fig. 7.

In step S808, after the storage capacitors of the respective storage cells are charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage and to switch the voltage applied to the second plate of the respective storage capacitors from the second voltage to the fourth voltage.

In some embodiments, after the storage capacitors of the respective storage cells are charged for a predetermined period of time, for example, after waiting for a preset number of command clocks, the voltage applied to the substrate may be switched from the first voltage to the third voltage by sending a second input signal to the input terminal of the voltage switching circuit, and the voltage applied to the second plate of the respective storage capacitors may be switched from the second voltage to the fourth voltage, i.e., the charging of the storage capacitors of the respective storage cells is stopped.

In step S810, a read operation is performed on each memory cell to perform a burn-in test on the dynamic random access memory.

In some embodiments, after the capacitor of the memory cell in the whole area is charged, i.e. written with "1", the memory cells are read for each bit line and word line, so as to perform burn-in test on the dynamic random access memory under the preset temperature stress, and the embodiment can refer to fig. 10.

Fig. 9 is a flow chart illustrating a writing background according to fig. 8. Referring to fig. 8, the operation of switching the voltage applied to the substrate from the third voltage to the first voltage and the voltage applied to the second plate of each storage capacitor from the fourth voltage in step S806 may be referred to as entering the design for testability (Entry Design For Test, entry DFT), and the operation of switching the voltage applied to the substrate from the first voltage to the third voltage and the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage in step S808 may be referred to as leaving the design for testability (Exit DFT). As shown in fig. 9, when writing the background by the method shown in fig. 8, the first voltage and the second voltage may be determined by the methods of S802 and S804, the design for testability is entered (S902), then the design for testability is left (S906) after waiting for the duration of n DES instructions (S904), then the storage capacitor charging area is changed (S908), and after the first voltage and the second voltage are determined by the methods of S802 and S804, the process returns to S902. And (3) finishing the background writing process after all the storage capacitors to be subjected to the aging test are charged (no changeable storage capacitor charging area exists) (S910).

Referring to fig. 1, when writing a background "1" to an array of X word line and Y bit line memory cells using the method of fig. 1, the required writing time is n×y×x DES instructions. The writing time of the method adopting the embodiment of the disclosure is Entry DFT+n DES instructions+exit DFT, and the total time of DFT Entry and Exit is not more than 10tCK, and the writing time is irrelevant to the row and column number of the memory cell array. Therefore, the time for writing the background "1" is shortened by (n×y×x) - (Entry dft+n+exit DFT), so that the test time can be greatly shortened.

Fig. 10 is a flow chart of a read operation according to the one shown in fig. 8. As shown in fig. 10, taking a memory cell connected to X word lines and Y bit lines as an example, the current word line is activated (S1002), and "1" is read on a bit line by bit line basis after the word line is activated (S1004), and n DES instructions are waited for when "1" is read (S1006), and then the current word line is precharged (S1008) after the Y bit lines are read in a traversing manner, and then the next word line is activated to traverse X word lines (S1009).

In the case that the fail bit is obtained by writing "1" by the method shown in fig. 1 and reading by the method shown in fig. 10, then writing "1" by the method shown in fig. 5 or fig. 8 and reading by the method shown in fig. 10, it can be verified whether the fail bit is caused by the defect of the wafer itself or by the Write operation abnormality. The methods provided by the embodiments of fig. 5 and 8 may also assist in verifying that Write operations are abnormal.

FIG. 11 is a block diagram illustrating a dynamic random access memory test device, according to an example embodiment. The apparatus shown in fig. 11 can be applied to a plurality of memory cells shown in fig. 3 and 4, for example.

Referring to fig. 11, an apparatus 110 provided by an embodiment of the present disclosure may include a control module 1102 and a test module 1104.

The control module 1102 is operable to charge the storage capacitor of each memory cell by applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each memory cell, the first voltage being higher than the second voltage.

The test module 1104 may be configured to perform a read operation on each memory cell after the storage capacitor of each memory cell is charged for a predetermined period of time to perform a burn-in test on the dynamic random access memory.

FIG. 12 is a block diagram of another dynamic random access memory test device, according to an example embodiment. The apparatus shown in fig. 12 can be applied to a plurality of memory cells shown in fig. 3 and 4, for example.

Referring to fig. 12, an apparatus 120 provided by an embodiment of the present disclosure may include a control module 1202, a test module 1204, and a determination module 1206.

The control module 1202 may be configured to charge the storage capacitance of each memory cell by applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitance of each memory cell, the first voltage being higher than the second voltage.

The control module 1202 may also be configured to: transmitting a first input signal to an input terminal of the voltage switching circuit to switch a voltage applied to the substrate from a third voltage to a first voltage and to switch a voltage applied to the second plate of each storage capacitor from a fourth voltage to a second voltage; wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

The control module 1202 may also be configured to: a first input signal is sent to a common input terminal of the first inverter and the second inverter to switch a voltage applied to the substrate from a third voltage to a first voltage through the first inverter, and to switch a voltage applied to the second plate of each storage capacitor from a fourth voltage to a second voltage through the second inverter.

The control module 1202 may also be configured to: after the storage capacitors of the respective storage cells are charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage and to switch the voltage applied to the second plate of the respective storage capacitors from the second voltage to the fourth voltage.

The control module 1202 may also be configured to: a second input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the first voltage to the third voltage through the first inverter and to switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.

The test module 1204 may be configured to perform a read operation on each memory cell after the storage capacitor of each memory cell is charged for a predetermined period of time, so as to perform a burn-in test on the dynamic random access memory.

The determination module 1206 may be configured to obtain a region size of the plurality of memory cells; a voltage difference between the first voltage and the second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.

Specific implementation of each module in the apparatus provided in the embodiments of the present disclosure may refer to the content in the foregoing method, which is not described herein again.

Fig. 13 shows a schematic structural diagram of an electronic device in an embodiment of the disclosure. It should be noted that the apparatus shown in fig. 13 is only an example of a computer system, and should not impose any limitation on the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 13, the apparatus 1300 includes a Central Processing Unit (CPU) 1301, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1302 or a program loaded from a storage section 1308 into a Random Access Memory (RAM) 1303. In the RAM 1303, various programs and data necessary for the operation of the apparatus 1300 are also stored. The CPU1301, ROM 1302, and RAM 1303 are connected to each other through a bus 1304. An input/output (I/O) interface 1305 is also connected to bus 1304.

The following components are connected to the I/O interface 1305: an input section 1306 including a keyboard, a mouse, and the like; an output portion 1307 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker, and the like; a storage portion 1308 including a hard disk or the like; and a communication section 1309 including a network interface card such as a LAN card, a modem, or the like. The communication section 1309 performs a communication process via a network such as the internet. The drive 1310 is also connected to the I/O interface 1305 as needed. Removable media 1311, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memory, and the like, is installed as needed on drive 1310 so that a computer program read therefrom is installed as needed into storage portion 1308.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such embodiments, the computer program may be downloaded and installed from a network via the communication portion 1309 and/or installed from the removable medium 1311. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU) 1301.

It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present disclosure may be implemented in software or hardware. The described modules may also be provided in a processor, for example, as: a processor includes a data control module and a test module. The names of these modules do not in any way constitute a limitation of the module itself, for example, a control module may also be described as "a module that sends control signals to the connected circuits".

As another aspect, the present disclosure also provides a computer-readable medium that may be contained in the apparatus described in the above embodiments; or may be present alone without being fitted into the device. The computer readable medium carries one or more programs which, when executed by a device, cause the device to include:

charging the storage capacitor of each memory cell by applying a first voltage to the substrate and a second voltage to the second plate of the storage capacitor of each memory cell, the first voltage being higher than the second voltage; after the storage capacitor of each storage unit is charged for a preset time, the storage unit is read to carry out aging test on the dynamic random access memory.

Exemplary embodiments of the present disclosure are specifically illustrated and described above. It is to be understood that this disclosure is not limited to the particular arrangements, instrumentalities and methods of implementation described herein; on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. The method for testing the dynamic random access memory is characterized in that the dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a storage capacitor and a first transistor, the first transistor is an NMOS transistor, a first polar plate of the storage capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, and a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate, and the method comprises the following steps:

Charging the storage capacitance of each memory cell by applying a first voltage to the substrate and a second voltage to a second plate of the storage capacitance of each memory cell, the first voltage being higher than the second voltage;

and after the storage capacitor of each storage unit is charged for a preset time, reading the storage units to perform aging test on the dynamic random access memory.

2. The method of claim 1, wherein applying a first voltage across the substrate and a second voltage across the second plate of each storage capacitor comprises:

transmitting a first input signal to an input terminal of a voltage switching circuit to switch a voltage applied to the substrate from a third voltage to the first voltage and to switch a voltage applied to a second plate of each storage capacitor from a fourth voltage to the second voltage;

wherein the third voltage is lower than the first voltage, the fourth voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

3. The method of claim 2, wherein the voltage switching circuit comprises a first inverter and a second inverter, an input of the first inverter being connected to an input of the second inverter;

Transmitting a first input signal to an input terminal of a voltage switching circuit to switch a voltage applied to the substrate from a third voltage to the first voltage and to switch a voltage applied to a second plate of each storage capacitor from a fourth voltage to the second voltage, comprising:

the first input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the third voltage to the first voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the fourth voltage to the second voltage through the second inverter.

4. The method of claim 2, wherein performing a read operation on each memory cell after a predetermined period of time has elapsed since the storage capacitor of the respective memory cell has been charged, comprises:

after the storage capacitors of the respective storage cells are charged for a predetermined period of time, a second input signal is sent to the input terminal of the voltage switching circuit to switch the voltage applied to the substrate from the first voltage to the third voltage and to switch the voltage applied to the second plate of the respective storage capacitors from the second voltage to the fourth voltage.

5. The method of claim 4, wherein the voltage switching circuit comprises a first inverter and a second inverter, the first inverter sharing an input with the second inverter;

transmitting a second input signal to an input terminal of the voltage switching circuit to switch a voltage applied to the substrate from the first voltage to the third voltage and to switch a voltage applied to a second plate of each storage capacitor from the second voltage to the fourth voltage, comprising:

the second input signal is sent to a common input terminal of the first inverter and the second inverter to switch the voltage applied to the substrate from the first voltage to the third voltage through the first inverter, and to switch the voltage applied to the second plate of each storage capacitor from the second voltage to the fourth voltage.

6. The method as recited in claim 1, further comprising:

obtaining the area sizes of the plurality of storage units;

a voltage difference between a first voltage and a second voltage is determined according to the area sizes of the plurality of memory cells to obtain the first voltage and the second voltage.

7. A dynamic random access memory test device, wherein the dynamic random access memory comprises a substrate and a plurality of memory cells, each memory cell comprises a storage capacitor and a first transistor, the first transistor is an NMOS transistor, a first plate of the storage capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, and a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate, the device comprising:

the control module is used for charging the storage capacitor of each storage unit by applying a first voltage on the substrate and applying a second voltage on the second polar plate of the storage capacitor of each storage unit, and the first voltage is higher than the second voltage;

and the test module is used for reading the storage units after the storage capacitors of the storage units are charged for a preset time so as to carry out aging test on the dynamic random access memory.

8. The dynamic random access memory testing device is characterized by comprising a dynamic random access memory to be tested and a voltage switching circuit, wherein:

the dynamic random access memory to be tested comprises a substrate and a plurality of memory cells, wherein each memory cell comprises a memory capacitor and a first transistor, the first transistor is an NMOS transistor, a first polar plate of the memory capacitor of each memory cell is electrically connected with a drain electrode of the corresponding first transistor, and a P-type silicon substrate of the first transistor of each memory cell is electrically connected with the substrate;

The voltage switching circuit comprises a first output end and a second output end, wherein the first output end of the voltage switching circuit is electrically connected with the substrate and used for applying a first voltage to the substrate, the second output end of the voltage switching circuit is electrically connected with the second polar plate of each storage capacitor and used for applying a second voltage to the second polar plate of each storage capacitor, and the first voltage is higher than the second voltage so as to charge the storage capacitor of each storage unit.

9. The apparatus of claim 8, wherein the voltage switching circuit comprises a first inverter and a second inverter, an input of the first inverter being connected to an input of the second inverter, an output of the first inverter being the first output, and an output of the second inverter being the second output.

10. The apparatus of claim 9, wherein the first inverter and the second inverter are CMOS transistors.

11. The apparatus of claim 10, wherein the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal, the input voltage of the source of the PMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the NMOS transistor of the first inverter is the third voltage;

The drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor of the second inverter are connected with the second output end, the input voltage of the source electrode of the PMOS transistor of the second inverter is the second voltage, the input voltage of the source electrode of the NMOS transistor of the second inverter is the fourth voltage, and the fourth voltage is higher than the third voltage;

the input end of the first inverter and the input end of the second inverter are used for receiving a first input signal so as to enable the PMOS transistor of the first inverter and the PMOS transistor of the second inverter to be conducted, and the NMOS transistor of the first inverter and the NMOS transistor of the second inverter to be cut off.

12. The apparatus of claim 11, wherein the input of the first inverter and the input of the second inverter are further configured to receive a second input signal to turn off the PMOS transistor of the first inverter and the PMOS transistor of the second inverter and to turn on the NMOS transistor of the first inverter and the NMOS transistor of the second inverter.

13. The apparatus of claim 10, wherein the drain of the NMOS transistor and the drain of the PMOS transistor of the first inverter are connected to the first output terminal, the input voltage of the source of the NMOS transistor of the first inverter is the first voltage, and the input voltage of the source of the PMOS transistor of the first inverter is the third voltage;

The drain electrode of the NMOS transistor and the drain electrode of the PMOS transistor of the second inverter are connected with the second output end, the input voltage of the source electrode of the NMOS transistor of the second inverter is the second voltage, the input voltage of the source electrode of the PMOS transistor of the second inverter is the fourth voltage, and the fourth voltage is higher than the third voltage;

the input end of the first inverter and the input end of the second inverter are used for receiving a first input signal so as to enable the NMOS transistor of the first inverter and the NMOS transistor of the second inverter to be conducted, and the PMOS transistor of the first inverter and the PMOS transistor of the second inverter to be cut off.

14. The apparatus of claim 13, wherein the input of the first inverter and the input of the second inverter are further configured to receive a second input signal to turn off the NMOS transistor of the first inverter and the NMOS transistor of the second inverter and to turn on the PMOS transistor of the first inverter and the PMOS transistor of the second inverter.

15. The apparatus of claim 8, wherein the first output of the voltage switching circuit is electrically connected to the substrate through a connection plug.