CN117809710A - DDR training system, training method and medium based on instruction set control - Google Patents

Abstract

The invention provides a DDR training system based on instruction set control, a training method and a medium, wherein the training system uses a plurality of continuous write commands to expand WDQS signals, and the operation is flexible and simple, and comprises the following steps: the DDR training control module comprises a command generation sub-module, a chip selection processing sub-module, a first whole UI delay sub-module, a second whole UI delay sub-module and a delay control logic sub-module; the command generation sub-module is used for sending a write command and a read command to the DDR particles; the chip selection processing sub-module selects one chip selection signal from a plurality of chip selection signals in the writing delay training process, so that DDR particles can recognize writing commands; the data detection submodule is used for detecting and judging the read-back data; and the delay control logic submodule is used for adjusting the number of standard delay units passing through in the WDQS and WDQ transmission processes according to the detection result of the read-back data in the training process until the read-back data is consistent with the transmitted data and the training is finished.

Description

DDR training system, training method and medium based on instruction set control

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a DDR training system, a training method and a medium based on instruction set control.

Background

The Double Data Rate (DDR) system is a habitual abbreviation of Double Data Rate synchronous dynamic random access memory system, and has the advantages of large storage capacity, low cost, mature interface and higher access Rate in parallel burst access. The DDR external signal interface mainly comprises: clock signals, data signals, strobe signals, and command/address signals.

To perform normal DDR write functions, it is necessary to ensure that the rising edge of the WDQS received by the DDR particles is aligned with the rising edge of clock CK_t, and to ensure that the WDQS is received again at regular write latency intervals after the DDR particles receive a write command. According to the description of the DDR standard document, the former can be realized through write balance training, but the write balance training cannot ensure that the time interval of the particle receiving the command and the WDQS meets the write delay requirement. Thus, after the write equalization training is completed, write latency training is required to ensure that the latency between the write command to the WDQS meets the requirements. In general, the basic training process for conventional write latency is as follows: the delay position of WDQS is set first, then write command is sent to a certain address of DDR granule, then WDQS and WDQ are sent, then data are read back, whether the read-back code pattern is consistent with the sent code pattern is judged, if not, the delay position of WDQS is adjusted, and the process is repeated. Considering that DDR particles may have stored the same data as the transmit pattern at the address prior to training, to avoid training failure due to this special case, a special write operation is typically sent to the address before sending the normal write command, and the data at the address is rewritten to all 1's. The WDQ for this write operation is all 1's and the WDQS needs to be extended to ensure that the WDQ is correctly written. It is currently common practice to directly extend the WDQS signal of a write command and simultaneously extend the output/input enable signal of the corresponding signal. This requires additional special control of the WDQS and enable signals, which is complex and inflexible.

Disclosure of Invention

The invention aims to provide a DDR training system, a training method and a medium based on instruction set control, which use a plurality of continuous write commands to extend WDQS signals, and are flexible and simple to operate.

In a first aspect, the present invention provides a DDR training system based on instruction set control, comprising: the DDR training control module comprises a command generation sub-module, a chip selection processing sub-module, a first whole UI delay sub-module, a second whole UI delay sub-module and a delay control logic sub-module; the IO module is provided with a first delay sub-module and a second delay sub-module data detection sub-module; the command generation sub-module is used for generating a write command and a read command of DDR particles, and generating a corresponding WDQS signal and a corresponding WDQ signal according to the write command; the chip selection processing sub-module is used for selecting one chip selection signal from a plurality of chip selection signals in the writing delay training process so as to enable DDR particles to recognize writing commands; the first whole UI delay module is used for completing coarse granularity delay processing of at least one whole UI for the WDQS signal through digital logic; the second whole UI delay module is used for finishing coarse granularity delay processing of at least one whole UI on the WDQ signal through digital logic; the first delay submodule is used for carrying out fine granularity delay processing on the WDQS signal after the coarse delay processing; the second delay sub-module is used for carrying out fine granularity delay processing on the WDQ signal after the coarse delay processing; the data detection sub-module is used for detecting and judging the read data; and the delay control logic sub-module is used for adjusting the number of the standard delay units passing through in the WDQS and WDQ transmission process according to the detection result of the read-back data in the training process so as to enable the WDQ to continuously change relative to the WDQS.

In a possible embodiment, the first delay sub-module and the second delay sub-module each include an SDL and a CDL, where the SDL is a standard delay unit with a fixed delay function composed of a combinational logic cascade, and the CDL is a standard delay unit with a fixed delay function composed of an analog circuit. Optionally, the first delay sub-module and the second delay sub-module are each composed of 96 stages of SDL and 4 stages of CDL in series.

In another possible embodiment, the data detection submodule detects data, and is specifically configured to: judging whether the write data is correctly written into DDR particles according to whether the read-back data and the write data are equal or not for the position of each WDQ; when the read data is consistent with the write data, it indicates that the current WDQS setting meets the write latency requirement, otherwise, it does not.

In other possible embodiments, for a DDR system in which the deviation of the WDQS signal from the WDQ signal is relatively large, the interval from the start position to the end position of the WDQ signal is set to be a first interval, and for a DDR system in which the deviation of the WDQS signal from the WDQ signal is relatively small, the interval from the start position to the end position of the WDQ signal is set to be a second interval, and the first interval is greater than or equal to the second interval.

In one possible embodiment, the lower the DDR training system frequency, the greater the number of standard delay cells per delay increase that the WDQ can set.

In another possible embodiment, the DDR training system is applied to an FPGA platform, or to the integrated circuit system and SOC of the DDR granule.

In a second aspect, the present invention provides a DDR write latency training method based on an instruction set, applied to the DDR training system according to the first aspect, including:

s1, setting an initial position of a WDQS signal and finishing writing equalization training;

s2, based on a result of write equalization training, performing delay processing on WDQS signals through the first whole UI delay module and the first delay sub-module;

s3, setting an initial position of WDQ according to the delay setting of WDQS;

s4, writing a background value into a target address of the DDR particle before sending a write command; the process generates a plurality of continuous write commands through an instruction control command generation submodule, wherein the write commands are used for generating corresponding WDQS signals and WDQ signals so as to expand the WDQS signals; selecting one chip selection signal from a plurality of chip selection signals through a chip selection processing sub-module for DDR particles to recognize the write command;

s5, aiming at the position of each WDQS signal, carrying out delay processing on the WDQ signal through the second whole UI delay module and the second delay sub-module so as to enable the WDQ to continuously change relative to the WDQS position;

s6, generating a write command through a command generation submodule and sending the write command to the DDR particles;

s7, sending a read command to the target address through a command generation sub-module;

and S8, the data detection sub-module detects the read data, and when judging that the read-back data is inconsistent with the transmitted data, the method returns to S5, continues to delay the WDQ signal for writing equalization training, and repeats the process until the read-back data is consistent with the transmitted data and the training is finished or the WDQ delay reaches a set end point.

And S9, if the WDQ reaches the set end point and the training is not finished, returning to S2, continuing to delay the WDQS signal for writing the equalization training, and repeating the process until the read-back data is consistent with the transmitted data or the WDQS delay reaches the set end point to finish the training.

In a possible embodiment, when the read command is sent to the target address by the command generating sub-module after the WDQ signal is delayed, the method further includes: generating a plurality of continuous write commands through an instruction control command generation submodule; the chip select processing sub-module selects one chip select signal from a plurality of chip select signals for the DDR particles to recognize the write command.

In a third aspect, embodiments of the present application further provide a computer readable storage medium, which includes a computer program, which when run on an electronic device causes the electronic device to perform the method of any one of the possible designs of the first aspect.

In a fourth aspect, embodiments of the present application also provide a method comprising a computer program product, which when run on an electronic device, causes the electronic device to perform any one of the possible designs of the first aspect described above.

The DDR training system, the training method and the medium based on instruction set control have the beneficial effects that: aiming at the characteristics of multiple types of DDR particles and multiple systems, the method provided by the embodiment designs a DDR training system based on instruction set control based on the FPGA, and the system can complete the functions of particle initialization, basic read-write, delay control and the like through the combination of instructions. The logic module can be built by using programmable logic of an FPGA, and can also be integrated on various SOCs using DDR systems. In addition, the system provided by the embodiment provides a manner of expanding WDQS by using a plurality of continuous write commands according to a delay difference between a write command address signal and a WDQS signal, and can send any continuous write command which is the same as a conventional write command, and only redundant chip select signals are required to be covered in control logic, so that the system is flexible and simple to operate.

In the training method provided in this embodiment, in the process of moving the WDQ, delay control may be performed on the WDQ by the standard delay unit SDL, so that the number of delay increases of the WDQ each time may be determined according to the system frequency. For low frequency systems, the delay of multiple SDLs may be increased at a time. In addition, the starting and ending positions of WDQ scanning can be adjusted according to the estimated WDQS and WDQ offset, and the write delay training time can be greatly shortened. In addition, the system which is insensitive to training time or can not estimate the relative offset of the WDQS and the WDQ can directly set the starting position and the ending position of the WDQ to be the maximum range, and the setting can meet all system requirements. The control process is controlled by the information carried by the instruction, so that the system is convenient to debug and flexible to control.

Drawings

FIG. 1 is a block diagram of a DDR training system based on instruction set control provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a DDR gating signal training method based on instruction set provided by the invention;

FIG. 3 is a schematic diagram of another instruction set-based DDR gating signal training method according to the present invention;

FIG. 4 is a schematic waveform diagram showing alignment of WDQS and CK at the grain end for performing write equalization training in accordance with the present invention;

FIG. 5 is a schematic diagram of waveforms of WDQS and CK delayed by 1tCK in accordance with the present invention;

FIG. 6 is a schematic waveform representation of an extended WDQS signal provided by the present invention;

FIG. 7 is a schematic waveform diagram of WDQ versus WDQS position provided by the present invention;

FIG. 8 is a waveform schematic diagram of the correspondence between WDQ and WDQS of different particles provided by the present invention.

Detailed Description

The terms referred to herein are explained first:

DDR: double Data Rate.

DDR particles: DDR SDRAM, synchronous dynamic random access memory with double data transmission rate.

DQ: data, bidirectional data signal lines of DDR particles.

DQS (DQS): the data strobe corresponds to a reference clock of the data signal and is used for sampling the data signal line.

WDQS: write data strobe for sampling the data signal lines in the write direction, includes a pair of differential signals WDQS_t and WDQS_c.

CK: clock, DDR granule clock signal, includes a pair of differential clocks CK_t and CK_c.

SDL: standard Cell Delay Line a standard delay cell with a fixed delay function consisting of a combinatorial logic cascade.

CDL: customer delay line, a custom standard delay cell consisting of analog circuitry.

WRITE LEVELING: write equalization is a DDR particle training process that is used to align the rising edge of WDQS_t received by the DDR particle with the rising edge of CK_t.

Skuw: different signals may have signal offset at the receiving end due to wiring problems, etc., so that the signals may not be perfectly aligned.

tCK: DDR clock cycle.

UI: one half of the DDR clock period.

WRITE LATENCY: write latency, DDR particles, after receiving a write command, need to go through a fixed number of clock signal (CK_t) latency times, which is the write latency, to accept WDQS.

CS: one of the Chip select, and DDR granule standard interface signals belongs to one of the command signals.

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In order to solve the problems set forth in the background art, the present application provides a DDR training system based on instruction set control, and fig. 1 is a frame diagram of the DDR training system based on instruction set control provided in the embodiment of the present application. The system can be realized based on FPGA, comprising: DDR training control module 10 and IO module 20, IO module 20 is connected to DDR particles 30, the types of DDR particles including, but not limited to, DDR3, DDR4, DDR5, or LPDDR. Wherein: the DDR training control module 10 comprises a command generation sub-module 101, a chip selection processing sub-module 102, a first whole UI delay sub-module 103, a second whole UI delay sub-module 104 and a delay control logic sub-module 105; the IO module 20 is provided with a first delay sub-module 201, a second delay sub-module 202 and a data detection sub-module 203.

The command generation sub-module 101 is configured to generate a write command and a read command of the DDR granule, send the write command and the read command to the DDR granule, and generate a corresponding WDQS signal and a WDQ signal according to the write command;

the chip selection processing sub-module 102 is configured to select one chip selection signal from a plurality of chip selection signals in the write delay training process, for the DDR granule to recognize a write command, and mask the remaining chip selection signals;

a first full UI delay module 103 for performing coarse granularity delay processing of at least one full UI on the WDQS signal by digital logic;

a second whole UI delay module 104, configured to perform coarse granularity delay processing of at least one whole UI on the WDQ signal through digital logic. In this embodiment, 2 UIs are 1tCK, and the first whole UI delay module 103 and the second whole UI delay module 104 complete delay processing mainly through digital logic, and the minimum unit is 1UI.

The first delay sub-module 201 is configured to perform fine granularity delay processing on the WDQS signal after the coarse delay processing;

the second delay sub-module 202 is configured to perform fine granularity delay processing on the WDQ signal after the coarse delay processing;

the data detection sub-module 203 is configured to detect and determine the read-back data. Specifically, one possible detection method may be: judging whether the write data is correctly written into DDR particles according to whether the read-back data and the write data are equal or not for the position of each WDQ; when the read data is consistent with the write data, it indicates that the current WDQS setting meets the write latency requirement, otherwise, it does not.

The delay control logic sub-module 105 is configured to adjust the number of standard delay units passing through the WDQS and the WDQ transmission process according to the detection result of the readback data during the training process, so that the WDQ position relative to the WDQS is continuously changed.

In a possible embodiment, the first delay sub-module 201 and the second delay sub-module 202 each include an SDL and a CDL, where the SDL is a standard delay unit with a fixed delay function formed by a combinational logic cascade, and the CDL is a standard delay unit with a fixed delay function formed by an analog circuit. Optionally, in this embodiment, the first delay sub-module 201 and the second delay sub-module 202 are each formed by serially connecting 96 stages of SDL and 4 stages of CDL. In this embodiment, the delay time of each CDL is about 5ps, the delay time of the serial connection of 4 CDLs is about equal to the delay time of 1 SDL, and when the delay time of the CDL reaches 4 stages, one SDL is added and the value of the CDL is cleared. In the writing delay training process, the requirement on delay precision is low, and CDL4 is not needed.

Based on the training system, the embodiment of the invention also provides a DDR write delay training method based on an instruction set, as shown in fig. 2, comprising the following steps:

s1, setting an initial position of a WDQS signal and finishing writing equalization training;

s2, based on a result of write equalization training, performing delay processing on WDQS signals through the first whole UI delay module and the first delay sub-module;

s3, setting an initial position of WDQ according to the delay setting of WDQS;

s4, writing a background value into a target address of the DDR particle before sending a write command; in the process, a write command is generated by an instruction control command generation submodule and a plurality of continuous write commands are sent to the DDR particles, wherein the write commands are used for generating corresponding WDQS signals and WDQ signals so as to expand the WDQS signals; selecting one chip selection signal from a plurality of chip selection signals through a chip selection processing sub-module for DDR particles to recognize the write command;

s5, aiming at the position of each WDQS signal, carrying out delay processing on the WDQ signal through the second whole UI delay module and the second delay sub-module so as to enable the WDQ to continuously change relative to the WDQS position;

s6, generating a write command through a command generation submodule and sending the write command to the DDR particles;

s7, sending a read command to the target address through a command generation sub-module;

s8, the data detection sub-module detects the read data, and when judging that the read-back data is inconsistent with the transmitted data, the step S5 is returned, the WDQ signal of the write equalization training is continuously delayed, the process is repeated until the read-back data is consistent with the transmitted data, the training is ended, or the WDQ delay reaches a set end point;

and S9, if the WDQ reaches the set end point and the training is not finished, returning to S2, continuing to delay the WDQS signal for writing the equalization training, and repeating the process until the read-back data is consistent with the transmitted data or the WDQS delay reaches the set end point to finish the training.

In one possible embodiment, the step S6 specifically includes: the command generation sub-module is controlled by an instruction to generate a plurality of continuous write commands again and send the plurality of continuous write commands to the DDR particles; the chip select processing sub-module selects one chip select signal from a plurality of chip select signals for the DDR particles to recognize the write command. It will be appreciated that each time a background value or write command is written, the WDQS signal may be extended by sending multiple write commands and a chip select signal selected from the multiple chip select signals by the chip select processing sub-module, which facilitates accurate writing of data.

The method is illustrated below in conjunction with the method flowchart shown in fig. 3, and includes the following steps:

step a, setting an initial position of a WDQS signal.

And b, according to DDR standard document description, completing a write equalization training process by moving an SDL standard delay unit of WDQS. WDQS and CK that complete the write equalization training are aligned at the grain end, and exemplary correspondence is shown in FIG. 4:

step c, after the write equalization training is completed, updating the delay position of the WDQS, that is, performing delay processing on the WDQS signal through the first full UI delay module and the first delay sub-module, for example, as shown in fig. 5, because the write delay is an integer multiple of the tCK delay, each time the delay of the WDQS is adjusted, the delay is pushed back by 1tCK.

Step d, writing all 1 background values for DDR particles.

Because the correct position of the WDQS is not known before the write delay training is performed, the WDQS needs to be extended in order to ensure that the full 1 background value can be correctly written to the grain. Compared with the traditional mode, the method provided by the embodiment can continuously send a plurality of basic writing operations, and the WDQS is expanded through processing a chip select signal (CS). The process is simple in processing, only needs to process the chip selection signal, and the expansion length of WDQS can be determined by controlling the number of continuous write commands through instructions, so that the expansion capacity is large, the operation is flexible, and the applicability is stronger. Taking fig. 6 as an example, this example illustrates the manner of operation for the WDQS to extend 4tCK forward and 4tCK backward. The process generates 3 consecutive chip select signals, the first and last of which do not need to be sent to the particles, which are masked by the chip select processing module, in such a way that the WDQS expansion is completed.

Step e, for each WDQS position, adjusting the SDL delay setting of the WDQ to continuously change the WDQ relative to the WDQS position.

Illustratively, as shown in FIG. 7, the distance that WDQ moves backward each time is in SDL number. For DDR systems with larger WDQS and WDQ offset (SKEW) and larger difference between different inter-particle offset (SKEW), the same initial delay value is set for WDQ, and the corresponding relationship between WDQ and WDQS among different particles is also larger. Taking fig. 8 as an example, the initial positions of the same delay are set for two pellets WDQ above the dashed line box, and at this time, pellet 1 can correctly acquire DQ0, but pellet 0 cannot acquire correct DQ0. To ensure that particle 0 will find the correct position when WDQS is in the correct position, a suitable termination position needs to be set so that particle 0 will be sampled correctly before the termination position. Therefore, for a DDR system in which the deviation of the WDQS signal from the WDQ signal is relatively large, the section from the start position to the end position of the WDQ signal is set to be a first section, and for a DDR system in which the deviation of the WDQS signal from the WDQ signal is relatively small, the section from the start position to the end position of the WDQ signal is set to be a second section, and the first section is larger than or equal to the second section. In addition, when the frequency is relatively low, the distance of DQ per movement may be set to be relatively large, and the larger the number of standard delay units per delay increase the WDQ may set, the number of movements of the WDQ from the initial position to the final position may be reduced to shorten the training time. Because the method completes the training process based on the instruction set, the settings come from the information carried in the instructions, and the adjustment can be quickly and flexibly carried out for different systems and requirements. It will be appreciated that the process of sending the write command and the read command shown in steps e-h will be performed for each WDQ location, and whether the write data is correctly written into the granule will be determined based on whether the read-back data is equal to the write data.

Step f-step h) after the DQ delay is adjusted, a write command and a read command are required to be sent to the DDR particles, and the data is judged. If the delay of the current WDQS is not satisfactory, the data will not be written correctly, the data in the DDR particles will be a combination of a portion of the write data and the write background value, and the read data will fail to compare with the written data. If the WDQS write delay time meets the requirements, the DQ position of the grain can be correctly written in the write data in the WDQ moving process, and the read data is identical to the write data at the moment, so that the read data is successfully compared. By judging whether a small range exists in the whole WDQ moving process, the writing data can be stably and correctly written, so that whether the current WDQS setting is correct or not is judged.

Step i) when the WDQ moves from the initial delay position to the end position, and no range for stably and correctly writing data exists, the current WDQS position is considered to not meet the writing delay requirement, and the delay of the WDQS needs to be increased by 1tCK, so that the training process is continued.

Step g-step k if the current WDQS has not reached the set endpoint, then the WDQS set is incremented and the process of steps 2-10 is repeated. When the WDQS setting has reached the end point, the read-back data is inconsistent with the transmitted data, the training is ended, the WDQS setting is considered to not meet the write delay requirement, at the moment, the training is considered to be failed, and the phenomenon is generally caused only when the SKEW of the WDQS and the WDQ in the system is too large to exceed the tolerance upper limit, and the training is marked to be failed.

And step l-step m, when the read data are consistent with the write data, indicating that the current WDQS position meets the write delay requirement, delaying the training success, ending the training process, and recording the current WDQS position as a final training result.

As can be seen from the above discussion, according to the characteristics of multiple types of DDR particles and multiple systems, the method provided in this embodiment can design a DDR training system based on instruction set control based on FPGA, and the system can complete the functions of particle initialization, basic read-write, delay control, and the like through the combination of instructions. The logic module can be built by using programmable logic of an FPGA, and can also be integrated on various SOCs using DDR systems. In addition, the method provided by the embodiment provides a method for expanding WDQS by using a plurality of continuous write commands according to the delay difference between the address signal of the write command and the WDQS signal, and can send any continuous write command which is the same as the conventional write command, and only redundant chip select signals are required to be covered in the control logic, so that the method is flexible and simple to operate.

In the method provided in this embodiment, during the process of moving the WDQ, delay control may be performed on the WDQ by the standard delay unit SDL, so that the number of delay increases of the WDQ each time may be determined according to the system frequency. For low frequency systems, the delay of multiple SDLs may be increased at a time. In addition, the starting and ending positions of WDQ scanning can be adjusted according to the estimated WDQS and WDQ offset, and the write delay training time can be greatly shortened. In addition, the system which is insensitive to training time or can not estimate the relative offset of the WDQS and the WDQ can directly set the starting position and the ending position of the WDQ to be the maximum range, and the setting can meet all system requirements. The control process is controlled by the information carried by the instruction, so that the system is convenient to debug and flexible to control.

The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a computer implements the method of the above-described method embodiments.

The invention also provides a computer program product which, when executed by a computer, implements the method of the above-described method embodiments.

While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (10)

1. The DDR training system based on instruction set control is characterized by comprising a DDR training control module and an IO module, wherein the IO module is connected to external DDR particles, and the DDR training control module comprises a command generation sub-module, a chip selection processing sub-module, a first whole UI delay sub-module, a second whole UI delay sub-module and a delay control logic sub-module; the IO module is provided with a first delay submodule, a second delay submodule and a data detection submodule;

the command generation sub-module is used for generating a write command and a read command of the DDR grain, sending the write command and the read command to the DDR grain, and generating a corresponding WDQS signal and a corresponding WDQ signal according to the write command;

the chip selection processing sub-module is used for selecting one chip selection signal from a plurality of chip selection signals in the writing delay training process, so that DDR particles can recognize writing commands, and masking other chip selection signals;

the first whole UI delay module is used for completing coarse granularity delay processing of at least one whole UI for the WDQS signal through digital logic;

the second whole UI delay module is used for finishing coarse granularity delay processing of at least one whole UI on the WDQ signal through digital logic;

the first delay submodule is used for carrying out fine granularity delay processing on the WDQS signal after the coarse delay processing;

the second delay sub-module is used for carrying out fine granularity delay processing on the WDQ signal after the coarse delay processing;

the data detection sub-module is used for detecting and judging the read-back data;

and the delay control logic sub-module is used for adjusting the number of the standard delay units passing through in the WDQS and WDQ transmission process according to the detection result of the read-back data in the training process so as to enable the WDQ to continuously change relative to the WDQS.

2. The DDR training system of claim 1, wherein the first delay sub-module and the second delay sub-module each comprise an SDL and a CDL, wherein the SDL is a standard delay unit with a fixed delay function composed of a combinatorial logic cascade and the CDL is a standard delay unit with a fixed delay function composed of an analog circuit.

3. The DDR training system of claim 2, wherein the first delay sub-module and the second delay sub-module are each comprised of 96 stages SDL and 4 stages CDL in series.

4. The DDR training system of claim 2, wherein the data detection submodule detects data, in particular for:

judging whether the write data is correctly written into DDR particles according to whether the read-back data and the write data are equal or not for the position of each WDQ;

when the read data is consistent with the write data, it indicates that the current WDQS setting meets the write latency requirement, otherwise, it does not.

5. The DDR training system according to any one of claims 1 to 4, wherein for a DDR system in which a deviation of the WDQS signal from the WDQ signal is relatively large, a section from a start position to an end position of the WDQ signal is set to be a first section, and for a DDR system in which a deviation of the WDQS signal from the WDQ signal is relatively small, a section from a start position to an end position of the WDQ signal is set to be a second section, the first section being greater than or equal to the second section.

6. The DDR training system of any of claims 1-4, wherein the lower the DDR training system frequency, the greater the number of standard delay cells per delay increase the WDQ can set.

7. The DDR training system of any of claims 1 to 4, wherein the DDR training system is applied to an FPGA platform, or to integrated circuit systems and SOCs of DDR particles.

8. A DDR write latency training method based on instruction set, applied to the DDR training system according to any one of claims 1 to 5, comprising:

s1, setting an initial position of a WDQS signal and finishing writing equalization training;

s2, based on a result of write equalization training, performing delay processing on WDQS signals through the first whole UI delay module and the first delay sub-module;

s3, setting an initial position of WDQ according to the delay setting of WDQS;

s4, writing a background value into a target address of the DDR particle before sending a write command; in the process, a write command is generated by an instruction control command generation submodule and a plurality of continuous write commands are sent to the DDR particles, wherein the write commands are used for generating corresponding WDQS signals and WDQ signals so as to expand the WDQS signals; selecting one chip selection signal from a plurality of chip selection signals through a chip selection processing sub-module for DDR particles to recognize the write command;

s5, aiming at the position of each WDQS signal, carrying out delay processing on the WDQ signal through the second whole UI delay module and the second delay sub-module so as to enable the WDQ to continuously change relative to the WDQS position;

s6, generating a write command through a command generation submodule and sending the write command to the DDR particles;

s7, sending a read command to the target address through a command generation sub-module;

s8, the data detection sub-module detects the read data, and when judging that the read-back data is inconsistent with the transmitted data, the step S5 is returned, the WDQ signal of the write equalization training is continuously delayed, the process is repeated until the read-back data is consistent with the transmitted data, the training is ended, or the WDQ delay reaches a set end point;

and S9, if the WDQ reaches the set end point and the training is not finished, returning to S2, continuing to delay the WDQS signal for writing the equalization training, and repeating the process until the read-back data is consistent with the transmitted data or the WDQS delay reaches the set end point to finish the training.

9. The method of claim 8, wherein S6, generating a write command by a command generation submodule and sending the write command to the DDR granule, comprises:

the command generation sub-module is controlled by an instruction to generate a plurality of continuous write commands again and send the plurality of continuous write commands to the DDR particles;

the chip select processing sub-module selects one chip select signal from a plurality of chip select signals for the DDR particles to recognize the write command.

10. A computer readable storage medium having a computer program stored therein, characterized in that the computer program, when executed by a processor, implements the method of any of claims 8 to 9.