CN117807011A

CN117807011A - Information processing method, device, equipment and storage medium

Info

Publication number: CN117807011A
Application number: CN202311820183.7A
Authority: CN
Inventors: 施楠; 吕骏华; 祝红彬; 高昌垒
Original assignee: STMicroelectronics Shenzhen R&D Co Ltd
Current assignee: STMicroelectronics Shenzhen R&D Co Ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-04-02

Abstract

According to the information processing method, the information processing device, the information processing equipment and the storage medium, under the condition that the command descriptor is obtained from the host, the command descriptor is analyzed, and analysis information is obtained; under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, sending a read data request to the radio equipment to obtain packet switched interconnection (SRIO) response information of the radio equipment, and sending a high-speed serial computer expansion bus standard (PCIe) write command to the host based on the SRIO response information to write data into a host memory space; and under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information, sending a PCIe read command to the host to read CPLD data from the host, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device, so that data movement between the host and the radio device can be realized.

Description

Information processing method, device, equipment and storage medium

Technical Field

The application belongs to the technical field of information processing, and particularly relates to an information processing method, an information processing device, information processing equipment and a storage medium.

Background

PCIe is a widely used high-speed interface, which has strong compatibility and plasticity in application scenarios, and Rpidio, which is also a high-speed interface, performs particularly inauguration in peer-to-peer device communication transmission, but Rpidio does not define a standard software model, which results in a large probability that devices among manufacturers cannot be compatible, so that in order to achieve compatibility, a host system is generally used to schedule communication of each Rpidio device, but the Rpidio device cannot directly interact with a host, so that data movement between the Rpidio device and the host cannot be achieved, and therefore, a method is needed to achieve data movement between the Rpidio device and the host system.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide an information processing method, apparatus, device, and storage medium, which can implement high-speed and flexible data movement between an Rpidio device and a host system.

The embodiment of the application provides an information processing method, which comprises the following steps:

under the condition that a command descriptor is acquired from a host, analyzing the command descriptor to obtain analysis information;

under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, sending a read data request to the radio equipment to obtain SRIO response information of the radio equipment, and sending a PCIe write command to the host based on the SRIO response information to write data into the memory space of the host;

And under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information, sending a PCIe read command to the host to read CPLD data from the host, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device.

An embodiment of the present application provides an information processing apparatus including:

the analysis module is used for analyzing the command descriptor to obtain analysis information under the condition that the command descriptor is acquired from the host;

the first processing module is used for sending a read data request to the radio equipment to obtain SRIO response information of the radio equipment under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, and sending a standard PCIe write command to the host computer based on the SRIO response information to write data into the memory space of the host computer;

and the second processing module is used for sending a PCIe read command to the host to read CPLD data from the host under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device.

An embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method of any one of the above when executing the computer program.

Embodiments of the present application provide a computer readable storage medium storing a computer program which, when executed by a processor, implements a method as described in any one of the above.

Embodiments of the present application provide a computer program product for causing an electronic device to perform any one of the methods described above when the computer program product is run on a terminal device.

According to the information processing method, the information processing device, the information processing equipment and the storage medium, under the condition that the command descriptor is obtained from the host, the command descriptor is analyzed, and analysis information is obtained; under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, sending a read data request to the radio equipment to obtain packet switched interconnection (SRIO) response information of the radio equipment, and sending a high-speed serial computer expansion bus standard (PCIe) write command to the host based on the SRIO response information to write data into a host memory space; and under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information, sending a PCIe read command to the host to read CPLD data from the host, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device, so that high-speed and flexible data movement between the host and the radio device can be realized.

Drawings

The present application will be described in more detail hereinafter based on embodiments and with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a connection structure of an information processing system according to an embodiment of the present application;

fig. 2 is a schematic implementation flow chart of an information processing method according to the embodiment of the present application;

FIG. 3 is a schematic diagram of a data structure of a read request transmission according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a data structure of a write request transmission according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a data structure of a maintenance request according to an embodiment of the present application;

fig. 6 is a schematic diagram of a data structure of a reply packet according to an embodiment of the present application;

fig. 7 is a schematic diagram of a descriptor obtaining flow provided in an embodiment of the present application;

fig. 8 is a schematic diagram of a data transmission descriptor according to an embodiment of the present application;

fig. 9 is a schematic diagram of a direct data transmission descriptor according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating a jump of a block pointer descriptor to another memory space according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a format of a block pointer descriptor according to an embodiment of the present application;

FIG. 12 is a schematic diagram of linear addressing provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of a loopback address transfer according to an embodiment of the present application;

fig. 14 is a schematic diagram of a step address transmission manner according to an embodiment of the present application;

FIG. 15 is a diagram illustrating a definition of a read command size according to an embodiment of the present application;

FIG. 16 is a diagram illustrating a definition of a read command size according to an embodiment of the present application;

FIG. 17 is a diagram illustrating a definition of a write command size according to an embodiment of the present application;

FIG. 18 is a diagram illustrating a definition of a write command size according to an embodiment of the present application;

fig. 19 is a schematic diagram of a streaming transmission according to an embodiment of the present application;

fig. 20 is a schematic diagram of performing appropriate conversion according to a bit width of an AXI interface according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a read command processing flow according to an embodiment of the present disclosure;

FIG. 22 is a schematic diagram illustrating a flow of implementing a write command according to an embodiment of the present application;

FIG. 23 is a diagram illustrating a descriptor status update data format according to an embodiment of the present application;

FIG. 24 is a schematic diagram of a descriptor update flow provided in an embodiment of the present application;

fig. 25 is a schematic structural diagram of an information processing apparatus according to an embodiment of the present application;

Fig. 26 is a schematic diagram of a composition structure of an electronic device according to an embodiment of the present application.

In the drawings, like parts are given like reference numerals, and the drawings are not drawn to scale.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first\second\third" appears in the application document, the following description is added, in which the terms "first\second\third" are merely distinguishing between similar objects and do not represent a particular ordering of the objects, it being understood that the "first\second\third" may be interchanged in a particular order or precedence, where allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

Based on the problems existing in the related art, the embodiment of the application provides an information processing method, which can be applied to electronic devices such as a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (personal digital assistant, PDA) and the like, and the embodiment of the application does not limit the specific types of the electronic devices. The functions implemented by the information processing method provided in the embodiments of the present application may be implemented by invoking program codes by a processor of an electronic device, where the program codes may be stored in a computer storage medium.

Fig. 1 is a schematic diagram of a connection structure of an information processing system according to an embodiment of the present application, where, as shown in fig. 1, the information processing system includes: an electronic device may be considered as a protocol conversion device, for example, a Block DMA Engine (BDMA), where one end of the electronic device is connected to a PCIe interface, and the other end of the electronic device is connected to an SRIO interface, and a BDMA Engine is taken as an example for the electronic device.

In the embodiment of the application, the BDMA engine can simultaneously perform command sending and receiving operations to the PCIe interface and the SRIO interface.

In the embodiment of the application, the BDMA engine provides a high-performance data moving method, and mainly realizes all types of read-write operation conversion (the BDMA engine does not process message commands). The operation trigger window of the BDMA is only provided to the host, i.e. only the host can trigger the BDMA to execute the read-write command. Inside the BDMA engine are a plurality of independently operated DMA channels, each of which has a function of acquiring a transfer command from a host, and can execute a plurality of commands at the same time. Complex data transfer mechanisms can be implemented by connecting different command linked lists while providing flexible memory handling schemes.

An embodiment of the present application provides an information processing method, and fig. 2 is a schematic implementation flow diagram of the information processing method provided by the embodiment of the present application, where, as shown in fig. 2, the method includes:

step S101, when a command descriptor is acquired from a host, the command descriptor is parsed to obtain parsing information.

In the embodiment of the application, the BDMA engine is provided with 8 DMA channels which independently run, each channel can realize data movement, and conversion and execution of various SRIO protocol packets can be realized. The DMA channel performs the translation from PCIe to SRIO protocol by retrieving the command descriptor from host memory and then parsing the descriptor execution. Complex data movement operations may be implemented by linking DMA descriptors together to form a list of descriptor blocks, where the descriptors in each descriptor block exist in contiguous host memory space.

In this embodiment of the present application, the command descriptor may be parsed, and parsing information may be obtained, where the parsing information may include: address, data length, etc. In the embodiment of the present application, the address may include: a source address and a destination address.

Step S102, under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, a read data request is sent to the radio equipment to obtain SRIO response information of the radio equipment, and a PCIe write command is sent to the host based on the SRIO response information to write data into the memory space of the host.

In an embodiment of the present application, the descriptor of the read command may include: DMA descriptor of SRIO NREAD or SRIO maintenance read (maintenance read) command. The DMA data source of the read command is the memory of the Rapid DEVICE, and the DEVICE ID representing the Rapid DEVICE, the SRIO address/configuration offset of the DMA data, and other attributes in the SRIO header are all part of the DMA descriptor.

In this embodiment of the present application, the destination end of the DMA data of the descriptor of the read command is a host memory, and the destination address is a PCIe address in the descriptor. The S-RIO address is used as a source address, SADDR is used as a destination address, DADDR is used as a PCIe address, a DMA channel of the BDMA engine pre-fetches a DMA descriptor, sends an SRIO NREAD or SRIO maintenance read command to read the memory data of the radio device, and then converts an SRIO response into a PCIe MWr packet to store the data in a host memory space.

And step S103, when the command type of the command descriptor is determined to be a write command based on the analysis information, sending a PCIe read command to the host to read CPLD data from the host, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device.

In an embodiment of the present application, the descriptor of the write command may include: SRIO (SRIO)

The DMA descriptor of the NWRITE/SWRITE/NWRITE_R or SRIO maintenance write (maintenance write) command, the DMA data source of the descriptor of the write command is host memory, and the source address is the PCIe address in the DMA descriptor. The DMA data destination is the memory of the Rapid DEVICE, and the Device ID representing the Rapid DEVICE, the SRIO address/configuration offset of the DMA data, and other attributes in the SRIO header are all part of the DMA descriptor. PCIe address is a source address, denoted by SADDR, SRIO address is a destination address, denoted by DADDR.

In this embodiment of the present application, the DMA channel of the BDMA engine may prefetch the command descriptor, initiate a PCIe MRd command to read data from the host, then convert the CPLD data returned by PCIe into an SRIO NWRITE/SWRITE/nwrite_r or SRIO maintenance write command, and send the data to the radio device.

According to the method provided by the embodiment of the application, under the condition that the command descriptor is acquired from the host, the command descriptor is analyzed, so that analysis information is obtained; under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, sending a read data request to the radio equipment to obtain SRIO response information of the radio equipment, and sending a PCIe write command to the host based on the SRIO response information to write data into the memory space of the host; and under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information, sending a PCIe read command to the host to read CPLD data from the host, and sending an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device, so that data movement between the host and the radio device can be realized.

In this embodiment, the SRIO packets are of many types, and each processing element of the request packet is different, where the element represents a series of operations performed by the SRIO peer to complete the request. Table 1 is a schematic table of operation meanings of all request packet types and transmission types of SRIO provided in the embodiment of the present application, as shown in table 1:

Each type of request packet has a corresponding field representing a specific execution requirement of the request, and table 2 is a schematic representation of meanings represented by different fields in the request packet according to the embodiment of the present application, as shown in table 2:

the combined fields and positions of the data packets of different types are different in transmission, and the data packets of the SRIO can comprise: fig. 3 is a schematic diagram of a data structure of a read request transmission provided in an embodiment of the present application, fig. 4 is a schematic diagram of a data structure of a write request transmission provided in an embodiment of the present application, fig. 5 is a schematic diagram of a data structure of a maintenance request provided in an embodiment of the present application, fig. 6 is a schematic diagram of a data structure of a reply packet provided in an embodiment of the present application, and the reply packet (reply) is divided into with data and without data, and if the type is without data, then the reply example in fig. 6 does not have subsequent 8bytes data.

The BDMA engine supports all types of SRIO packet conversion and realizes efficient and stable data transmission through the DMA channel.

In the embodiment of the application, the BDMA engine mainly realizes large-scale data movement between the host and the radio equipment, and the flexible address selection mode of the BDMA engine can greatly improve the utilization and performance of the memory.

The BDMA engine initiates a read-write command of data by acquiring and analyzing the descriptor command, and each channel supports the read-write command at the same time, and updates the state after completing the command to handshake with a Host to represent that the execution of the descriptor is completed. According to the command execution steps and types, the main functions of the BDMA engine include:

1. descriptor prefetch: this function is primarily implemented to read command descriptors from host memory and store them in BDMA engine memory. The design can obtain 32 descriptors at a time, one descriptor can transmit 64M data at maximum, and 3 descriptor types are supported for use in different scenes.

2. Read command execution: this function is used to trigger the reading of data from the SRIO device and then the transfer of the data to the host. The method comprises the steps that 32 descriptor commands can be executed at most simultaneously under the condition that memory is available, and the descriptor commands are transmitted to a host in an out-of-order mode;

3. write command execution: the function is used for triggering the data of the host to be read into the BDMA engine cache and then written into the srio equipment, and the design can simultaneously execute 32 commands at most under the condition that the memory is available and sequentially transmit the commands into the srio equipment;

4. and (5) updating the state: the function reports the execution condition of the normal completion descriptor, and realizes command handshake between the host and the BDMA engine. To be able to save the consumption of the bus by the module, the function updates the state once after completing 8 descriptors by default, and the sending frequency is configurable.

The design of the functions can realize the following characteristics of the BDMA engine: support independent 8-channels; each lane supports data movement from host to SRIO device and data movement from SRIO device to host; a Round-robin arbitration mechanism is realized among all channels; a maximum of 32 descriptors per channel can be prefetched; the description linked list supports Scatter-and-gather; step, loop back and three address modes are supported; a single descriptor supports a maximum of 64M data transmission; each channel simultaneously supports read-write descriptors; supporting a dynamic descriptor linked list; a total of 64 outlining PCIe side commands are supported; a total of 64 outlining SRIO side commands are supported; the following SRIO command types are supported: NREAD, NWRITE, SWRITE, NWRITE _R, maintance read, maintenance write, support three types of descriptors; support descriptor embedded data transfer.

In some embodiments, prior to step S101, the method further comprises:

under the condition that the descriptor caches are larger than the preset number, determining the number of command descriptors which need to be executed and the minimum value of the residual caches; determining a number of command descriptors to be acquired from the host based on the number and the minimum value; and initiating a read command of the command descriptor to the host based on the number of command descriptors required to be acquired from the host, so as to acquire the command descriptor from the host.

In this embodiment of the present application, the preset number may be configured, and for example, when the buffer space of the descriptor is greater than 8, descriptor acquisition is automatically initiated, where the number of acquired commands to be executed is the minimum value of the number of remaining commands and the remaining buffers.

In the embodiment of the application, the number of command descriptors needing to be acquired from the host can be determined through two command pointer registers.

In the embodiment of the application, the two command pointer registers can enable the computer to trigger the execution of the command of the message at any time and monitor the progress condition of the command execution. These two registers are defined as DMA Descriptor Write Count and DMA Descriptor Read Count, each DMA has an independent register, the DMA Descriptor Write Count register is maintained by the host, the host informs the BDMA engine of the number of message commands that need to be processed by updating the registers, the DMA Descriptor Read Count register is maintained by the BDMA engine, and the BMDA engine needs to update the registers every time a command is fetched, the total number of commands that need to be processed is the difference of the two registers. Both of these registers exist in the BMDA engine, which can be accessed by the host through memory read/write type commands.

In the embodiment of the present application, the size of one descriptor is 16 bytes, in order to reduce latency and arbitration overhead of descriptor acquisition, 32 descriptors can be prefetched in each DMA channel at most, and the descriptor acquisition adopts a real-time monitoring scheme, and when the number of descriptor caches is greater than 8, the descriptor acquisition is automatically initiated, where the number of acquired commands to be executed is the minimum of the number of remaining commands and the remaining caches.

In the embodiment of the present application, the command for acquiring the descriptor is a PCIe memory read type packet, and the descriptor acquiring function of different DMA channels of the BDMA engine designates a specific ID for accurately receiving the descriptor command read from the host. Each time the start address of the fetch descriptor is an accumulation of the previous address, the initial address is specified by the host and stored in register Outbound DMAChannel Descriptor Pointer.

In the embodiment of the present application, the types of the command descriptors may include: block pointer descriptors, data transfer descriptors, direct data transfer descriptors, and data transfer descriptors, direct data transfer descriptors may be read-write commands.

In the embodiment of the present application, type 1 contains some descriptions about data transmission, which are called data transmission descriptors. Type 2 is a direct data transfer descriptor. Type 3 is a block pointer descriptor used to concatenate descriptor blocks.

In this embodiment, each DMA channel has only one descriptor list, and one descriptor block includes a plurality of descriptors existing in a continuous memory space. The last descriptor may be any type of descriptor, the type 3 descriptor represents the end of the descriptor block, and each host 4K memory page holding the descriptor must be prefetchable, otherwise it may result in an unexpected error.

In some embodiments, after step S101, the method further comprises: updating a channel descriptor pointer in a case that it is determined that a command type of the command descriptor is a block pointer descriptor based on the parsing information; reinitiating a read command of the command descriptor to the host based on the block pointer descriptor; in case the type is a non-block pointer descriptor, the command descriptor is stored in a command descriptor cache and the number of command descriptors read is updated.

In this embodiment of the present application, fig. 7 is a schematic diagram of an acquisition flow of a descriptor provided in this embodiment of the present application, as shown in fig. 7, including:

in step S801, the host configuration DMA Descriptor Write Count register updates the trigger command descriptor (descriptor) prefetch.

Step S802, judging whether the DMA channel is a suspend or an abort.

In the embodiment of the present application, if not, step S803 is executed, and if yes, the judgment is continued.

In step S803, the number of commands is calculated.

In step S804, it is determined whether the difference between the write number and the read number is greater than 0.

In the embodiment of the application, by determining the difference value, it can be determined how many command descriptors of host need to be executed.

Step S805, determine whether the descriptor cache is not full.

In the embodiment of the present application, step S803 is performed if full, and step S806 is performed if not full.

In this embodiment, the descriptor cache space can store at least 8 descriptors, and the minimum value is compared with the total number of the descriptor commands to determine how many descriptors are acquired at a time.

Step S806, a read command of the descriptor is initiated.

In the embodiment of the application, a read command is initiated to the host memory space.

Step S807, it is determined whether the descriptor is abnormal.

In the embodiment of the present application, if abnormal, step S808 is performed, and if not abnormal, step S809 is performed.

Step S808, executing the abart process.

After step S808, the flow ends.

Step S809, parse and classify the descriptors.

Step S810, determining whether the descriptor is abnormal.

In the embodiment of the present application, if abnormal, step S811 is performed, and if not abnormal, step S813 is performed.

Step S811, discard the current descriptor.

After step S811, step S812 is performed.

Step S812, the number of read commands of the descriptor is updated.

After step S812, post-headquarter S809 is performed.

Step S813, determine whether DTYPE3.

In the embodiment of the present application, if yes, step S814 is performed, and if no, step S815 is performed.

In step S814, the number of Descriptor reads is updated DMAChannel Descriptor Pointer.

After step S814, step S802 is performed.

Step S815, the number of reads is stored in the descriptor cache and updated.

In step S816, whether all descriptors are parsed is completed.

In the embodiment of the present application, if yes, step S801 is performed, and if no, only step S809 is performed.

In this embodiment of the present application, the data transmission descriptor is used to trigger massive data transmission, and is of type DTYPE1, and the data transmission descriptor is of type DTYPE1, and fig. 8 is a schematic diagram of a data transmission descriptor provided in this embodiment of the present application, as shown in fig. 8, where fields of the data transmission descriptor are as follows

Table 3 as shown in table 3, table 3 is a schematic illustration of a data transmission descriptor field provided in an embodiment of the present application,

in the embodiment of the application, one DMA data transfer may be composed of a plurality of SRIO packets. The data transfer DMA descriptor instructs the DMA channel to perform a data transfer operation. Descriptor processing is complete when data transfer is complete or errors are detected.

SRIO address RADDR [65:0] may be any byte alignment, RADDR being the source address when RTYPE is NREAD, labeled SADDR. Otherwise, RADDR is the destination address, marked as DADDR. The 64bit PCIe address BUFFER_PTR [63:0] may be any byte alignment, with BUFFER_PTR being the destination address, labeled DADDR, when RTYPE is NREAD. Otherwise BUFFER_PTR is the source address, labeled SADDR.

For descriptors where RTYPE is NREAD or maintenance read, the BDMA engine generates one or more NREAD commands and converts corresponding SRIO response information Responses to PCIe MWr for transmission to the host. A plurality of NREAD commands will be generated when: (1) BCOUNT exceeds 256Bytes; (2) RAADR non-8-Byte alignment; (3) The SRIO address steps and the payload of the descriptor request spans multiple non-consecutive SRIO step addresses. When this happens, the BDMA needs to generate multiple SRIO NREAD commands. An SRIO Response may also be split by a DMA channel into one or more PCIe MWr: (1) one SRIO Response crosses PCIe 4K boundary; (2) one SRIO Response exceeds PCIe MAX_PAYLOAD_SIZE; (3) PCIe address step and requires writing SRIO Response to two or more non-consecutive host step addresses. When this happens the BDMA engine needs to split the SRIO response into multiple MWr TLP packets. SRIO responses for different requests are out of order, as specified by the SRIO protocol. The BDMA engine may not receive SRIO responses in the order of requests. This requires the BDMA engine to dynamically translate these responses into PCIe MWr, so the PCIe MWr issued by the BDMA engine may not arrive at the destination address in the order in which NREADs were issued.

For descriptors where RTYPE is non-NREAD or maintenance read, the BDMA engine needs to generate one or more PCIe MRds to fetch data from host memory and convert the returned CPLD into one or more SRIO NWRITE/SWRITE/NWRITE_R/maintenance write commands. A plurality of MRd commands will be generated when: (1) bcour exceeds PCIe MRRS; (2) descriptor data requests cross 4K boundaries; (3) PCIe address step, the data requested by the descriptor exists in non-contiguous step addresses. The BDMA engine may initiate MRd commands that do not cross 4K boundaries and are less than or equal to the MRRS maximum data payload. For a memory read request for PCIe, one or more CPLDs are returned, which are converted by the BDMA engine into one or more NWRITE/SWRITE/NWRITE_R/maintenance write commands. The DMA channel reassembles the returned multiple pcie plds and sends NWRITE/SWRITE/nwrite_r/maintenance write packets with rules of SRIO. Sometimes, however, the BDMA engine splits a CPLD into multiple NWRITE/SWRITE/NWRITE_R/maintenance write packets. Since the protocol specifies that the SRIO address must be 8-byte aligned, but the addresses of PCIe and SRIO in the descriptor are arbitrarily byte aligned, this also requires the BDMA engine to split the return data into multiple segments to send NWRITE/SWRITE/NWRITE_R/maintenance write packets. When the SRIO address uses a step mode, PCIe return data needs to be written into two or more non-contiguous address spaces, at which time the BDMA engine is also required to split the return data into multiple segments to send NWRITE/SWRITE/NWRITE_R/maintenance write packets. It should be noted that CPLDs returned for different requests are out of order, as specified by the PCIe protocol, and thus the BDMA engine may not receive CPLDs in the order of the requests. The BDMA engine needs to reassemble CPLD and ensure that NWRITE/SWRITE/NWRITE_R packets arrive at the SRIO destination in the correct order.

In this embodiment, the direct data transfer descriptor is used to instruct the DMA channel to transfer the data embedded in the descriptor to the target device (the DMA transfer has no source address), or to read the data of the source device to the descriptor (the DMA transfer has no destination address), and to write the descriptor of the embedded data into the descriptor acquisition pointer. The direct data transmission descriptor is used for triggering a small amount of data transmission, and is of type DTYPE2, fig. 9 is a schematic diagram of a direct data transmission descriptor provided in an embodiment of the present application, as shown in fig. 9, table 4 is a schematic diagram illustrating one field in a direct data transmission descriptor provided in an embodiment of the present application, as shown in table 4,

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the implementation of the direct data transfer descriptor is similar to the data transfer descriptor except that the data is embedded in the descriptor and the maximum transfer size is 16bytes. When RTYPE is NWRITE/SWRITE/NWRITE_R/maintenance write, the PCIe MRd command is not sent because the data is present in the descriptor. When RTYPE is NREAD/maintenance read, the BDMA engine generates a PCIe MWr with descriptor pointer as address to write the read data into. Direct data transfer descriptors do not support fixed address and step address modes.

For descriptors where RTYPE is NREAD or maintenance read, BDMA causes one or more NREAD commands to be generated and the corresponding SRIO Responses are translated into PCIe MWr for transmission to the host. Multiple NREAD commands will be generated when RADDR non-8-byte aligns. SRIO responses for different requests are out of order, as specified by the SRIO protocol. The BDMA engine may not receive SRIO responses in the order of requests. This requires the BDMA engine to dynamically translate these responses into PCIe MWr, so the PCIe MWr issued by the BDMA engine may not arrive at the destination address in the order in which NREADs were issued.

For other types of RTYPE, the BDMA engine will generate one or more

NWRITE/SWRITE/nwrite_r/maintenance write packet.

The Block pointer descriptor can dynamically jump the descriptor Block to other memory spaces, and addresses of the descriptors in the same Block are continuous.

In this embodiment of the present application, fig. 10 is a schematic diagram of a jump from a block pointer descriptor to another memory space, where, as shown in fig. 10, the block pointer descriptor flexibly uses memory resources, and connects descriptors of different intervals in series.

Fig. 11 is a schematic diagram of a format of a block pointer descriptor according to an embodiment of the present application, as shown in fig. 11, and table 5 is a schematic diagram of field descriptions of a block pointer descriptor according to an embodiment of the present application, as shown in table 5.

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In some embodiments, step S102 may be implemented by:

under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, a read data request is sent to the radio equipment based on the command descriptor and the analysis information so as to obtain SRIO response information of the radio equipment, parameters of the read data request are stored in corresponding command caches, and data in the SRIO response information are stored in the cache area; and detecting the state of the command descriptor through SRIO response information, analyzing the command descriptor to acquire the memory space of the host, and sending a PCIe write command to write the data read from the Rapid device into the memory space of the host.

In some embodiments, the parsing information includes: data length and address information, said sending a read data request to said Rapidio device based on command descriptor and parsing information, comprising:

determining an address pattern, a source data address and a destination data address based on the address information,

determining whether to disassemble the command descriptor into commands based on the address pattern and the data length;

under the condition that disassembly is needed, the command descriptor is disassembled, and a read data request is sent to the radio equipment based on the disassembled command descriptor;

And sending a read data request to the radio equipment based on the command descriptor without disassembly.

In some embodiments, before sending the PCIe write command to the host, the method further comprises:

judging whether the write address of the host of the PCIe write command is overlapped with the address of the host of the current read command;

in the event that there is an overlap, determining whether the current read command is complete;

determining whether to send the PCIe write command to the host based on whether the current read command is completed, wherein the PCIe write command is sent to the host if the current read command is completed, and waiting for the completion of the current read command if the current read command is not completed.

In this embodiment, the whole read command execution may be divided into two functional areas, where the first area faces the radio device and the second area faces the host on the PCIe side, and the two areas have both independence and relevance. The method comprises the following steps:

SRIO region:

in order to be able to send read commands quickly and avoid waiting for response to affect command execution, command execution on the side of SRIO is divided into two parts, the first part of functions being: reading an analysis descriptor, calculating an address, calculating a cache size, initiating an SRIO read command, applying for a command ID and the like; the second part functions as: and receiving the read data, storing the read data into a corresponding cache address, and sending a PCIe write command to the PCIe operation area. The design has the advantages that the read command can be continuously sent for a plurality of times under the condition of enough cache, and the subsequent read command is not blocked by waiting for data response, so that the reading of the data is greatly improved.

The BDMA engine supports multiple address hopping patterns, so that when a read command is initiated, the address calculation needs to consider not only 8-byte alignment, but also different address patterns, and different address parameters split the command from the data. However, according to the specificity of the read operation, the length of the read command can be set to be 8-byte aligned when the read command is actually initiated, the multi-read operation is performed on the data which is not 8-byte aligned, and the returned data can be subjected to the effective data stripping operation through the actual length and the address offset.

In the embodiment of the application, two relatively common modes of the BDMA engine are linear addressing, constant addressing and step addressing.

In its simplest form, the addressing is linear addressing, and fig. 12 is a schematic diagram of the linear addressing provided in the embodiment of the present application, as shown in fig. 12, that is, data composed of bcour byte is transferred from the start address SADDR to the target address DADDR. In contrast, constant addressing is used to repeatedly read/write the same address. And is often used to move data to/from a memory mapped FIFO.

Addressing operations implemented by the DMA channel are shown at 12, table 6 provides a schematic representation of relevant parameters for embodiments of the present application, as shown in table 6,

although the source addressing algorithm and the destination addressing algorithm are the same, different parameters may lead to different behaviors; when byte count is exhausted, the addressing operation is completed.

Table 7 shows a schematic table of DMA channel address parameters according to the embodiment of the present application, as shown in Table 7:

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linear address transmission means that the acquisition and transmission addresses of data are consecutive, SSSIZE, SSDIST or DSSIZE, DSDIST being 0 when linear address transmission is performed. Table 8 is a schematic table provided in the embodiment of the present application, in which a linear address mode is used to transmit 1K data, as shown in table 8:

in the embodiment of the application, the loopback address transmission is similar to FIFO access, and data reading and writing are performed in a certain address range, and the process is repeated until bcour ends. SSSIZE or DSSIZE is not zero and SSDIST or DSDIST is negative when performing loop-back address transfer. Fig. 13 is a schematic diagram of a loopback address transmission according to an embodiment of the present application, as shown in fig. 13, and table 9 is a schematic table of a loopback address mode for transmitting 1K data according to an embodiment of the present application, as shown in table 9,

in this embodiment, the step address transmission is a fixed interval discrete data transmission mode, and data with a fixed length is acquired or written in a fixed interval, and the steps are repeated until bcour ends. SSSIZE or DSSIZE is not zero and SSDIST or DSDIST is a positive number when step address transmission is performed. Fig. 14 is a schematic diagram of a step address transmission manner provided in the embodiment of the present application, and as shown in fig. 14, table 10 is a schematic table of a step address transmission manner for transmitting 1K data provided in the embodiment of the present application:

In the embodiment of the application, the PCIe address and the SRIO address in the descriptor may be any byte alignment, but the protocol specifies that the PCIe command address must be DW (Double Word) aligned, and the SRIO command address must be byte aligned, so that the PCIe direction and the SRIO direction data and address alignment operations are particularly important in the DMA design. The address operation design will be described below by way of example, respectively.

SRIO address alignment: the SRIO protocol specifies that all read and write operations must specify the transmission data size and Byte enable according to the combination of wdtr and rdsize, wrsize, so that all commands must be sent in compliance with the combination specification, and hereinafter, all data combination modes are specified for SRIO, and the transmission not existing in the combination modes must be disassembled into the specified combination modes.

Fig. 15 and 16 are schematic diagrams illustrating definition of a read command size according to an embodiment of the present application, as shown in fig. 15 and 16. Fig. 17 and fig. 18 are schematic diagrams illustrating the definition of a write command size according to an embodiment of the present application.

SRIO has a large end data payload with 8-byte alignment. This means that this data interaction with PCIe requires a size-end data translation operation to format the data payload. The size end conversion function is designed as follows:

In the embodiment of the application, the data operation of less than 8-byte should make the byte find the proper position for byte alignment in the big-end 8-byte. When the SRIO address is 0x0000_0002, the transmission data is 1byte, the correct data position is shown as a hatching, wddtr=0b0, wrsize/rdsize=0b 0010. When the SRIO address is 0x0000_0002, the transmission data is 2byte, the correct data position is shown as a shadow, wddtr=0b0, wrsize=0b 0110. When the SRIO address is 0x0000_0004, the transmission data is 4byte, the correct data position is shown as a hatching, wddtr=0b1, wrsize=0b1000.

For a write operation, the processing element should properly transfer the data to the 8-byte alignment boundary in order to properly transfer the data to the destination. If the data is not naturally aligned, then the data needs to be split into multiple transactions. Fig. 19 is a schematic diagram of a streaming provided in an embodiment of the present application, and as shown in fig. 19, the following example illustrates a 48-byte data streaming, and although the entire data size is 8-byte aligned, since the addresses are not 8-byte aligned, a command needs to be divided into three transactions.

Since the AXI interface is required to be used for connection with the PCIe controller in the design, the 4-byte aligned data transmission specified by the PCIe protocol requires appropriate conversion according to the bit width of the AXI interface. Fig. 20 is a schematic diagram of performing appropriate conversion according to the bit width of the AXI interface according to the embodiment of the present application, as shown in fig. 20, the effective data length (eL): the byte length of the active PCIe TLP contains the state of every 1 bit in byte enable (FBE/LBE).

Effective start address (eA): the address (byte granularity) of the active PCIe TLP is derived by parsing the byte enable FBE/LBE of the TLP into an aligned address with the TLP DW. To an AXI address (araddr or awaddr).

For PCIe write operations with a start address of 0x6, a true transport length of 9bytes, and a PCIe packet transport length of 3DW, to achieve DW alignment, the packet address is 0x4, the first DW is only valid for the higher 2bytes (because the true start address is 0x 6), and the last DW is valid for the lower 3bytes (because the true length is 9 bytes). The corresponding AXI interface also requires address alignment, e.g., an AXI data bus bit width of 64 bits, so 8-byte alignment is required to transfer data, with a first transfer of data having a start address of 0x6 being only high 2bytes valid (because of the data bus 8-byte alignment) and a second transfer of data being only low 7bytes valid (because of the transfer length remaining only 7 bytes).

The data command transmission modes of AXI and PCIe are similar to write data for read data, but different from the write data, the write data can be any value for the complement data, only valid data is required to be specified according to byte_enable, but for read data, valid data is required to be extracted from all data through read address offset and data length. If the initial address is 0x6 and the real length is 9bytes, the read command is actually data from 0x4 address to 3DW, then through an AXI interface aligned with 8-bytes, the design needs to obtain only high 2bytes data of the first data of AXI through the real address 0x6, and then obtain low 7bytes data of the second data according to the remaining data length, so that the PICE and corresponding AXI data address alignment operation is completed.

In order to improve the performance of the PCIe side, therefore, the PCIe uses a 128-bit-wide data bus, and the SRIO side uses a 64-bit data bit-wide, so, in order not to affect the performance of PCIe sending data, a bit-wide conversion operation is placed at the SRIO data receiving end, an alignment and removal operation of valid data is based on the data after the bit-wide conversion, and final valid data is written into the sram.

The Rapidio protocol specifies that the returned responses are out-of-order replies, no sequential relation to the initiated read request, so in order to be able to identify different read commands split by different descriptors, a unique ID needs to be applied for each request before sending the command, which ID is used to correspond to the response receiving the corresponding request and to be able to manage in real time the status of completion of each descriptor command.

In order to send the read data to the host more quickly, the data after all the descriptors are split is waited for to be recombined under the common operation because of the disorder of the SRIO, and then the recombined data is integrally written into the host, but the performance is affected by the limited cache in the DMA channel. Therefore, when the SRIO command is sent, the PCIe side address corresponding to the command is synchronously calculated, and according to the address and the ID, the PCIe side can write the data returned by each disordered sequence into the corresponding host space, so that the command conversion efficiency is greatly improved.

PCIe region:

this function includes: receiving and analyzing a write command sent by an SRIO region, reading cache data, performing non-alignment operation according to an address, generating a PCIe MWr command, releasing an SRIO ID and a cache, and generating a descriptor update command.

Although the command sent in the SRIO domain already includes the write address on the PCIe side, since the host address jump also supports multiple modes, the write command needs to be split into multiple write commands according to the mode and the address parameters based on the existing PCIe address.

When executing a PCIe write command, care should be taken to prevent the host memory data from being covered, which results in the change of the data read by the SRIO write command from the host, so before sending the PCIe write command, it needs to check whether there is an overlapping area between the host memory address currently read by the SRIO write operation and the write address, if there is no overlapping, the write command may be directly sent, and if there is an overlapping address, it needs to wait for the SRIO write operation to complete the host read command, and then the PCIe MWr may be executed.

Fig. 21 is a schematic diagram of a processing flow of a read command according to an embodiment of the present application, as shown in fig. 21, including: firstly, when the descriptor is retrieved, the execution of the descriptor buffer non-empty trigger command is detected, and if the current DMA channel state is the record, the command is not executed. And fetching a command from the descriptor buffer, analyzing the address, the length, the mode, the command and S-RIO related command information, and determining whether to disassemble the current descriptor command or the current residual descriptor according to the address parameter, the mode, the transmission data length and the current data buffer. After calculation, a read data request is initiated to the S-RIO side, parameters related to the command are stored in the internal outstanding buffer for waiting for data arrival, and then a PCIe write command is sent. After the command is sent, when the write PCIE side detects that there is a read command, the command is read, and read data is waited for to return, and it should be noted here that, because the S-RIO bridge splits our request into a plurality of read requests to send, and the returned data is out of order, in order to improve performance, out of order return out of order write is designed, so that relevant information of the split command needs to be obtained while the data is accepted, so that BDMA can calculate the position of the returned data, and thus calculate a proper PCIe write address. Before the PCIe side write command is initiated, whether the write address is overlapped with the PCIe side address of the current read command is judged, and if so, the write command can be initiated only after the read command is completed. The split command is also determined according to the address mode until the data of the write command is completely sent, and the current step is repeated until all commands of the current descriptor are completed. An interrupt needs to be issued after completion of the assert IOF. If the acquired data has errors, entering an abart process. The above operation is repeated until all descriptors have completed returning to IDLE.

In some embodiments, step S103 may be implemented by:

determining an address mode, a source data address and a destination data address based on the address information under the condition that the command type of the command descriptor is determined to be a write command based on the analysis information;

under the condition that disassembly is needed, the command descriptor is disassembled, and a reading data request is sent to a host based on the disassembled command descriptor;

sending a read data request to a host based on the command descriptor without disassembly;

storing parameters of the read data request into an unfinished buffer to read CPLD data from the host device and store the CPLD data in the buffer;

and sending a write command to the radio device so that the radio device detects that the read command is not completed, wherein when the radio device detects that the read command is not completed, acquiring data from the cache area and writing the data into the radio device.

In this embodiment, the whole write command execution is divided into two functional areas, the first area faces the PCIe side, the second area faces the radio side, and the designs of the two areas have both independence and relevance.

The specific design is as follows:

PCIe region:

in order to improve the conversion performance, the PCIe region splits the message read command behavior into two parts, the first part functions as: reading the analysis descriptor, calculating the address, calculating the buffer size, and initiating a PCIe MRd read command; the second part functions as: and receiving the read data, storing the read data in a corresponding cache address, and sending an SRIO write command to the radio area. The design has the advantages that the read command can be continuously sent for a plurality of times under the condition of enough cache, and the subsequent read command is not blocked by waiting for data response, so that the reading of the data is greatly improved.

It should be noted that, when calculating the address and data volume, since BDMA supports multiple address hopping patterns, it is necessary to consider not only crossing the host 4K page boundary but also the address hopping boundary condition when sending the command. Thus, the starting address and the data size of each read data need to be continuously calculated and adjusted according to the address mode and the corresponding address parameters. And secondly, because the addresses of the multiple read commands and the data quantity are aligned by the non-data bus, the data read by each pen need to be aligned according to the address offset, and then the effective data which are picked out are stored in the SRAM.

SRIO region:

in order to be able to send data quickly and avoid waiting for response to affect command execution, the command execution on the side of SRIO is also divided into two parts, the first part of functions being: receiving a write command, an analysis command, read data, generate an SRIO packet, send data and the like sent by an analysis PCIe area; the second part functions as: receive response of the resolution device, release data cache, initiate descriptor update command, etc. When the write command type does not need to receive response, the descriptor update command is triggered by executing only the first part.

There are two points in sending write commands and data that are difficulties in the transition design: first: the SRIO side also supports a plurality of address modes, so that the address calculation of the write command not only needs to consider the 8-byte alignment, but also needs to consider different address modes, and different address parameters split the command and the data; second,: because the PCIe uses 128bit wide data bus and the SRIO uses 64bit wide data bus to improve PCIe side performance, so that the bit wide conversion operation is put at the SRIO data transmitting end in order not to affect PCIe data receiving performance, but because of splitting any data length and address, effective data in the next command may exist in the last converted data, so that the sram address callback needs to be controlled according to the transmitting address offset to prevent data from being read out.

The DMA write channel can execute multiple descriptors simultaneously, each descriptor can be split into multiple commands, and the BDMA engine can dynamically track and manage each command of each descriptor.

Fig. 22 is a schematic flowchart of implementation of a write command according to an embodiment of the present application, where, as shown in fig. 22, the method includes: firstly, when the descriptor is retrieved, the execution of the descriptor buffer non-empty trigger command is detected, and if the current DMA channel state is the record, the command is not executed. And fetching a command from the descriptor buffer, analyzing the address, the length, the mode, the command and S-RIO related command information, and determining whether to disassemble the current descriptor command or the current residual descriptor according to the address parameter, the mode, the transmission data length and the current data buffer. After calculation, a read data request is initiated to the PCIE side, and parameters related to the command are stored in the internal outstanding buffer to wait for the arrival of data and then the write command is sent. After the command is sent out, the two-line parallel execution is divided into:

if the full execution of the current description Fu Weiwan is completed, the process returns to the previous step to recalculate and initiate a new command (the linear address mode generally needs to wait until data is transmitted to the S-RIO side before the data buffer space initiates a new command, and other modes may need to initiate commands again before data is not transmitted) until the channel outstanding command is full. If the current descriptor has been completed, a first step may be returned to re-execute the new command.

When the writing S-RIO side detects that a writing command is output, the command is read, the reading data is waited to return and reach the set threshold number to initiate the S-RIO side writing command, the splitting command is also determined according to the address mode at the same time until the data of the reading command is completely sent, and the current steps are repeated until all commands are completed. An interrupt needs to be issued after completion of the descriptor at the time of the assert IOF. If the acquired data has errors, entering an abart process.

The above operation is repeated until all descriptors have completed returning to IDLE.

In some embodiments, to enable the host to monitor the state of the descriptor execution, for a descriptor state update operation, the host is informed of the result check by writing the normally executed descriptor address into the host memory and by updating the pointer or interrupt, the host can determine whether the descriptor is normally completed by comparing the descriptor pointer to release the descriptor resource or perform a resend operation.

The update address is configured by the host at initialization, the configuration register is DMA Descriptor Status FIFO Base, and the space size is defined in register DMA Descriptor Status FIFO Size. While the design descriptor updates the pointer registers DMA Descriptor Status FIFO Read Pointer and DMA Descriptor Status FIFO Write Pointer, the write pointer is maintained by the design to indicate the number of state updates, and the read pointer is maintained by the software to inform the hardware of the progress of the hardware design software processing results, thereby managing the state update space.

Fig. 23 is a schematic diagram of a descriptor status update data format according to an embodiment of the present application, where, as shown in fig. 23, each descriptor status entry has a length of 64 bytes and is divided into 8 segments, and each segment stores a successfully completed descriptor acquisition address. Representing termination of the state entry when the host reads a segment address of all 0 s.

In order to reasonably utilize the descriptor status update space and reduce the influence of frequent update status on bandwidth, the method is designed to send descriptor update data in an aggregation or triggering mode, namely, the descriptor status is updated when the following conditions are met: and the number of completion descriptors is greater than or equal to 8, the descriptors execute errors, and the last descriptor is completed.

In this embodiment of the present application, fig. 24 is a schematic diagram of an update flow of a descriptor provided in this embodiment of the present application, as shown in fig. 24, including: the message execution function sends an update descriptor status command; the BDMA engine judges whether the current state buffer is in a full state or not (whether the value of WR_PTR+ MOD DMA Descriptor Status FIFO Size is equal to RD_PTR or not) according to the buffer size updated by the descriptor and the read-write pointer, if so, the BDMA engine pauses the state update, and if not, the BDMA engine starts the state update; the BDMA engine takes up to 8 pointers as an entry to form a MWr; after the PCIE receives MWr, the PCIE indicates that the message engine writes the pointer of the processed descriptor into an entry of the descriptor state cache; the BDMA engine updates DMA Descriptor Status FIFO Write Pointer register write pointer WR_PTR to be added with 1, and is used for informing the host of the updated number; software judges whether an entry is valid or not, and needs to constantly read a descriptor state buffer to acquire a complete entry, each entry possibly has 1 to 8 pointers, and if all the pointers are 0, the entry is proved to be invalid; software clears the read entry; after the software reads the post entry, adding 1 to the read pointer RD_PTR of the DMA Descriptor Status FIFO Read Pointer register; checking the update number of the descriptor state, matching the receiving and transmitting descriptor addresses, and then performing retransmission, reset or initialization operation. If all descriptor states are updated, it represents the end of the entire messaging operation.

Based on the foregoing embodiments, the embodiments of the present application provide an information processing apparatus, where each module included in the apparatus, and each unit included in each module may be implemented by a processor in a computer device; of course, the method can also be realized by a specific logic circuit; in practice, the processor may be a central processing unit (CPU, central Processing Unit), a microprocessor (MPU, microprocessor Unit), a digital signal processor (DSP, digital Signal Processing), or a field programmable gate array (FPGA, field Programmable Gate Array), or the like.

An embodiment of the present application provides an information processing apparatus, and fig. 25 is a schematic structural diagram of the information processing apparatus provided in the embodiment of the present application, as shown in fig. 25, an information processing apparatus 2500 includes:

the parsing module 2501 is configured to parse the command descriptor to obtain parsing information when the command descriptor is obtained from the host;

the first processing module 2502 is configured to send a read data request to the radio device to obtain SRIO response information of the radio device when the command type of the command descriptor is determined to be a read command based on the parsing information, and send a PCIe write command to the host based on the SRIO response information to write data into a host memory space;

The second processing module 2503 is configured to send a PCIe read command to the host to read CPLD data from the host, and send an SRIO write command to the radio device based on the CPLD data to send the CPLD data to the radio device, where the command type of the command descriptor is determined to be a write command based on the parsing information.

In some embodiments, the information processing apparatus further includes:

the first determining module is used for determining the number of the command descriptors which are required to be executed and the minimum value of the residual caches under the condition that the descriptor caches are larger than the preset number;

the second determining module is used for determining the number of command descriptors needing to be acquired from the host computer based on the number and the minimum value;

and the first sending module is used for initiating a read command of the command descriptor to the host based on the number of the command descriptors required to be acquired from the host so as to acquire the command descriptor from the host.

In some embodiments, the information processing apparatus further includes:

a first updating module, configured to update a channel descriptor pointer in a case where it is determined that a command type of the command descriptor is a block pointer descriptor based on the parsing information;

a second sending module, configured to reinitiate a read command of the command descriptor to the host based on the block pointer descriptor;

And the second updating module is used for storing the command descriptors in a command descriptor cache and updating the number of the read command descriptors in the case that the type is a non-block pointer descriptor.

In some embodiments, the first processing module comprises:

the first processing unit is used for sending a read data request to the radio equipment based on the command descriptor and the analysis information under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information so as to obtain SRIO response information of the radio equipment, storing parameters of the read data request into an unfinished buffer area, and storing data in the SRIO response information into the buffer area;

the first sending unit is used for detecting the state of the command descriptor through the SRIO response information, analyzing the command descriptor to acquire the memory space of the host, and sending a PCIe write command to write the data read from the radio device into the memory space of the host.

In some embodiments, the parsing information includes: data length and address, said sending a read data request to said Rapidio device based on command descriptor and parsing information, comprising:

In some embodiments, prior to sending the PCIe write command to the host, the first processing module further comprises:

the judging unit is used for judging whether the write address of the host of the PCIe write command is overlapped with the address of the host of the current read command;

a first determining unit for determining whether the current read command is completed in case of overlap;

and a second determining unit, configured to determine whether to send the PCIe write command to the host based on whether the current read command is completed, where the PCIe write command is sent to the host when the current read command is completed, and wait for the completion of the current read command when the current read command is not completed.

In some embodiments, the parsing information includes: address and data length, a second processing module comprising:

a third determining unit configured to determine an address mode, a source data address, and a destination data address based on the address information, in a case where it is determined that the command type of the command descriptor is a write command based on the parsing information;

A fourth determining unit for determining whether to disassemble the command descriptor based on the address pattern and the data length;

the disassembly unit is used for disassembling the command descriptor under the condition that disassembly is needed, and sending a read data request to the host based on the disassembled command descriptor;

the second sending unit is used for sending a read data request to the host based on the command descriptor under the condition that disassembly is not needed;

a buffer unit for storing the parameters of the read data request into an unfinished buffer area to read the CPLD data from the host device and store the CPLD data in the buffer area;

and the third sending unit is used for sending a write command to the radio equipment so as to enable the radio equipment to detect that the read command is not completed, wherein when the radio equipment detects that the read command is not completed, the data is acquired from the corresponding buffer area through the read descriptor information and the CPLD information, the SRIO write command is sent, and the data read from the host is written into the radio equipment.

The embodiment of the application provides electronic equipment, which can be a road side unit or a vehicle-mounted unit; fig. 26 is a schematic diagram of a composition structure of an electronic device according to an embodiment of the present application, as shown in fig. 26, the electronic device 1500 includes: a processor 1501, at least one communication bus 1502, a user interface 1503, at least one external communication interface 1504, and a memory 1505. Wherein communication bus 1502 is configured to enable connected communication between these components. The user interface 1503 may include a display screen, and the external communication interface 1504 may include a standard wired interface and a wireless interface, among others. The processor 1501 is configured to execute a program of an information processing method stored in a memory to implement the steps in the information processing method provided in the above-described embodiment.

In the embodiment of the present application, if the above-described information processing method is implemented in the form of a software functional module and sold or used as a separate product, it may also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the prior art, and the computer software product may be stored in a storage medium, and include several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

Accordingly, the present embodiment provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the information processing method provided in the above embodiment.

Embodiments of the present application further provide a computer program product for causing an electronic device to execute the information processing method according to any one of the above-mentioned claims when the computer program product is run on a terminal device.

The description of the electronic device and the storage medium embodiments above is similar to that of the method embodiments described above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the computer apparatus and the storage medium of the present application, please refer to the description of the method embodiments of the present application.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.

Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the prior art, embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a controller to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

The foregoing is merely an embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An information processing method, characterized by comprising:

under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, sending a read data request to the radio equipment to obtain packet switched interconnection (SRIO) response information of the radio equipment, and sending a high-speed serial computer expansion bus standard (PCIe) write command to the host based on the SRIO response information to write data into a host memory space;

2. The method according to claim 1, wherein the method further comprises:

under the condition that the descriptor caches are larger than the preset number, determining the number of command descriptors which need to be executed and the minimum value of the residual caches;

determining a number of command descriptors to be acquired from the host based on the number and the minimum value;

and initiating a read command of the command descriptor to the host based on the number of command descriptors required to be acquired from the host, so as to acquire the command descriptor from the host.

3. The method according to claim 2, wherein the method further comprises:

updating a channel descriptor pointer in a case that it is determined that a command type of the command descriptor is a block pointer descriptor based on the parsing information;

reinitiating a read command of the command descriptor to the host based on the block pointer descriptor;

in case the type is a non-block pointer descriptor, the command descriptor is stored in a command descriptor cache and the number of command descriptors read is updated.

4. The method according to claim 1, wherein, in the case that the command type of the command descriptor is determined to be a read command based on the parsing information, sending a read data request to the radio device to obtain SRIO response information of the radio device, and sending a PCIe write command to the host based on the SRIO response information to write data into the host memory space, including:

under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, a read data request is sent to the radio equipment based on the command descriptor and the analysis information so as to obtain SRIO response information of the radio equipment, parameters of the read data request are stored in an unfinished buffer area, and data in the SRIO response information are stored in the buffer area;

And detecting the state of the command descriptor through SRIO response information, analyzing the command descriptor to acquire the memory space of the host, and sending a PCIe write command to write the data read from the Rapid device into the memory space of the host.

5. The method of claim 4, wherein the parsing information comprises: data length and address information, said sending a read data request to said Rapidio device based on command descriptor and parsing information, comprising:

6. The method of claim 5, wherein prior to sending the PCIe write command to the host, the method further comprises:

7. The method of claim 1, wherein the parsing information comprises: address and data length, in the case where the command type of the command descriptor is determined to be a write command based on the parsing information, sending a PCIe read command to the host to read CPLD data from the host, sending a write command to the Rapidio device based on the CPLD data to send the CPLD data to the Rapidio device, comprising:

and sending a write command to the radio device so that the radio device detects that the read command is not completed, wherein when the radio device detects that the read command is not completed, the write command is read from the host to write the read data into the radio device by reading the descriptor information and the CPLD information, acquiring the data from the corresponding buffer area, and sending an SRIO write command.

8. An information processing apparatus, characterized by comprising:

the first processing module is used for sending a read data request to the radio equipment to obtain SRIO response information of the radio equipment under the condition that the command type of the command descriptor is determined to be a read command based on the analysis information, and sending a PCIe write command to the host computer based on the SRIO response information to write data into the memory space of the host computer;

9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the information processing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the information processing method according to any one of claims 1 to 7.