CN117806997A - DMA operation queue management method, apparatus, device and readable storage medium - Google Patents
DMA operation queue management method, apparatus, device and readable storage medium Download PDFInfo
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Abstract
The present disclosure relates to a DMA operation queue management method, apparatus, device, and readable storage medium. The method comprises the steps of receiving a request sent by a central processing unit, determining a DMA operation queue corresponding to the virtual machine equipment address based on a mapping table from equipment to queue, processing the request based on the DMA operation queue to obtain request processing data, determining virtual machine equipment corresponding to the address of the DMA operation queue based on the mapping table from queue to equipment, adding the address of the virtual machine equipment to the request processing data, and returning the request processing data added with the address of the virtual machine equipment to the central processing unit. Compared with the prior art, the embodiment of the disclosure manages the DMA operation queue by using the mapping table from device to queue and the mapping table from queue to device, so that the flexibility and manageability of DMA operation are improved, the DMA operation queue is allocated by using the hardware configuration mapping table, the dependence on CPU is reduced, and the system performance is improved.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for managing a DMA operation queue.
Background
In computer systems, direct memory access (Direct Memory Access, DMA) is a technique that allows peripheral devices to exchange data directly with memory without processing by a central processing unit (Central Processing Unit, CPU). This allows the data transfer to be completed more quickly, thereby improving the overall performance of the system.
Existing solutions, which typically use a single mapping table or a simple one-to-many mapping relationship to allocate DMA operation queues to peripheral devices, require the use of hardware registers to set transfer parameters, such as target addresses and transfer lengths, and require the CPU to allocate DMA operation queues.
However, the existing method is a simple mapping allocation method, has poor flexibility and manageability, and the allocation of DMA operation queues depends on a CPU, so that when a plurality of DMA operations are processed, CPU resources are occupied relatively, and the system performance is affected.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a DMA operation queue management method, apparatus, device, and readable storage medium, so as to improve flexibility and manageability of DMA operation queue allocation and improve system performance.
In a first aspect, an embodiment of the present disclosure provides a DMA operation queue management method, including:
receiving a request sent by a central processing unit, wherein the request comprises a virtual machine equipment address;
determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue;
processing the request based on the DMA operation queue to obtain request processing data;
determining virtual machine equipment corresponding to the address of the DMA operation queue based on a queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data;
and returning request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
In a second aspect, an embodiment of the present disclosure provides a DMA operation queue management apparatus, the apparatus including:
the receiving module is used for receiving a request sent by the central processing unit, wherein the request comprises a virtual machine equipment address;
the first determining module is used for determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue;
the obtaining module is used for processing the request based on the DMA operation queue to obtain request processing data;
the second determining module is used for determining virtual machine equipment corresponding to the address of the DMA operation queue based on the queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data;
and the return module is used for returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method according to the first aspect.
In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium having stored thereon a computer program for execution by a processor to implement the method of the first aspect.
In a fifth aspect, embodiments of the present disclosure also provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement a method as described in the first aspect.
The DMA operation queue management method, the device, the equipment and the readable storage medium provided by the embodiment of the disclosure are used for receiving a request sent by a central processing unit, wherein the request comprises a virtual machine equipment address, determining a DMA operation queue corresponding to the virtual machine equipment address based on a mapping table from equipment to queue, processing the request based on the DMA operation queue to obtain request processing data, determining a virtual machine equipment corresponding to the address of the DMA operation queue based on the mapping table from queue to equipment, adding the address of the virtual machine equipment to the request processing data, and returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment. Compared with the prior art, the embodiment of the disclosure manages the DMA operation queues by using the device-to-queue mapping table and the queue-to-device mapping table, wherein one mapping table is used for mapping the device-to-DMA operation, and the other mapping table is used for mapping the DMA operation to the device, so that the flexibility and manageability of the DMA operation are improved, the DMA operation queues are allocated by using the hardware configuration mapping table, the dependence on a CPU is reduced, and the system performance is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flowchart of a method for managing a DMA operation queue provided by an embodiment of the present disclosure;
FIG. 2 is a functional block diagram of a DMA operation queue management method provided by an embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for managing a DMA operation queue according to another embodiment of the present disclosure;
FIG. 4 is a flowchart of a method for managing a DMA operation queue according to another embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a device-to-queue mapping table circuit provided by an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a queue to device mapping table circuit provided by an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a DMA operation queue management apparatus according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
In computer systems, direct memory access (Direct Memory Access, DMA) is a technique that allows peripheral devices to exchange data directly with memory without processing by a central processing unit (Central Processing Unit, CPU). This allows the data transfer to be completed more quickly, thereby improving the overall performance of the system.
Existing solutions, which typically use a single mapping table or a simple one-to-many mapping relationship to allocate DMA operation queues to peripheral devices, require the use of hardware registers to set transfer parameters, such as target addresses and transfer lengths, and require the CPU to allocate DMA operation queues.
However, the existing method is a simple mapping allocation method, has poor flexibility and manageability, and the allocation of DMA operation queues depends on a CPU, so that when a plurality of DMA operations are processed, CPU resources are occupied relatively, and the system performance is affected. In view of this problem, embodiments of the present disclosure provide a DMA operation queue management method, which is described below with reference to specific embodiments.
FIG. 1 is a flowchart of a method for managing a DMA operation queue according to an embodiment of the present disclosure. The execution subject of the method is an electronic device. The electronic equipment can be portable mobile equipment such as smart phones, tablet computers, notebook computers, vehicle navigation equipment, intelligent sports equipment and the like; the system can also be a fixed device such as a personal computer, an intelligent household appliance, a server and the like, wherein the server can be a single server, can be a server cluster, and can be a distributed cluster or a centralized cluster. The method can be applied to the scene of managing the DMA operation queue and the scene of distributing the DMA operation queue. It can be appreciated that the DMA operation queue management method provided by the embodiment of the present disclosure may also be applied in other scenarios.
The DMA operation queue management method shown in fig. 1 is described below, and the method includes the following specific steps:
s101, receiving a request sent by a central processing unit, wherein the request comprises a virtual machine device address.
As shown in fig. 2, a virtual machine device (VM) sends a request through a Central Processing Unit (CPU), and an electronic device receives the request sent by the central processing unit, the request including a virtual machine device address.
S102, determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue.
As shown in fig. 2, the electronic device determines, through a device-to-queue mapping table (map_ftq), a DMA operation queue corresponding to the address of the virtual machine device, that is, the electronic device allocates, through the device-to-queue mapping table, a corresponding DMA operation queue to the virtual machine device.
Optionally, the device-to-queue mapping table is keyed by a device ID and the DMA operation queue ID is a value. When a device needs to be allocated to a DMA operation queue, only a correspondence between a device ID and a DMA operation queue ID needs to be added to the device-to-queue mapping table. Also, when a device needs to be removed from a DMA operation queue, only the data corresponding to the device needs to be deleted from the device-to-queue mapping table.
S103, processing the request based on the DMA operation queue to obtain request processing data.
After determining a DMA operation queue corresponding to the virtual machine equipment address, the electronic equipment processes the request based on the DMA operation queue to obtain request processing data of the request.
S104, determining virtual machine equipment corresponding to the address of the DMA operation queue based on the queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data.
As shown in fig. 2, the electronic device determines, through a queue-to-device mapping table (map_qtf), a virtual machine device corresponding to an address of the DMA operation queue, and adds the address of the virtual machine device to the request processing data.
Optionally, the queue to device mapping table is keyed by a DMA operation queue ID, with a device ID being a value. When a DMA operation queue needs to be allocated to a device, only a corresponding relationship between a DMA operation queue ID and a device ID needs to be added to the queue-to-device mapping table. Similarly, when a DMA operation queue needs to be removed, only the data corresponding to the DMA operation queue needs to be deleted in the queue-to-device mapping table.
And S105, returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
Further, the electronic device returns request processing data added with the address of the virtual machine device to the central processing unit, and the central processing unit determines the corresponding virtual machine device according to the address of the virtual machine device in the request processing data, and sends the request processing data to the virtual machine device to complete the request process.
In some embodiments, before the receiving the request sent by the central processing unit, the method further includes: initializing the device-to-queue mapping table.
And in the system starting stage, initializing and distributing the DMA operation queue, and setting a preset threshold value. Specifically, the device counter and the allocation counter are both reset to zero, and then serial pre-allocation operation is carried out on the virtual machine device according to the threshold value respectively until all allocation is completed
In some embodiments, initializing the device-to-queue mapping table includes: and pre-distributing the DMA operation queue according to the virtual machine equipment to obtain a mapping table from the pre-distributed equipment to the queue.
Optionally, the pre-allocating the DMA operation queue according to the virtual machine device to obtain a mapping table from the pre-allocated device to the queue, including the following steps:
s1, zeroing a device counter and an allocation counter, and emptying a mapping table from the device to a queue;
s2, judging whether the equipment counter is larger than or equal to a preset threshold value, if so, executing S4, otherwise, executing S3;
s3, if the equipment counter is smaller than a preset threshold value, the current DMA operation queue is distributed to virtual machine equipment, and the equipment counter is incremented by one;
s4, if the equipment counter is larger than or equal to a preset threshold value, writing a DMA operation queue address, adding one to the writing address, and adding one to the distribution counter;
s5, judging whether the DMA operation queue pre-allocation is completed or not;
s6, if the DMA operation queue pre-allocation is completed, obtaining a pre-allocated device-to-queue mapping table.
The method comprises the steps of receiving a request sent by a central processing unit, determining a DMA operation queue corresponding to the address of the virtual machine equipment based on a mapping table from equipment to queue, processing the request based on the DMA operation queue to obtain request processing data, determining virtual machine equipment corresponding to the address of the DMA operation queue based on a mapping table from queue to equipment, adding the address of the virtual machine equipment to the request processing data, and returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment. Compared with the prior art, the embodiment of the disclosure manages the DMA operation queues by using the device-to-queue mapping table and the queue-to-device mapping table, wherein one mapping table is used for mapping the device-to-DMA operation, and the other mapping table is used for mapping the DMA operation to the device, so that the flexibility and manageability of the DMA operation are improved, the DMA operation queues are allocated by using the hardware configuration mapping table, the dependence on a CPU is reduced, and the system performance is improved.
FIG. 3 is a flowchart of a method for managing a DMA operation queue according to another embodiment of the present disclosure, as shown in FIG. 3, the method includes the following steps:
s201, receiving a request sent by a central processing unit, wherein the request comprises a virtual machine device address.
Specifically, the implementation process and principle of S201 and S101 are consistent, and will not be described herein.
S202, judging whether a release pointer operation or an allocation pointer operation exists currently.
In this step, the electronic device determines whether it is currently an allocation pointer operation (alloc) or a release pointer operation (free).
S203, if no pointer operation is released and no pointer operation is allocated at present, setting a read address as a relative address of the current equipment, and reading out the address of the DMA operation queue in real time.
Fig. 5 is a schematic diagram of a device-to-queue mapping table circuit provided in an embodiment of the present disclosure, and as shown in fig. 5, the device-to-queue mapping table (map_ftq) circuit is composed of a DPA-RAM (Dual-Port Asynchronous RAM), a three-way selector (MUX 3), and an or gate. When there is no DMA operation queue allocation pointer operation (alloc) or release pointer operation (free), the read state is maintained, the read address is set as the current device relative address (func_addr), and the DMA operation queue address (que _out) is read out in real time.
S204, if the pointer allocation operation exists currently, writing the allocated DMA operation queue address into the relative address of the current equipment.
As shown in fig. 5, when the DMA operation queue allocation pointer operation (alloc) is performed, the allocated DMA operation queue address (que _in) is written in the current device relative address (func_addr).
S205, if the release pointer operation is currently performed, writing zero into the relative address of the current equipment.
As shown in fig. 5, when the DMA operation queue release pointer operation is performed, 0 is written in the current device relative address (func_addr).
S206, processing the request based on the DMA operation queue to obtain request processing data.
Specifically, the implementation process and principle of S206 and S103 are consistent, and will not be described herein.
S207, determining virtual machine equipment corresponding to the address of the DMA operation queue based on a queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data.
Specifically, the implementation process and principle of S207 and S104 are identical, and will not be described herein.
And S208, returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
Specifically, the implementation process and principle of S208 and S105 are identical, and will not be described herein.
The embodiment of the disclosure judges whether a pointer releasing operation or a pointer distributing operation exists currently or not by receiving a request sent by a central processing unit, wherein the request comprises a virtual machine equipment address. Further, if no pointer operation is released and no pointer operation is allocated at present, setting a read address as a relative address of the current equipment, and reading out a DMA operation queue address in real time; if the pointer operation is currently allocated, writing the allocated DMA operation queue address into the relative address of the current equipment; and if the release pointer operation is currently performed, writing zero into the relative address of the current equipment. And then, processing the request based on the DMA operation queue to obtain request processing data, determining virtual machine equipment corresponding to the address of the DMA operation queue based on a mapping table from the queue to the equipment, and adding the address of the virtual machine equipment into the request processing data. And then, the request processing data added with the address of the virtual machine equipment is returned to the central processing unit, so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment. Compared with the prior art, the embodiment of the disclosure manages the DMA operation queues by using the device-to-queue mapping table and the queue-to-device mapping table, wherein one mapping table is used for mapping the device-to-DMA operation, and the other mapping table is used for mapping the DMA operation to the device, so that the flexibility and manageability of the DMA operation are improved, the DMA operation queues are allocated by using the hardware configuration mapping table, the dependence on a CPU is reduced, and the system performance is improved. And, support dynamically allocating and reclaiming DMA operation queues to accommodate a large or varying DMA operation demand.
FIG. 4 is a flowchart of a method for managing a DMA operation queue according to another embodiment of the present disclosure, as shown in FIG. 4, the method includes the following steps:
s301, receiving a request sent by a central processing unit, wherein the request comprises a virtual machine device address.
Specifically, the implementation process and principle of S301 and S101 are identical, and will not be described herein.
S302, determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue.
Specifically, the implementation process and principle of S302 and S102 are consistent, and will not be described herein.
S303, processing the request based on the DMA operation queue to obtain request processing data.
Specifically, the implementation process and principle of S303 and S103 are identical, and will not be described herein.
S304, judging whether a release pointer operation or an allocation pointer operation exists currently.
In this step, the electronic device determines whether it is currently an allocation pointer operation (alloc) or a release pointer operation (free).
S305, if no pointer operation is released currently and no pointer operation is allocated, setting a read address as a current DMA operation queue address, and reading out the relative address of the device in real time.
Fig. 6 is a schematic diagram of a queue to device mapping table circuit provided in an embodiment of the present disclosure, and as shown in fig. 6, the queue to device mapping table (map_qtf) circuit is composed of a DPA-RAM (Dual-Port Asynchronous RAM), a two-way selector (MUX 2), and an or gate. When there is no DMA operation queue allocation pointer operation (alloc) or release pointer operation (free), the read state is maintained, the read address is set to the current operation queue address (que _out), and the device relative address (func_addr) is read out in real time.
S306, if the pointer allocation operation exists currently, writing the allocated relative address of the equipment into the current DMA operation queue address.
As shown in fig. 6, when the DMA operation queue allocation pointer operation (alloc) is performed, the current DMA operation queue address (que _in) is written with the allocated device relative address (func_in) as a write address.
S307, if the release pointer operation exists currently, zero is written into the current DMA operation queue address.
As shown in fig. 6, when a DMA operation queue release operation is performed, 0 is written in the current operation queue address (que _in).
S308, adding the address of the virtual machine equipment to the request processing data.
S309, returning request processing data added with the address of the virtual machine device to the central processing unit, so that the central processing unit sends the request processing data to the virtual machine device corresponding to the address of the virtual machine device.
Specifically, the implementation process and principle of S308 and S105 are consistent, and will not be described herein.
According to the embodiment of the disclosure, a request sent by a central processing unit is received, the request comprises a virtual machine equipment address, a DMA operation queue corresponding to the virtual machine equipment address is determined based on a mapping table from equipment to the queue, and the request is processed based on the DMA operation queue, so that request processing data is obtained. Further, judging whether a release pointer operation or an allocation pointer operation exists at present, if no release pointer operation exists at present and no allocation pointer operation exists at present, setting a read address as a current DMA operation queue address, and reading out the relative address of the equipment in real time; if the pointer operation is currently allocated, writing the allocated relative address of the equipment into the current DMA operation queue address; and if the release pointer operation exists currently, writing zero into the current DMA operation queue address. Then, the address of the virtual machine device is added to the request processing data. And then, the request processing data added with the address of the virtual machine equipment is returned to the central processing unit, so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment. Compared with the prior art, the embodiment of the disclosure manages the DMA operation queues by using the device-to-queue mapping table and the queue-to-device mapping table, wherein one mapping table is used for mapping the device-to-DMA operation, and the other mapping table is used for mapping the DMA operation to the device, so that the flexibility and manageability of the DMA operation are improved, the DMA operation queues are allocated by using the hardware configuration mapping table, the dependence on a CPU is reduced, and the system performance is improved. And, support dynamically allocating and reclaiming DMA operation queues to accommodate a large or varying DMA operation demand.
Fig. 7 is a schematic structural diagram of a DMA operation queue management apparatus according to an embodiment of the present disclosure. The DMA operation queue management apparatus may be an electronic device as described in the above embodiments, or the DMA operation queue management apparatus may be a part or component in the electronic device. The DMA operation queue management apparatus provided in the embodiment of the present disclosure may execute the processing flow provided in the DMA operation queue management method embodiment, as shown in fig. 7, the DMA operation queue management apparatus 40 includes: a receiving module 41, a first determining module 42, an obtaining module 43, a second determining module 44, a returning module 45; the receiving module 41 is configured to receive a request sent by the central processing unit, where the request includes a virtual machine device address; the first determining module 42 is configured to determine a DMA operation queue corresponding to the virtual machine device address based on a device-to-queue mapping table; the obtaining module 43 is configured to process the request based on the DMA operation queue, and obtain request processing data; the second determining module 44 is configured to determine, based on a queue-to-device mapping table, a virtual machine device corresponding to an address of the DMA operation queue, and add the address of the virtual machine device to the request processing data; the return module 45 is configured to return, to the central processing unit, request processing data for adding an address of the virtual machine device, so that the central processing unit sends the request processing data to a virtual machine device corresponding to the address of the virtual machine device.
Optionally, the DMA operation queue management apparatus 40 further includes an initialization module 46; the initialization module 46 is used to initialize the device-to-queue mapping table.
Optionally, when the initializing module 46 initializes the device-to-queue mapping table, the initializing module is specifically configured to: and pre-distributing the DMA operation queue according to the virtual machine equipment to obtain a mapping table from the pre-distributed equipment to the queue.
Optionally, the initialization module 46 is specifically configured to, when pre-allocating the DMA operation queue according to the virtual machine device to obtain a pre-allocated device-to-queue mapping table: zeroing the device counter and the allocation counter, and emptying a mapping table from the device to the queue; judging whether the equipment counter is larger than or equal to a preset threshold value; if the device counter is smaller than the preset threshold, the current DMA operation queue is distributed to the virtual machine device, and the device counter is incremented by one; if the equipment counter is larger than or equal to a preset threshold value, writing a DMA operation queue address, adding one to the writing address, and adding one to the distribution counter; judging whether the DMA operation queue pre-allocation is completed or not; and if the DMA operation queue pre-allocation is completed, obtaining a pre-allocated device-to-queue mapping table.
Optionally, when the first determining module 42 determines, based on the device-to-queue mapping table, a DMA operation queue corresponding to the virtual machine device address, the method is specifically configured to: judging whether a release pointer operation or an allocation pointer operation exists at present; if no pointer operation is released and no pointer operation is allocated at present, setting a read address as the relative address of the current equipment, and reading the address of the DMA operation queue in real time; if the pointer operation is currently allocated, writing the allocated DMA operation queue address into the relative address of the current equipment; and if the release pointer operation is currently performed, writing zero into the relative address of the current equipment.
Optionally, when the second determining module 44 determines, based on the queue-to-device mapping table, a virtual machine device corresponding to an address of the DMA operation queue, the second determining module is specifically configured to: judging whether a release pointer operation or an allocation pointer operation exists at present; if no pointer operation is released and no pointer operation is allocated at present, setting a read address as a current DMA operation queue address, and reading out the relative address of the equipment in real time; if the pointer operation is currently allocated, writing the allocated relative address of the equipment into the current DMA operation queue address; and if the release pointer operation exists currently, writing zero into the current DMA operation queue address.
The DMA operation queue management apparatus of the embodiment shown in fig. 7 may be used to implement the technical solution of the above method embodiment, and its implementation principle and technical effects are similar, and will not be described herein again.
Fig. 8 is a schematic structural diagram of an electronic device in an embodiment of the disclosure. Referring now in particular to fig. 8, a schematic diagram of an electronic device 600 suitable for use in implementing embodiments of the present disclosure is shown. The electronic device shown in fig. 8 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 8, the electronic device 600 may include a processing means (e.g., a central processing unit, a graphic processor, etc.) 601 that may perform various suitable actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603 to implement a DMA operation queue management method according to an embodiment of the present disclosure. In the RAM 603, various programs and data required for the operation of the electronic apparatus 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
In general, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, magnetic tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. While fig. 8 shows an electronic device 600 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program containing program code for performing the method shown in the flowchart, thereby implementing the DMA operation queue management method as described above. In such an embodiment, the computer program may be downloaded and installed from a network via communication means 609, or from storage means 608, or from ROM 602. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 601.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
In some implementations, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol ), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the internet (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to:
receiving a request sent by a central processing unit, wherein the request comprises a virtual machine equipment address;
determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue;
processing the request based on the DMA operation queue to obtain request processing data;
determining virtual machine equipment corresponding to the address of the DMA operation queue based on a queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data;
and returning request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
Alternatively, the electronic device may perform other steps described in the above embodiments when the above one or more programs are executed by the electronic device.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including, but not limited to, an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).
Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (10)
1. A method for managing a DMA operation queue, the method comprising:
receiving a request sent by a central processing unit, wherein the request comprises a virtual machine equipment address;
determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue;
processing the request based on the DMA operation queue to obtain request processing data;
determining virtual machine equipment corresponding to the address of the DMA operation queue based on a queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data;
and returning request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
2. The method of claim 1, wherein prior to receiving the request sent by the central processor, the method further comprises:
initializing the device-to-queue mapping table.
3. The method of claim 2, wherein initializing the device-to-queue mapping table comprises:
and pre-distributing the DMA operation queue according to the virtual machine equipment to obtain a mapping table from the pre-distributed equipment to the queue.
4. The method of claim 3, wherein the pre-allocating the DMA operation queues according to the virtual machine device, to obtain a pre-allocated device-to-queue mapping table, comprises:
zeroing the device counter and the allocation counter, and emptying a mapping table from the device to the queue;
judging whether the equipment counter is larger than or equal to a preset threshold value;
if the device counter is smaller than the preset threshold, the current DMA operation queue is distributed to the virtual machine device, and the device counter is incremented by one;
if the equipment counter is larger than or equal to a preset threshold value, writing a DMA operation queue address, adding one to the writing address, and adding one to the distribution counter;
judging whether the DMA operation queue pre-allocation is completed or not;
and if the DMA operation queue pre-allocation is completed, obtaining a pre-allocated device-to-queue mapping table.
5. The method of claim 1, wherein the determining the DMA operation queue corresponding to the virtual machine device address based on the device-to-queue mapping table comprises:
judging whether a release pointer operation or an allocation pointer operation exists at present;
if no pointer operation is released and no pointer operation is allocated at present, setting a read address as the relative address of the current equipment, and reading the address of the DMA operation queue in real time;
if the pointer operation is currently allocated, writing the allocated DMA operation queue address into the relative address of the current equipment;
and if the release pointer operation is currently performed, writing zero into the relative address of the current equipment.
6. The method of claim 1, wherein the determining, based on the queue-to-device mapping table, a virtual machine device to which the address of the DMA operation queue corresponds comprises:
judging whether a release pointer operation or an allocation pointer operation exists at present;
if no pointer operation is released and no pointer operation is allocated at present, setting a read address as a current DMA operation queue address, and reading out the relative address of the equipment in real time;
if the pointer operation is currently allocated, writing the allocated relative address of the equipment into the current DMA operation queue address;
and if the release pointer operation exists currently, writing zero into the current DMA operation queue address.
7. A DMA operation queue management apparatus, the apparatus comprising:
the receiving module is used for receiving a request sent by the central processing unit, wherein the request comprises a virtual machine equipment address;
the first determining module is used for determining a DMA operation queue corresponding to the virtual machine equipment address based on the mapping table from the equipment to the queue;
the obtaining module is used for processing the request based on the DMA operation queue to obtain request processing data;
the second determining module is used for determining virtual machine equipment corresponding to the address of the DMA operation queue based on the queue-to-equipment mapping table, and adding the address of the virtual machine equipment into the request processing data;
and the return module is used for returning the request processing data added with the address of the virtual machine equipment to the central processing unit so that the central processing unit sends the request processing data to the virtual machine equipment corresponding to the address of the virtual machine equipment.
8. The apparatus of claim 7, wherein the apparatus further comprises:
and the initialization module is used for initializing the mapping table from the equipment to the queue.
9. An electronic device, comprising:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-6.
10. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method according to any of claims 1-6.
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