CN117806862A - Data consistency processing unit and functional chip - Google Patents
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Abstract
The application discloses a data consistency processing unit, includes: the data processing unit is used for sending the action instruction to the corresponding functional module and sending the action execution data to the memory; the address processing unit is used for detecting whether the data in the cache is consistent with the data at the corresponding address of the memory according to the read request of the functional module for executing the data of the corresponding action, and when the data is inconsistent with the data, the data processing unit is controlled to send the completely read data to the functional module after the data processing unit completely reads the data in the cache; and when the data are consistent, the data processing unit controls the memory to send corresponding data to the functional module. The data consistency processing unit can enable the data called by each functional module according to the instruction of the processor to be consistent with the control intention of the processor.
Description
Technical Field
The present disclosure relates generally to the field of integrated circuits, and more particularly, to a data consistency processing unit and a functional chip.
Background
In a large-scale integrated circuit, a plurality of functional modules controlled by a processor are generally integrated, and the control mechanism is generally as follows: the processor sends a specific instruction to the corresponding functional module and sends corresponding data to the memory, and the functional module reads the data at the corresponding position of the memory according to the instruction so as to complete the corresponding action. To improve the access performance of the chip, the cache is often used as a data exchange space between the processor and the memory. The processor outputs the data quickly to the cache and then outputs the data relatively slowly from the cache to the memory. Therefore, when the processor needs to access the data in the memory, the processor only needs to check whether the data is cached in the cache, and if the data corresponds to the cache, the data can be directly read, so that the time delay of reading the data from the memory is avoided, and the response speed and the operation efficiency of the system are improved. Meanwhile, data transmission between the processor and the memory is reduced, and the overall energy consumption of the chip can be reduced. However, since the cache memory requires a relatively long time in updating the data output by the processor to the memory. Therefore, when the function module calls data from the memory according to the corresponding instruction of the processor, the updated data may not be obtained, and the action performed by the function module after obtaining the data which is not updated may not be consistent with the control intention of the processor. It has become a major issue in the art how to keep the data called by the functional modules of the chip with the cache consistent with the control intent of the processor according to the instruction of the processor.
Disclosure of Invention
In view of the above-described drawbacks or shortcomings in the prior art, it is desirable to provide a data consistency processing unit that can make data called by each functional module according to a processor instruction consistent with the control intention of the processor.
The specific technical scheme is as follows:
first aspect
The application provides a data consistency processing unit, comprising:
the data processing unit is respectively connected with the cache, each functional module and the memory, and is used for sending action instructions to the corresponding functional modules and sending action execution data to the memory, wherein the action instructions and the action execution data are both generated by the processor and sent to the data processing unit through the cache, and the functional modules can execute corresponding actions according to the action execution data;
an address processing unit, which is respectively connected with the cache, each functional module and the data processing unit and is used for detecting whether the data in the cache is consistent with the data under the corresponding address of the memory according to the read request of the functional module to the corresponding action execution data,
when the data is inconsistent, after the data processing unit completely reads the data in the cache, controlling the data processing unit to send the completely read data to the functional module;
and when the data are consistent, the data processing unit controls the memory to send corresponding data to the functional module.
As a further definition of the present application, the address processing unit includes:
the module request arbitration unit is used for judging the priority of the read requests sent by a plurality of functional modules at the same time and sending a probe request to the cache according to the read request with the highest priority;
a bus request arbitration unit for alternately granting a write request from the processor to the memory and a read request from the functional module to the memory;
and the request queue management unit is used for receiving the probe result returned by the cache and judging whether the data in the cache is consistent with the data at the corresponding address of the memory.
As a further definition of the present application, the data processing unit comprises:
the data gating unit is used for acquiring action execution data output by the cache and writing the action execution data into the memory according to the alternate authorization result of the bus request arbitration unit to the write request and the read request, or sending the action execution data to the corresponding functional module, or controlling the memory to send the action execution data to the corresponding functional module;
and the data transmitting unit is used for receiving the action execution data transmitted by the data gating unit and transmitting the action execution data to the memory or the functional module, and is used for receiving a control instruction transmitted by the data gating unit and controlling the memory to transmit the action execution data to the corresponding functional module.
As a further definition of the present application, it further comprises:
the processor interface unit is connected among the cache, the address processing unit and the data processing unit and is used for realizing data interaction among the cache, the address processing unit and the data processing unit;
and the on-chip bus interface unit is connected among the address processing unit, the data processing unit, each functional module and the memory and is used for realizing data interaction among the four.
As a further definition of the present application, the on-chip bus interface unit employs an AXI or AHB standardized bus.
Second aspect
The application provides a functional chip including the data consistency processing unit as described above, further including: a processor, a cache, functional modules and a memory.
The beneficial effects of the application are that:
in this scheme, when the processor needs to control the functional module to perform a corresponding action, the processor sends the action instruction to the corresponding functional module through the cache, the processor interface unit, the data processing unit and the on-chip bus interface unit, and sends data applied to the execution of the action to the memory through the cache, the processor interface unit, the data processing unit and the on-chip bus interface unit, and when the functional module needing to execute the action needs to acquire the execution data of the action according to the action instruction, the functional module sends a first data acquisition request to the data consistency processing unit, the request is transmitted to the address processing unit through the on-chip bus interface unit, and the address processing unit sends a probe request to the cache according to the first data acquisition request through the processor interface unit, so as to probe whether the data in the cache is updated data, and when the data is updated data, the data in the memory is old data which is not updated. At this time, the address processing unit sends a second data acquisition request to the data processing unit, and the data processing unit judges the action execution data sent from the cache according to the second data acquisition request to determine whether it is completely sent. After judging that the action execution data is completely sent to the data processing unit, the data processing unit sends the action execution data to the functional module through the on-chip bus interface unit according to the second data acquisition request, and the functional module is used for executing corresponding actions. When the data in the cache after being probed is the data which is not updated, the cache is indicated to completely write the action execution data into the memory, at the moment, the address processing unit sends a third data acquisition request to the data processing unit, the data processing unit sends a fourth data acquisition request to the memory through the on-chip bus interface unit according to the third data acquisition request, and the memory sends corresponding action execution data to the functional module through the on-chip bus interface unit according to the fourth data acquisition request, so that the functional module executes corresponding actions. Compared with the prior art, the scheme can enable the functional module to execute data according to the actions finally, execute corresponding actions and be consistent with the control intention of the processor.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
fig. 1 is a schematic diagram of an internal connection structure of a chip with a data consistency processing unit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an internal connection structure of the address processing unit in FIG. 1;
fig. 3 is a schematic diagram of an internal connection structure of the data processing unit in fig. 1.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, a data consistency processing unit 101 provided in this embodiment, as shown in fig. 1, mainly includes: an address processing unit 1011, a data processing unit 1012, a processor interface unit 1013, and an on-chip bus interface unit 1014.
The data coherency handling unit 101 performs cache coherency management for access to memory data in a system chip, this embodiment provides a flexible and easily scalable data processing architecture for issuing access requests (requests to write or read data) initiated on the processor core 1016 and functional module 1018 to memory 1019 on an on-chip bus and allowing probing whether data in cache 1017 in processor unit 1015 has been completely written into memory 1019, thereby enabling hardware to automatically maintain data coherency between different modules and caches.
The address processing unit 1011 is responsible for performing priority arbitration and queue management of access sequences for data access requests initiated by the processor units (cpu processor 1016 and cache 1017) and the functional modules, and mainly includes, as shown in fig. 2: a module request arbitration unit 201, a bus request arbitration unit 202, and a request queue management unit 203.
The module request arbitration unit 201 is configured to determine the priority of the access address request initiated by each functional module. When multiple functional modules (such as DMA, ethernet, compute engine, high speed transmission interface, etc.) in fig. 2 compete for memory access rights at the same time, the address processing unit 1011 processes access requests of only one functional module at a time in consideration of the requirement of data consistency. The module request arbitration unit 201 determines the priority of each function module access request using a variety of factors including the amount of requested access data, the longest waiting time, the latest grant time, or the like. The module request arbitration unit 201 uses an anti-starvation algorithm to ensure that when a functional module which does not obtain access right after the secondary priority is judged, if a large data volume access requirement exists, the priority of the functional module can be correspondingly improved, so that the situation that the access right cannot be obtained for a long time is avoided.
The bus request arbitration unit 202 is used to coordinate new requests into the on-chip bus interface unit 1014 to generate access queues. Considering that the bus on the chip for connecting the memory 1019 and the data processing unit 1012 operates most efficiently in the case of continuously transmitting one access request, the bus request arbitration unit 202 is used to alternately grant write or read requests from the cache and the functional module when the cache 1017 and the functional module 1018 simultaneously initiate write or read requests to the memory 1019. If the new request has a higher priority than the ongoing request, the higher priority request may interrupt the current ongoing request.
The request queue management unit 203 is configured to receive data read or write requests with higher priority arbitrated by the bus request arbitration unit 202, and for each data read request, the request queue management unit 203 is further configured to make a determination as to whether data corresponding to the request is completely written into the memory 1019.
To meet data coherency requirements, request queue management unit 203 enforces coherency processing operations on access requests to memory 1019 that are marked as probed or that the processor may cache.
The data processing unit 1012 is responsible for arbitrating, gating and sending data sent by the processor and the various modules, and mainly includes, as shown in fig. 3: a data strobe unit 301 and a data transmission unit 302.
As shown in fig. 3, the data strobe unit 301 is configured to acquire data to be read by the function module having the highest current priority in the memory 1019, and send it to the data transmission unit 302. The data sending unit 302 is responsible for sending the data to the on-chip bus interface unit 1014, and is acquired by the function module 1018 with the highest current priority. For a write access request of the cache 1017 to the memory 1019, the data strobe unit 301 is configured to receive data to be written to the memory 1019, and the data transmitting unit 302 is responsible for transmitting the data onto the on-chip bus interface unit 1014, and obtaining the data from the memory 1019.
The processor interface unit 1013 is responsible for processing address data of access requests to the memory 1019 while managing queuing of the respective access requests. The processor interface unit 1013 has a buffer provided therein for receiving write request data initiated from the processor and read request data initiated by the functional module. If a cache hit occurs, the data is sent to the on-chip bus interface unit 1014 through the data processing unit 1012. The buffer is also used for receiving the read request data initiated by the processor and the write request data initiated by the functional module, and forwarding the data from the on-chip bus interface unit 1014 to the processor if a cache hit occurs.
The on-chip bus interface unit 1014 is responsible for interfacing to the bus interface on the memory 1019, and its bidirectional interworking function may forward access requests from the functional module 1018 and the coherence processing unit 101, and may employ standardized buses such as AXI/AHB to compromise flexibility and protocol specifications.
The workflow of the data consistency processing method is as follows:
the first step: starting a data access request, requesting the function module to enter a second step, and requesting the processor unit to enter a third step;
and a second step of: the module request arbitration unit 201 arbitrates the simultaneous function module requests, and the module obtaining the access right enters a third step, and in order to ensure the consistency of the data, the request performs cache probing to determine whether the data in the cache is hit;
and a third step of: the bus request arbitration unit 202 arbitrates the processor request and the function module request (the prior arbitration access right is obtained) which occur simultaneously, and the request for obtaining the access right enters a request queue for queuing;
fourth step: the request queue initiates a request processing operation, the function module requests to enter a fifth step, and the processor unit requests to enter a tenth step;
fifth step: when the request is data read access and the cache is searched for hit, the sixth step is entered;
when the request is data read access and the cache is in a probe miss, entering a seventh step;
when the request is data write access and the cache is searched for a hit, the eighth step is entered;
when the request is data write access and the cache probe is not hit, entering a ninth step;
sixth step: the access data address is in the cache, and the read cache data is returned to the requester;
seventh step: the read bus data is directly returned to the requesting party;
eighth step: the access data address is in the cache, the data is updated to the cache, and then the ninth step is carried out;
ninth step: writing the data directly to the bus;
tenth step: when the request is data read access, entering a seventh step;
if the request is a data write access, the ninth step is entered.
The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Claims (6)
1. A data consistency processing unit, comprising:
the data processing unit is respectively connected with the cache, each functional module and the memory, and is used for sending action instructions to the corresponding functional modules and sending action execution data to the memory, wherein the action instructions and the action execution data are both generated by the processor and sent to the data processing unit through the cache, and the functional modules can execute corresponding actions according to the action execution data;
an address processing unit, which is respectively connected with the cache, each functional module and the data processing unit and is used for detecting whether the data in the cache is consistent with the data under the corresponding address of the memory according to the read request of the functional module to the corresponding action execution data,
when the data is inconsistent, after the data processing unit completely reads the data in the cache, controlling the data processing unit to send the completely read data to the functional module;
and when the data are consistent, the data processing unit controls the memory to send corresponding data to the functional module.
2. The data consistency processing unit according to claim 1, wherein the address processing unit comprises:
the module request arbitration unit is used for judging the priority of the read requests sent by a plurality of functional modules at the same time and sending a probe request to the cache according to the read request with the highest priority;
a bus request arbitration unit for alternately granting a write request from the processor to the memory and a read request from the functional module to the memory;
and the request queue management unit is used for receiving the probe result returned by the cache and judging whether the data in the cache is consistent with the data at the corresponding address of the memory.
3. The data consistency processing unit of claim 1, wherein the data processing unit comprises:
the data gating unit is used for acquiring action execution data output by the cache and writing the action execution data into the memory according to the alternate authorization result of the bus request arbitration unit to the write request and the read request, or sending the action execution data to the corresponding functional module, or controlling the memory to send the action execution data to the corresponding functional module;
and the data transmitting unit is used for receiving the action execution data transmitted by the data gating unit and transmitting the action execution data to the memory or the functional module, and is used for receiving a control instruction transmitted by the data gating unit and controlling the memory to transmit the action execution data to the corresponding functional module.
4. The data consistency processing unit of claim 1, further comprising:
the processor interface unit is connected among the cache, the address processing unit and the data processing unit and is used for realizing data interaction among the cache, the address processing unit and the data processing unit;
and the on-chip bus interface unit is connected among the address processing unit, the data processing unit, each functional module and the memory and is used for realizing data interaction among the four.
5. The data coherency handling unit of claim 4, wherein the on-chip bus interface unit employs an AXI or AHB standardized bus.
6. A functional chip comprising a data consistency processing unit according to any of claims 1-5, further comprising: a processor, a cache, functional modules and a memory.
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| CN202311633214.8A CN117806862A (en) | 2023-11-30 | 2023-11-30 | Data consistency processing unit and functional chip |
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| CN202311633214.8A CN117806862A (en) | 2023-11-30 | 2023-11-30 | Data consistency processing unit and functional chip |
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