CN117806712A - Instruction processing method, apparatus, computer device and storage medium - Google Patents

Abstract

The embodiment of the application provides an instruction processing method, an instruction processing device, computer equipment and a storage medium, and relates to the field of processors. The instruction processing method comprises the following steps: reading instructions from a memory; fully decoding the read instruction, and judging whether the current instruction is a double-emission instruction or not; and when the current instruction is a double-emission instruction, executing two instructions simultaneously. The instruction processing method improves the concurrency of the processor on the basis of reducing the pipeline.

Description

Instruction processing method, apparatus, computer device and storage medium

Technical Field

The present disclosure relates to the field of processor technologies, and in particular, to an instruction processing method, an apparatus, a computer device, and a storage medium.

Background

Modern processor technology often employs pipeline technology in order to maximize operating frequency and performance. Such as five-stage pipelining. Wherein each stage in the five-stage pipeline technology is responsible for executing part of the contents of one instruction.

However, in a classical five-stage pipeline architecture, it is not suitable for small processors due to the larger area consumption and more dynamic power consumption caused by the longer pipeline.

Disclosure of Invention

The embodiment of the application provides an instruction processing method, an instruction processing device, computer equipment and a storage medium.

In a first aspect of an embodiment of the present application, there is provided an instruction processing method, including: reading instructions from a memory; fully decoding the read instruction, and judging whether the current instruction is a double-emission instruction or not; and when the current instruction is a double-emission instruction, executing two instructions simultaneously.

In an optional embodiment of the present application, the determining whether the current instruction is a dual-issue instruction includes: when the current instruction is a general operation instruction, the current instruction is a double-emission instruction.

In an alternative embodiment of the present application, the method further comprises: and executing an instruction when the current instruction is a non-dual-emission instruction.

In an alternative embodiment of the present application, the non-dual emission instruction includes: multiplication instructions, division instructions, floating point operation instructions, and memory access instructions.

In an alternative embodiment of the present application, the method further comprises: multiple instructions are executed simultaneously in the same execution cycle.

In an alternative embodiment of the present application, the method further comprises: after executing the plurality of instructions, performing a write-back operation.

In an alternative embodiment of the present application, the method further comprises: when fully decoding a read instruction, multiple instructions are decoded.

In a second aspect of embodiments of the present application, there is provided an instruction processing apparatus, the apparatus including: a reading module for reading instructions from the memory; the decoding module is used for fully decoding the read instruction and judging whether the current instruction is a double-emission instruction or not; and the execution module is used for executing two instructions simultaneously when the current instruction is a double-emission instruction.

In a third aspect of embodiments of the present application, there is provided a computer device comprising: comprising a memory storing a computer program and a processor implementing the steps of any of the methods described above when the processor executes the computer program.

In a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of the above.

The embodiment of the application provides an instruction processing method. By reducing the five-stage pipeline into three-stage pipelines, each stage of pipeline respectively processes different fragment tasks, thereby removing useless logic in functions, reducing the pipeline means less resource requirements and also means less logic dynamic power consumption, thereby obviously reducing the chip area and the control power consumption to meet the requirements of area and power consumption in practical application; the three-level pipeline architecture provided by the embodiment of the application can support the emission of two instructions at a time, namely, the instruction execution unit has two similar pipelines, so that the processor can execute two instructions of specified types, the high concurrency of the processor is obviously improved, and the execution speed of an instruction stream is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic architecture diagram of a classical five-stage pipeline provided in one embodiment of the present application;

FIG. 2 is a flow chart of a method of instruction processing provided in one embodiment of the present application;

FIG. 3 is a pipeline architecture corresponding to an instruction processing method according to one embodiment of the present application;

FIG. 4 is a schematic diagram of an instruction processing apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

In the process of implementing the present application, the inventor finds that the current classical five-stage pipeline is shown in fig. 1, and includes a IF (Instruction Fetch) instruction fetch module, a ID (Instruction Decode) instruction decode module, a EX (Instruction Execute) instruction execution module, a MEM (Memory Access) memory access module and a WB (Write Back) write-back module, where IF refers to a process of reading an instruction from a memory; ID refers to the process of translating the instruction fetched from the memory, and after decoding, the index of the operand register required by the instruction is obtained, and the operand can be read out from the general register group by using the index; EX refers to the process of actually performing an operation on an instruction, for example, if the instruction is an add instruction, then the operation is performed on an operand, and if the instruction is a subtract instruction, then the operation is performed on an operand; MEM refers to the process of a memory access instruction to read data from or write data to a memory; WB refers to the process of writing back the result of instruction execution into the general register set, and if it is a normal operation instruction, the result value comes from the result of "execute" stage calculation; in the case of a memory read instruction, the result is from data read from memory during the "memory access" phase.

The above is a classical five-stage pipeline workflow, and part of the instruction life cycle goes through the five-stage pipeline, or four stages of the five stages (some instructions do not require WB and some instructions do not require MEM).

However, the classical pipeline described above suffers from significant drawbacks: first, since there are only 1 pipeline, at most 1 instruction can be executed in a single cycle, and the processor performance is extremely limited. Second, longer pipelines result in greater area consumption and more dynamic power consumption, which is not appropriate for some small processors.

In view of the foregoing, an embodiment of the present application provides an instruction processing method. By reducing the five-stage pipeline into three-stage pipelines, each stage of pipeline respectively processes different fragment tasks, thereby removing useless logic in functions, reducing the pipeline means less resource requirements and also means less logic dynamic power consumption, thereby obviously reducing the chip area and the control power consumption to meet the requirements of area and power consumption in practical application; the three-level pipeline architecture provided by the embodiment of the application can support the emission of two instructions at a time, namely, the instruction execution unit has two similar pipelines, so that the processor can execute two instructions of specified types, the high concurrency of the processor is obviously improved, and the execution speed of an instruction stream is improved.

The solutions in the embodiments of the present application may be implemented in various computer languages, for example, object-oriented programming language Java, and an transliterated scripting language JavaScript, etc.

In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.

Referring to fig. 2, the instruction processing method provided in the embodiment of the present application includes the following steps:

step 201, reading instructions from a memory.

Typically, instructions are the basic elements of a program that tell the processor that those operations should be performed. An instruction needs to be fetched from memory before it can be processed. In this embodiment of the present application, the reading instruction from the memory mainly includes:

IF0: the instruction is prefetched, a plurality of instructions can be obtained from a memory during prefetching, the complete instructions are cut according to the instruction length, and meanwhile, the instruction pre-decoding is finished, so that information is provided for branch jump.

In the embodiment of the application, the prefetching, slicing and pre-decoding of the instruction are completed through the IF0, and a basis is provided for subsequent full decoding and execution.

Step 202, performing full decoding on the read instruction, and judging whether the current instruction is a dual-emission instruction.

Typically, the processor decodes the instruction before it is executed, which extracts information carried in the instruction, which the processor uses to control subsequent pipelines to execute the instruction, and to determine the operations and associated data that need to be performed, which requires some time and may be a performance bottleneck.

In this embodiment, the parsing of the read instruction is based on the above-mentioned pre-decoding of the instruction, abbreviated as DE (DEcode), so step 202 is mainly the full decoding of the instruction in the specific parsing process to parse out the complete instruction information for subsequent execution. The instruction pre-decoding is to analyze or decode the instruction to be executed in advance, and when the processor executes the instruction, the pre-decoded instruction can reduce the waiting time of the processor when executing the instruction, reduce the time spent when executing the instruction, reduce unnecessary delay and improve the running speed of the program.

Pre-decoding is also a partial decoding, full decoding of an instruction is the complete decoding of an instruction, and in the pre-decoding stage, the instruction is decoded into an intermediate format, also known as micro-operations (μops). These micro-operations may interact more effectively with various parts of the CPU. In the full decode stage, these micro-operations are fully decoded into specific operations that can be performed on the CPU. This stage typically includes determining operands, addressing modes, operation types, and so forth.

In step 202, in addition to fully decoding the instruction, it is also required to determine whether the current instruction is a dual-issue instruction, where the dual-issue instruction refers to an instruction that can be executed by two simultaneous instructions, that is, in the subsequent execution module, the instruction that can be executed by two simultaneous instructions.

Step 203, executing two instructions simultaneously when the current instruction is a dual-emission instruction.

After the instruction is fully decoded, the execution phase is entered according to the different types of instructions. In a pipeline architecture as shown in fig. 3, corresponding to an embodiment of the present application, the execution of this step 203 is done by the EXU module. In an EXU module, its execution unit includes: a first arithmetic logic Unit (ALU 0, arithmetic Logic Unit), a second arithmetic logic Unit ALU1, MUL (MUL MULtiplication Unit), DIV (divbase), FPU (Float Point Unit), and WB write-back Unit. Among them, ALU is one of the core components of a computer, and is mainly used for performing arithmetic operations and logic operations, and it generally includes one or more arithmetic operation units such as adders, subtractors, multipliers and dividers, and some logic operation units such as AND, OR, NOT. The ALU performs the corresponding operation according to the opcode in the instruction. For example, if an instruction requires two-number addition operations to be performed, an adder in the ALU will add the two numbers and output the result; if the instruction requires a logical AND operation, an AND logic gate in the ALU ANDs the input signal AND outputs the result. In addition to performing arithmetic and logical operations, the ALU is also responsible for handling information such as overflows, carryover, etc., and storing the results in registers or memory as needed.

Floating point arithmetic unit FPU is a processor unit dedicated to floating point arithmetic and is often used in many higher-order programming languages (e.g. Fortran) and in some scientific operations requiring a large number of floating point arithmetic operations. The FPU, also called math coprocessor, is responsible for handling some floating point operations such as square root, logarithm, etc. In earlier computer designs, these operations were performed by logic circuitry in the CPU, but this was later found to complicate the CPU and make it difficult to maintain. FPUs have then been designed to specifically handle these operations so that the CPU can focus on other instructions. In a specific calculation process, the FPU can directly operate the floating point number storage unit in the memory, so that the operation speed of the floating point number is faster. In addition, the FPU may perform complex mathematical operations, such as trigonometric functions, logarithms, etc., that typically require multiple instructions in the CPU to complete.

In this embodiment of the present application, there are two arithmetic logic units in the EXU module, that is, the first arithmetic logic unit ALU0 and the second arithmetic logic unit ALU1, that is, the general operation instruction corresponding to the arithmetic logic unit may execute two instructions in the EXU module, that is, may execute two general operation instructions simultaneously. Therefore, the two instructions are emitted, namely, a double-emission pipeline is realized, two similar pipelines exist in the instruction execution unit, two instructions of the specified type can be executed at the same time, and the high-concurrency micro-architecture can necessarily improve the execution speed of the instruction stream.

It should be noted that, in step 203, when the current instruction is a dual-issue instruction, two instructions may be executed simultaneously, and when the current instruction is a non-dual-issue instruction, only one instruction is executed. That is, when the instruction is a general operation instruction corresponding to the arithmetic logic unit ALU in fig. 3, the current instruction is a dual-issue instruction, and two instructions can be executed simultaneously; when the instruction is the instruction corresponding to the MUL multiplication unit, the DIV division unit and the FPU floating point operation unit in fig. 3, that is, when the current instruction is a non-dual-emission instruction, only one corresponding instruction is executed. Wherein the non-dual issue instruction may include: multiplication instructions, division instructions, floating point operation instructions.

In practical application, a plurality of dual-emission instructions can be set according to practical situations, namely, in the EXU module, not only a general operation instruction is set as a dual-emission instruction, but also a JumP instruction is set as a dual-emission instruction, and two BJP (Branch JumP unit) are set in the corresponding EXU module as units for executing the two JumP instructions. That is, the embodiment of the present application does not specifically limit the dual-issue instruction, and may be flexibly set according to actual needs.

In addition, in the embodiment of the present application, in addition to executing the dual-issue instruction, a plurality of instructions may be executed simultaneously in the same execution cycle, that is, the instruction processing method provided in the embodiment of the present application may execute not only two instructions in the same execution cycle, but also three or more instructions simultaneously in the same execution cycle.

For example, taking fig. 3 as an example, after the DE module decodes three instructions, e.g., two general purpose operation instructions and one multiplication instruction. In the EXU module, these three instructions may be executed simultaneously, specifically two ALU units executing two general purpose operation instructions and one MUL unit executing a multiplication instruction.

In this embodiment of the present application, since the WB write-back unit is also in the EXU module, after executing a plurality of instructions, for example, after executing two general operation instructions and one multiplication instruction, the write-back operation may be executed at the same pipeline stage, without waiting for the next pipeline stage, so that the number of stages of the pipeline architecture corresponding to the embodiment of the present application is reduced, and the logic dynamic power consumption of the pipeline is reduced.

It should be noted that, since a plurality of instructions need to be executed, when the read instructions are fully decoded, the plurality of instructions need to be decoded accordingly to meet the requirement of executing the instructions later.

According to the embodiment of the application, the classical five-stage pipeline is reduced to the three-stage pipeline, two units for executing the double-emission instruction are arranged in the execution module, the concurrency of the processor is improved on the basis of reducing the pipeline, fewer pipelines mean fewer resource requirements, and meanwhile fewer logic dynamic power consumption is also meant, so that the chip area and the control power consumption are obviously reduced, and the requirements of area and power consumption in practical application are met; the three-level pipeline architecture provided by the embodiment of the application can support the emission of two instructions at a time, namely, the instruction execution unit has two similar pipelines, so that the processor can execute two instructions of specified types, the high concurrency of the processor is obviously improved, and the execution speed of an instruction stream is improved.

It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or other steps.

Referring to fig. 4, one embodiment of the present application provides an instruction processing apparatus 400, including: a reading module 401, a decoding module 402 and an executing module 403; wherein,

the reading module 401 is used for reading instructions from the memory; the decoding module 402 is configured to fully decode the read instruction, and determine whether the current instruction is a dual-emission instruction; the execution module 403 is configured to execute two instructions simultaneously when the current instruction is a dual-issue instruction.

In an alternative embodiment of the present application, the decoding module 402 is further configured to determine that the current instruction is a dual-issue instruction when the current instruction is a general operation instruction.

In an alternative embodiment of the present application, the execution module 403 is further configured to execute an instruction when the current instruction is a non-dual issue instruction.

In an alternative embodiment of the present application, the non-dual issue instruction includes: multiplication instructions, division instructions, floating point operation instructions, and memory access instructions.

In an alternative embodiment of the present application, the execution module 403 is further configured to execute multiple instructions simultaneously in the same execution cycle.

In an alternative embodiment of the present application, the execution module 403 is further configured to perform a write-back operation after executing the plurality of instructions.

In an alternative embodiment of the present application, the decoding module 402 is further configured to decode a plurality of instructions when fully decoding the fetched instructions.

The specific limitation of the instruction processing apparatus may be referred to as limitation of the instruction processing method hereinabove, and will not be described herein. The respective modules in the above-described instruction processing apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 5. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an instruction processing method as described above. Comprising the following steps: the system comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes any step of the instruction processing method when executing the computer program.

In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, can implement any of the steps of the instruction processing method described above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. A method of instruction processing, the method comprising:

reading instructions from a memory;

fully decoding the read instruction, and judging whether the current instruction is a double-emission instruction or not;

and when the current instruction is a double-emission instruction, executing two instructions simultaneously.

2. The method of claim 1, wherein determining whether the current instruction is a dual issue instruction comprises:

when the current instruction is a general operation instruction, the current instruction is a double-emission instruction.

3. The instruction processing method according to claim 1, characterized in that the method further comprises:

and executing an instruction when the current instruction is a non-dual-emission instruction.

4. The instruction processing method of claim 3, wherein the non-dual issue instruction comprises: multiplication instructions, division instructions, floating point operation instructions, and memory access instructions.

5. The instruction processing method according to claim 1, characterized in that the method further comprises:

multiple instructions are executed simultaneously in the same execution cycle.

6. The instruction processing method of claim 5, wherein the method further comprises:

after executing the plurality of instructions, performing a write-back operation.

7. The instruction processing method of claim 5, wherein the method further comprises:

when fully decoding a read instruction, multiple instructions are decoded.

8. An instruction processing apparatus, the apparatus comprising:

a reading module for reading instructions from the memory;

the decoding module is used for fully decoding the read instruction and judging whether the current instruction is a double-emission instruction or not;

and the execution module is used for executing two instructions simultaneously when the current instruction is a double-emission instruction.

9. A computer device, comprising: comprising a memory and a processor, said memory storing a computer program, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when said computer program is executed.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.