CN117792599A - Dual system phase synchronization method, apparatus, electronic device, medium, and program product - Google Patents
Dual system phase synchronization method, apparatus, electronic device, medium, and program product Download PDFInfo
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Abstract
The method is applied to the second time-frequency phase system, and comprises the steps of obtaining at least two time stamps of the first time-frequency phase system and at least two time stamps of the second time-frequency phase system in preset duration, and obtaining a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset duration; based on the frequency error, adjusting the local oscillation frequency of the second time-frequency phase system to obtain the adjusted local oscillation frequency; based on the adjusted local oscillation frequency, obtaining a clock signal corresponding to the adjusted local oscillation frequency, wherein the clock signal is synchronous with a clock signal output by the first time-frequency phase system; and performing phase shifting operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
Description
Technical Field
The present disclosure relates to the field of clock synchronization, and more particularly, to a dual system phase synchronization method, apparatus, electronic device, medium, and program product.
Background
In recent years, with the development of high-frequency Band communication technologies such as Ultra wideband technology and millimeter wave technology, because such a system has the advantages of low complexity, low power spectrum density of a transmitting signal, insensitivity to channel fading, low interception capability, high positioning accuracy and the like, the system starts to gradually develop into the time synchronization field, and a high-precision wireless clock synchronization scheme for comparing through bidirectional transmitting clock signals by using an Ultra Wideband (UWB) channel and a millimeter wave channel as communication channels also appears in the time synchronization field.
In the related art, the general solution idea of the wireless synchronization technology is two steps of frequency synchronization and clock synchronization, and is not focused on phase synchronization too much. And because of the manufacturing errors of hardware systems, the initial phase difference of the crystal oscillator at the moment of power-on and the frequency adjustment errors in the synchronization process, each node cannot obtain a clock signal and a frequency signal which are completely synchronized in clock-frequency-phase by the existing wireless time-frequency synchronization technology.
Disclosure of Invention
In view of the foregoing, the present disclosure provides a dual system phase synchronization method, apparatus, electronic device, medium, and program product.
According to a first aspect of the present disclosure, there is provided a dual system phase synchronization method including a first time-frequency phase system and a second time-frequency phase system of a distributed radar system, the method being applied to the second time-frequency phase system, the method comprising:
acquiring at least two time stamps of a first time-frequency phase system and at least two time stamps of a second time-frequency phase system in a preset time length, and acquiring a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset time length;
based on the frequency error, adjusting the local oscillation frequency of the second time-frequency phase system to obtain an adjusted local oscillation frequency;
obtaining a clock signal corresponding to the adjusted local oscillation frequency based on the adjusted local oscillation frequency, wherein the clock signal is synchronous with a clock signal output by the first time-frequency phase system;
and performing phase shifting operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
According to an embodiment of the present disclosure, the obtaining the at least two time stamps of the first time-frequency phase system and the at least two time stamps of the second time-frequency phase system within a preset time period, and obtaining the frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system, and the preset time period includes:
acquiring a current time stamp of the first time-frequency phase system and a current time stamp of the second time-frequency phase system;
obtaining a current time stamp error based on the current time stamp of the first time-frequency phase system and the current time stamp of the second time-frequency phase system;
delaying for a preset time length, and acquiring a delay time stamp of the first time-frequency phase system and a delay time stamp of the second time-frequency phase system;
obtaining a delay time stamp error based on the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system;
and obtaining a frequency offset error according to the current time stamp error, the delay time stamp error and the preset time length.
According to an embodiment of the disclosure, adjusting the local oscillation frequency of the second time-frequency phase system based on the frequency error to obtain an adjusted local oscillation frequency includes:
obtaining a voltage control quantity of a second time-frequency phase system based on the frequency offset error;
and controlling and adjusting the local oscillation frequency of the second time-frequency phase system based on the voltage control quantity to obtain the adjusted local oscillation frequency.
According to an embodiment of the disclosure, the obtaining, based on the adjusted local oscillation frequency, a clock signal corresponding to the adjusted local oscillation frequency, where the clock signal is synchronous with a clock signal output by the first time-frequency phase system includes:
and inputting the adjusted local oscillation frequency to a time-frequency phase synthesis unit, and adjusting the clock signal of the second time-frequency phase system through a voltage-controlled control frequency source in the time-frequency phase synthesis unit to obtain a clock signal corresponding to the adjusted local oscillation frequency.
According to an embodiment of the disclosure, the phase shifting operation is performed on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency, so as to obtain a phase signal synchronous with a phase signal output by a first time-frequency phase system, including:
and the time-frequency phase synthesis unit of the second time-frequency phase system receives the clock signal corresponding to the adjusted local oscillation frequency, and adjusts the local oscillation frequency of the second time-frequency phase system through a voltage-controlled control frequency source in the time-frequency phase synthesis unit to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
A second aspect of the present disclosure provides a dual-system phase synchronization apparatus, the dual system including a first time-frequency phase system and a second time-frequency phase system of a distributed radar system, the apparatus being applied to the second time-frequency phase system, the apparatus comprising:
the frequency offset error calculation module is used for acquiring at least two time stamps of a first time-frequency phase system and at least two time stamps of a second time-frequency phase system in a preset time length, and obtaining a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset time length;
the local oscillation frequency adjusting module is used for adjusting the local oscillation frequency of the second time-frequency phase system based on the frequency error to obtain the adjusted local oscillation frequency;
the clock signal adjusting module is used for obtaining a clock signal corresponding to the adjusted local oscillation frequency based on the adjusted local oscillation frequency, and the clock signal is synchronous with the clock signal output by the first time-frequency phase system;
and the phase signal adjusting module is used for carrying out phase shifting operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
According to an embodiment of the present disclosure, the frequency offset error calculation module is further configured to:
acquiring a current time stamp of the first time-frequency phase system and a current time stamp of the second time-frequency phase system;
obtaining a current time stamp error based on the current time stamp of the first time-frequency phase system and the current time stamp of the second time-frequency phase system;
delaying for a preset time length, and acquiring a delay time stamp of the first time-frequency phase system and a delay time stamp of the second time-frequency phase system;
obtaining a delay time stamp error based on the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system;
and obtaining a frequency offset error according to the current time stamp error, the delay time stamp error and the preset time length.
A third aspect of the present disclosure provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the methods of the embodiments of the present disclosure described above.
A fourth aspect of the present disclosure also provides a computer-readable storage medium having stored thereon executable instructions that, when executed by a processor, cause the processor to perform the method of the embodiments of the present disclosure described above.
The fifth aspect of the present disclosure also provides a computer program product comprising a computer program which, when executed by a processor, implements the method of the embodiments of the present disclosure described above.
According to the method and the device, the frequency offset error is calculated by acquiring at least two time stamps of the first time-frequency phase system and at least two time stamps of the second time-frequency phase system in the preset time length, and the local oscillation frequency of the second time-frequency phase system is adjusted according to the frequency offset error, so that frequency synchronization is achieved. And adjusting the clock signal according to the local oscillation frequency adjusted by the second time-frequency phase system to achieve clock synchronization. Finally, the adjusted local oscillation frequency is subjected to phase shifting operation based on the adjusted clock signal, so that the phase of the adjusted local oscillation frequency can be kept consistent with that of an external node, a high-precision phase synchronization function is achieved, the requirements of more equipment can be met, and the method is suitable for wider scenes.
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The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of the operation of dual system phase synchronization in an embodiment of the present disclosure;
fig. 2 schematically shows the architecture of a time-frequency phase system;
FIG. 3 schematically illustrates a flow chart of a dual system phase synchronization method according to an embodiment of the disclosure;
fig. 4 shows a flowchart of obtaining a frequency offset error according to an embodiment of the present disclosure;
FIG. 5 illustrates a flow chart for obtaining an adjusted local oscillator frequency in accordance with an embodiment of the present disclosure;
FIG. 6a illustrates an effect diagram of time-frequency only synchronization in accordance with an embodiment of the present disclosure;
fig. 6b shows a phase synchronization effect graph after phase synchronization according to an embodiment of the present disclosure;
fig. 7 shows a PPS clock difference experimental effect diagram according to an embodiment of the present disclosure;
FIG. 8 is a graph of experimental effects of phase synchronization according to an embodiment of the present disclosure;
fig. 9 schematically illustrates a block diagram of a dual system phase synchronization apparatus according to an embodiment of the present disclosure;
fig. 10 schematically illustrates a block diagram of an electronic device adapted to implement a dual system phase synchronization method in accordance with an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
The time-frequency synchronization includes time synchronization and frequency synchronization, and takes the first time-frequency phase system and the second time-frequency phase system as an example, the time synchronization refers to that a clock signal of the first time-frequency phase is consistent with a clock signal of the second time-frequency phase system, where the clock signal may be a PPS (pulse per second) signal. The frequency synchronization means that the local oscillation frequency of the first time-frequency phase system is consistent with the local oscillation frequency of the second time-frequency phase system, and the phase synchronization means that the phases of the two time-frequency phase systems are always consistent. Under phase synchronization, the local oscillation frequencies of the two systems are the same at every moment. It follows that the requirements for phase synchronization are much higher than for pure time-frequency synchronization, which is the basis for phase synchronization, which is the phase position 0 operation on frequency on the basis of time-frequency synchronization.
For stand-alone radars, the receiving and transmitting share the same time system and frequency source, so that the problem of time-frequency phase asynchronization does not exist generally, but for distributed radars, a clock signal and a local oscillation frequency of phase synchronization are needed between all sub radars (i.e. the time-frequency synchronous system). If the respective clock signals and local oscillation frequency signals of the sub radars cannot be in phase synchronization, the time sequence of the sub radars is disordered, so that the performance of the sub radars is reduced or even detection fails when the sub radars are synthesized or cooperatively detected.
Based on the above, the embodiment of the disclosure provides a dual-system phase synchronization method, which can effectively realize phase synchronization between time-frequency phase systems, so that phase errors between time-frequency phase systems meet requirements, and provides technical support for distributed radars.
Fig. 1 is a schematic diagram of the operation of dual system phase synchronization in an embodiment of the present disclosure.
As shown in fig. 1, the distributed radar system 100 may include a first time-frequency phase system 101 and a second time-frequency phase system 102 that may be in communication with each other.
It should be noted that the dual-system phase synchronization method mentioned in this disclosure may be that the first time-frequency phase system sends a signal to the second time-frequency phase system, so that the second time-frequency phase system is synchronized with the first time-frequency phase system. The second time-frequency phase system may also send a signal to the first time-frequency phase system, so that the first time-frequency phase system and the second time-frequency phase system are synchronized. The present disclosure is not limited in this regard.
Those skilled in the art will appreciate that the number of time-frequency phase systems in the distributed radar system shown in fig. 1 is merely illustrative, and the present disclosure is not limited to the number of time-frequency phase systems in the distributed radar system described above.
Fig. 2 schematically shows the architecture of a time-frequency phase system. The architecture 200 may include a signal transceiver module 201, a timestamp comparison module 202, a phase lock module 203, an adjustable frequency source module 204, a synchronization module 205, and a frequency synthesis module 206.
In order to better explain the module function, the first time-frequency phase system and the second time-frequency phase system will be taken as an example, and in this example, the first time-frequency phase system sends a signal to the second time-frequency phase system, so that the second time-frequency phase system is synchronized with the first time-frequency phase system.
The signal transceiving module 201, which may be configured to transceive time-frequency synchronization signals and record high-precision time stamps, should be provided with a support hardware layer signal transceiving time stamp record and support external trigger synchronization.
The timestamp comparison module 202 may be configured to compare a timestamp of the first time-frequency phase system with a timestamp of the second time-frequency phase system, and calculate a clock-to-local oscillator frequency difference between the two timestamps.
The phase lock module 203 may be configured to tame a frequency source of the second time-frequency phase system, where the module has a programmable logic function, a clock counting function, and a PID voltage-controlled frequency source output frequency function.
The adjustable frequency source module 204, which may be configured to generate a clock signal, is an externally adjustable frequency module (controllable by voltage control or numerical control).
The synchronization module 205 may be configured to generate the PPS signal according to a local clock of the second time-frequency phase system and generate the timestamp.
The frequency synthesis module 206 may be configured to receive the local oscillation frequency signal generated by the adjustable frequency source module and not subjected to phase synchronization, and output the synchronized local oscillation frequency after performing phase synchronization on the local oscillation frequency signal, and has a triggering function.
In an exemplary embodiment of the present disclosure, the signal transceiver module, the timestamp comparison module, and the synchronization module are integrated together into a DecaWave DW1000 chip.
In an exemplary embodiment of the present disclosure, the signal transceiver module, the timestamp comparison module, and the synchronization module may also be integrated together into a DecaWave DW3000 chip.
In an exemplary embodiment of the present disclosure, the phase lock module is comprised of a voltage controlled tamer circuit of a PID control DAC.
In an exemplary embodiment of the present disclosure, the tunable frequency source module employs a voltage controlled oven controlled crystal oscillator (VCOCXO) with short term frequency stability 5E-12.
In an exemplary embodiment of the present disclosure, the frequency synthesis module employs a TI LMX25 series chip, which may be, for example, a TILMX2572 chip or a TILMX2592 chip.
Fig. 3 schematically illustrates a flow chart of a dual system phase synchronization method according to an embodiment of the disclosure.
The dual system comprises a first time-frequency phase system and a second time-frequency phase system of the distributed radar system, and the method is applied to the second time-frequency phase system.
As shown in fig. 3, the method may include the following operations.
In operation S310, at least two time stamps of the first time-frequency phase system and at least two time stamps of the second time-frequency phase system are obtained within a preset time period, and a frequency offset error is obtained based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset time period.
At least two time stamps can be taken within a preset time length to calculate the frequency error, the sampling number of the time stamps within the preset time length is not limited, and the average value can be calculated by sampling the time stamps for multiple times so that the calculation result is more accurate.
In operation S320, the local oscillation frequency of the second time-frequency phase system is adjusted based on the frequency error, and the adjusted local oscillation frequency is obtained.
In operation S330, a clock signal corresponding to the adjusted local oscillation frequency is obtained based on the adjusted local oscillation frequency, the clock signal being synchronized with a clock signal output by the first time-frequency phase system.
In operation S340, a phase shift operation is performed on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency, to obtain a phase signal synchronized with the phase signal output by the first time-frequency phase system.
According to the method and the device, the frequency offset error is calculated by acquiring at least two time stamps of the first time-frequency phase system and at least two time stamps of the second time-frequency phase system in the preset time length, and the local oscillation frequency of the second time-frequency phase system is adjusted according to the frequency offset error, so that frequency synchronization is achieved. And adjusting the clock signal according to the local oscillation frequency adjusted by the second time-frequency phase system to achieve clock synchronization. Finally, the adjusted local oscillation frequency is subjected to phase shifting operation based on the adjusted clock signal, so that the phase of the adjusted local oscillation frequency can be kept consistent with that of an external node, a high-precision phase synchronization function is achieved, the requirements of more equipment can be met, and the method is suitable for wider scenes.
As will be described below by means of fig. 4, it is exemplarily described how the frequency offset error is obtained based on at least two time stamps of the first time-frequency phase system, at least two time stamps of the second time-frequency phase system and a preset time period in operation S310.
Fig. 4 shows a flowchart of obtaining a frequency offset error according to an embodiment of the present disclosure.
As shown in FIG. 4, operations S410-S450 may be included in the flow 400.
In operation S410, a current time stamp of the first time-frequency phase system and a current time stamp of the second time-frequency phase system are acquired.
The current time stamp of the second time-frequency phase system is generated after the second time-frequency phase system is initialized, and the current time stamp of the first time-frequency phase system is obtained based on channel reception.
The above-mentioned channel is a communication channel with high fidelity clock information transmission capability, for example, can be a UWB channel or a millimeter wave channel, which is not limited in this disclosure.
In operation S420, a current timestamp error is obtained based on the current timestamp of the first time-frequency phase system and the current timestamp of the second time-frequency phase system.
In operation S430, a delay time stamp of the first time-frequency phase system and a delay time stamp of the second time-frequency phase system are acquired by delaying for a preset period of time.
Wherein the value range of the preset duration is 1ms-20ms.
In operation S440, a delay time stamp error is obtained based on the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system.
In operation S450, a frequency offset error is obtained according to the current time stamp error, the delay time stamp error, and the preset time period.
Based on this, the frequency offset error can be calculated by the following formula (1).
F＝(B-A)/T (1)
Wherein F may represent a frequency offset error, B may represent a delay time stamp error, a may represent a current time stamp error, and T may represent a preset duration.
In an exemplary embodiment of the present disclosure, the delay time stamp error may be, for example, 4ms, the current time stamp error may be, for example, 2ms, and the preset duration is set to 2ms, and the calculated frequency offset error is 1HZ.
In the embodiment of the disclosure, the time stamp is obtained for the first time-frequency phase system and the second time-frequency phase system in the preset time period, the current time stamp error is calculated by the current time stamp of the first time-frequency phase system and the current time stamp of the second time-frequency phase system, after the preset time period is delayed, the delay time stamp error is calculated by the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system, so that the frequency offset error can be accurately calculated, accurate data can be provided for the later frequency synchronization, the second time-frequency phase system can achieve frequency synchronization with the first time-frequency phase system, clock synchronization is achieved, and finally phase synchronization is achieved.
How the local oscillation frequency of the second time-frequency phase system is adjusted based on the frequency error in operation S320 will be exemplarily described below with reference to fig. 5, resulting in an adjusted local oscillation frequency.
Fig. 5 shows a flowchart for obtaining an adjusted local oscillator frequency in accordance with an embodiment of the present disclosure.
As shown in FIG. 5, operations S510-S520 may be included in the flow 500.
In operation S510, a voltage control amount of the second time-frequency phase system is obtained based on the frequency offset error.
In operation S520, the local oscillation frequency of the second time-frequency phase system is adjusted based on the voltage control amount control, and the adjusted local oscillation frequency is obtained.
In operation S330, the adjusted local oscillation frequency is input to the time-frequency phase synthesis unit, and the clock signal of the second time-frequency phase system is adjusted by the voltage-controlled control frequency source in the time-frequency phase synthesis unit, so as to obtain the clock signal corresponding to the adjusted local oscillation frequency.
The voltage controlled frequency source may be, for example, a voltage controlled oven controlled crystal oscillator (VCOCXO) with short term frequency stability 5E-12.
In operation S340, the clock signal corresponding to the adjusted local oscillation frequency is received by the time-frequency phase synthesis unit of the second time-frequency phase system, and the local oscillation frequency of the second time-frequency phase system is adjusted by the voltage-controlled control frequency source in the time-frequency phase synthesis unit, so as to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
In an alternative embodiment, steps S310-S340 may be repeated after step S340 to achieve adaptive synchronization of the first time-frequency phase system and the second time-frequency phase system.
According to the method, the two-system phase synchronization method is continuously executed during the system operation, so that the second time-frequency phase system can be adaptively in phase agreement with the first time-frequency phase system, the operation is simplified, and the stability of the distributed radar system is improved.
Fig. 6a shows an effect diagram of time-frequency only synchronization in accordance with an embodiment of the present disclosure.
Fig. 6b shows a phase synchronization effect graph after phase synchronization according to an embodiment of the present disclosure.
As shown in fig. 6a, before phase synchronization, the master node (i.e., the first time-frequency phase system in the present disclosure) and the slave node (i.e., the second time-frequency phase system in the present disclosure) output the clock signal and the local oscillation frequency as shown in the figure, so that it is obvious that the time of the clock signal transmission between the two nodes is consistent, i.e., the clock signals are synchronized. The number of periodic changes that the two nodes complete in a unit time is also consistent, i.e., frequency synchronized. But at the same point in time, the two nodes have a certain phase difference.
After the dual-system phase synchronization method according to the embodiments of the present disclosure, as shown in fig. 6b, the phases between two nodes are synchronized, and the phase synchronization means that the time-frequency between the two nodes is also synchronized.
Fig. 7 shows a PPS clock difference experimental effect diagram according to an embodiment of the present disclosure.
As shown in fig. 7, the abscissa in the graph is sampling time, the ordinate in the graph is clock difference (in ns), and because PPS emits a pulse every 1 second, the PPS corresponds to one clock difference every second in the graph, as shown in the graph, after the dual-system synchronization method of the embodiment of the present disclosure is adopted, the clock difference between two nodes is always kept below 1ns, that is, the present disclosure can achieve a better clock synchronization effect.
Fig. 8 is an experimental effect diagram of phase synchronization according to an embodiment of the present disclosure.
As shown in fig. 8, the two waveforms in the oscilloscope are nearly overlapping. Experimental results show that after the dual-system phase synchronization method of the embodiment of the disclosure, the time difference between two nodes reaching the same phase can reach 1ps under the frequency of 100 MHz.
Fig. 9 schematically illustrates a block diagram of a dual system phase synchronization apparatus according to an embodiment of the present disclosure. The device will be described in detail below in connection with fig. 9.
As shown in fig. 9, the dual-system phase synchronization apparatus 900 of this embodiment includes a frequency offset error calculation module 910, a local oscillation frequency adjustment module 920, a clock signal adjustment module 930, and a phase signal adjustment module 940.
The frequency offset error calculation module 910 is configured to obtain at least two time stamps of the first time-frequency phase system and at least two time stamps of the second time-frequency phase system within a preset duration, and obtain a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system, and the preset duration. In an embodiment, the frequency offset error calculation module 910 may be configured to perform the operation S310 described above, which is not described herein.
The local oscillation frequency adjusting module 920 is configured to adjust the local oscillation frequency of the second time-frequency phase system based on the frequency error, to obtain the adjusted local oscillation frequency. In an embodiment, the local oscillation frequency adjustment module 920 may be configured to perform the operation S320 described above, which is not described herein.
The clock signal adjusting module 930 is configured to obtain, based on the adjusted local oscillation frequency, a clock signal corresponding to the adjusted local oscillation frequency, where the clock signal is synchronous with a clock signal output by the first time-frequency phase system. In an embodiment, the clock signal adjusting module 930 may be used to perform the operation S330 described above, which is not described herein.
The phase signal adjusting module 940 is configured to perform a phase shifting operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency, so as to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system. In an embodiment, the phase signal adjustment module 940 may be used to perform the operation S340 described above, which is not described herein.
According to an embodiment of the present disclosure, any of the frequency offset error calculation module 910, the local oscillation frequency adjustment module 920, the clock signal adjustment module 930, and the phase signal adjustment module 940 may be combined in one module to be implemented, or any of the modules may be split into a plurality of modules. Alternatively, at least some of the functionality of one or more of the modules may be combined with at least some of the functionality of other modules and implemented in one module. According to embodiments of the present disclosure, at least one of the frequency offset error calculation module 910, the local oscillator frequency adjustment module 920, the clock signal adjustment module 930, and the phase signal adjustment module 940 may be implemented at least in part as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system-on-chip, a system-on-substrate, a system-on-package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging the circuitry, or in any one of or a suitable combination of three of software, hardware, and firmware. Alternatively, at least one of the frequency offset error calculation module 910, the local oscillator frequency adjustment module 920, the clock signal adjustment module 930, and the phase signal adjustment module 940 may be implemented at least in part as computer program modules that, when executed, perform the corresponding functions.
Fig. 10 schematically illustrates a block diagram of an electronic device adapted to implement a dual system phase synchronization method in accordance with an embodiment of the present disclosure.
As shown in fig. 10, an electronic device 1000 according to an embodiment of the present disclosure includes a processor 1001 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1002 or a program loaded from a storage section 1008 into a Random Access Memory (RAM) 1003. The processor 1001 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. The processor 1001 may also include on-board memory for caching purposes. The processor 1001 may include a single processing unit or multiple processing units for performing different actions of the method flows according to embodiments of the present disclosure.
In the RAM 1003, various programs and data necessary for the operation of the electronic apparatus 1000 are stored. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other by a bus 1004. The processor 1001 performs various operations of the method flow according to the embodiment of the present disclosure by executing programs in the ROM 1002 and/or the RAM 1003. Note that the program may be stored in one or more memories other than the ROM 1002 and the RAM 1003. The processor 1001 may also perform various operations of the method flow according to the embodiments of the present disclosure by executing programs stored in the one or more memories.
According to an embodiment of the disclosure, the electronic device 1000 may also include an input/output (I/O) interface 1005, the input/output (I/O) interface 1005 also being connected to the bus 1004. The electronic device 1000 may also include one or more of the following components connected to the I/O interface 1005: an input section 1006 including a keyboard, a mouse, and the like; an output portion 10010 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker, and the like; a storage portion 1008 including a hard disk or the like; and a communication section 1009 including a network interface card such as a LAN card, a modem, or the like. The communication section 1009 performs communication processing via a network such as the internet. The drive 1010 is also connected to the I/O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in the drive 1010, so that a computer program read out therefrom is installed as needed in the storage section 1008.
The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present disclosure.
According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to embodiments of the present disclosure, the computer-readable storage medium may include ROM 1002 and/or RAM 1003 and/or one or more memories other than ROM 1002 and RAM 1003 described above.
Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowcharts. The program code, when executed in a computer system, causes the computer system to implement the item recommendation method provided by embodiments of the present disclosure.
The above-described functions defined in the system/apparatus of the embodiments of the present disclosure are performed when the computer program is executed by the processor 1001. The systems, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.
In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program may also be transmitted in the form of signals on a network medium, distributed, and downloaded and installed via the communication section 1009, and/or installed from the removable medium 1011. The computer program may include program code that may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.
In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 1009, and/or installed from the removable medium 1011. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 1001. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.
According to embodiments of the present disclosure, program code for performing computer programs provided by embodiments of the present disclosure may be written in any combination of one or more programming languages, and in particular, such computer programs may be implemented in high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. Programming languages include, but are not limited to, such as Java, c++, python, "C" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (10)
1. A dual system phase synchronization method, wherein the dual system comprises a first time-frequency phase system and a second time-frequency phase system of a distributed radar system, the method being applied to the second time-frequency phase system, the method comprising:
acquiring at least two time stamps of a first time-frequency phase system and at least two time stamps of a second time-frequency phase system in a preset time length, and acquiring a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset time length;
based on the frequency error, adjusting the local oscillation frequency of the second time-frequency phase system to obtain an adjusted local oscillation frequency;
based on the adjusted local oscillation frequency, obtaining a clock signal corresponding to the adjusted local oscillation frequency, wherein the clock signal is synchronous with a clock signal output by the first time-frequency phase system;
and performing phase shifting operation on the adjusted local oscillation frequency based on a clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronous with a phase signal output by the first time-frequency phase system.
2. The dual system phase synchronization method according to claim 1, wherein the obtaining at least two time stamps of a first time-frequency phase system and at least two time stamps of a second time-frequency phase system within a preset time period, obtaining a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system, and the preset time period, comprises:
acquiring a current time stamp of the first time-frequency phase system and a current time stamp of the second time-frequency phase system;
obtaining a current time stamp error based on the current time stamp of the first time-frequency phase system and the current time stamp of the second time-frequency phase system;
delaying for a preset time length, and acquiring a delay time stamp of the first time-frequency phase system and a delay time stamp of the second time-frequency phase system;
obtaining a delay time stamp error based on the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system;
and obtaining a frequency offset error according to the current timestamp error, the delay timestamp error and the preset duration.
3. The dual system phase synchronization method of claim 1, wherein adjusting the local oscillator frequency of the second time-frequency phase system based on the frequency error, to obtain the adjusted local oscillator frequency, comprises:
obtaining a voltage control quantity of a second time-frequency phase system based on the frequency offset error;
and controlling and adjusting the local oscillation frequency of the second time-frequency phase system based on the voltage control quantity to obtain the adjusted local oscillation frequency.
4. The dual system phase synchronization method according to claim 1, wherein the obtaining, based on the adjusted local oscillation frequency, a clock signal corresponding to the adjusted local oscillation frequency, the clock signal being synchronized with a clock signal output by the first time-frequency phase system, includes:
and inputting the adjusted local oscillation frequency to a time-frequency phase synthesis unit, and adjusting the clock signal of the second time-frequency phase system through a voltage-controlled control frequency source in the time-frequency phase synthesis unit to obtain a clock signal corresponding to the adjusted local oscillation frequency.
5. The dual system phase synchronization method according to claim 1, wherein the performing a phase shift operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronized with the phase signal output by the first time-frequency phase system, includes:
and the time-frequency phase synthesis unit of the second time-frequency phase system receives the clock signal corresponding to the adjusted local oscillation frequency, adjusts the local oscillation frequency of the second time-frequency phase system through a voltage-controlled control frequency source in the time-frequency phase synthesis unit, and obtains a phase signal synchronous with the phase signal output by the first time-frequency phase system.
6. A dual system phase synchronization apparatus, the dual system comprising a first time-frequency phase system and a second time-frequency phase system of a distributed radar system, the apparatus being applied to the second time-frequency phase system, the apparatus comprising:
the frequency offset error calculation module is used for acquiring at least two time stamps of a first time-frequency phase system and at least two time stamps of a second time-frequency phase system in a preset duration, and obtaining a frequency offset error based on the at least two time stamps of the first time-frequency phase system, the at least two time stamps of the second time-frequency phase system and the preset duration;
the local oscillation frequency adjusting module is used for adjusting the local oscillation frequency of the second time-frequency phase system based on the frequency error to obtain the adjusted local oscillation frequency;
the clock signal adjusting module is used for obtaining a clock signal corresponding to the adjusted local oscillation frequency based on the adjusted local oscillation frequency, and the clock signal is synchronous with the clock signal output by the first time-frequency phase system;
and the phase signal adjusting module is used for carrying out phase shifting operation on the adjusted local oscillation frequency based on the clock signal corresponding to the adjusted local oscillation frequency to obtain a phase signal synchronous with the phase signal output by the first time-frequency phase system.
7. The dual system phase synchronization apparatus of claim 6, wherein the frequency offset error calculation module is further configured to:
acquiring a current time stamp of the first time-frequency phase system and a current time stamp of the second time-frequency phase system;
obtaining a current time stamp error based on the current time stamp of the first time-frequency phase system and the current time stamp of the second time-frequency phase system;
delaying for a preset time length, and acquiring a delay time stamp of the first time-frequency phase system and a delay time stamp of the second time-frequency phase system;
obtaining a delay time stamp error based on the delay time stamp of the first time-frequency phase system and the delay time stamp of the second time-frequency phase system;
and obtaining a frequency offset error according to the current timestamp error, the delay timestamp error and the preset duration.
8. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs,
wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the method of any of claims 1-5.
9. A computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to perform the method according to any of claims 1-5.
10. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 5.
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