CN117792554A - Clock domain crossing time information correction method and distributed system thereof - Google Patents
Clock domain crossing time information correction method and distributed system thereof Download PDFInfo
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Abstract
The invention provides a clock domain crossing time information correction method and a distributed system thereof, wherein the method comprises the following steps: the child node sends a digital signal carrying self clock and data information to the main node, and then the main node recovers the clock and the data of the child node; the master node is configured with a child node clock counter and a master node clock counter; the master node samples the other clock through any one clock of the slave node clock and the master node clock, and when the lag time between the two clocks reaches a single period of the clock with faster frequency, the slave node clock counter is adjusted to keep the two clock counters consistent; and obtaining the time stamp of the data of the child node in the master node clock domain through conversion of the child node clock counter and the master node clock. The invention has simple structure, saves the calculation cost and has higher time measurement precision.
Description
Technical Field
The invention belongs to the technical field of distribution, and particularly relates to a clock domain crossing time information correction method and a distributed system thereof.
Background
Time information generally refers to the specific moment of occurrence of an event or the interrelationship of the moments of occurrence of different events, such as time differences. For large distributed systems, it is sometimes desirable to accurately measure the exact time of occurrence of events at different nodes. To achieve this, in addition to time measurement by the child node design circuits, the relationship between the node clock references needs to be considered. Current typical distributed system time measurement techniques are generally based on a synchronous clock, with a master node distributing a clock reference to each child node. When the clocks of the whole system are homologous and stable, the time information obtained by measurement of each node can be converted into a unified clock domain. This synchronization has advantages, but for large systems, either based on independent clock distribution links or using clock distribution methods embedded in the data, complex system designs for accurate clock distribution are required, such as the need to achieve high precision clock distribution and scaling, and clock recovery circuits at each child node to obtain the system clock from the master node. All prior art methods tend to be expensive and difficult to deploy, while the accuracy of asynchronous clock time measurement schemes is relatively low.
Disclosure of Invention
The invention aims to solve the defects in the background technology, and provides a clock domain crossing time information correction method and a distributed system thereof, which have the advantages of simple structure, equipment cost saving, relatively convenient deployment and relatively high time measurement precision.
The technical scheme adopted by the invention is as follows: a method for correcting time information across clock domains, comprising the steps of:
the child node sends a digital signal carrying self clock and data information to the main node, and then the main node recovers the clock and the data of the child node;
the master node is configured with a child node clock counter and a master node clock counter; the master node samples the other clock through any one clock of the slave node clock and the master node clock, and when the lag time between the two clocks reaches a single period of the clock with faster frequency, the slave node clock counter is adjusted to keep the two clock counters consistent;
and obtaining the time stamp of the data of the child node in the master node clock domain through conversion of the child node clock counter and the master node clock.
In the above technical scheme, the method further comprises the following steps: counting the cycle number P of the sub-node clock in the process that the counter of the two clocks reaches a single cycle of the clock with faster frequency from the coincidence of the counter of the two clocks, and generating a correction value of the sub-node clock counter based on the cycle number P by the main node; and in each period of the sub-node clock, the sub-node clock counter increases the correction value as a counting result of the sub-node clock counter on the premise of normal counting.
In the technical scheme, when the counters of the two clocks are consistent, the correction value of the counter of the child node clock is 0;
under the condition that the clock frequency of the child node is larger than that of the main node, the correction value of the clock counter of the child node is increased by-1/P in each clock period of the child node compared with the previous clock period until the counter of the two clocks is adjusted to be consistent, and the cycle is performed;
in the case where the child node clock frequency is smaller than the master node clock frequency, the correction value of the child node clock counter is increased by +1/P over the last clock period at each child node clock period until the counter of the two clocks is adjusted to be identical, thereby cycling.
In the above technical solution, for the sampling result of any clock to another clock, when the lag time between two clocks reaches a single period of the clock with faster frequency, a window for prohibiting correction is added to the first jump edge of the sampling result.
In the above technical solution, when the lag time between two clocks reaches a single period of the clock with a faster frequency, an enable signal is generated, and the enable signal is used for adjusting the counter of the sub-node clock.
In the above technical solution, when the frequency of the sub-node clock is greater than that of the main node clock, the sub-node clock is used to sample the main node clock: when the sub-node clock is a rising edge, sampling the main node clock, and generating a sampling result according to the level state of the main node clock; when the sampling result shows a falling edge, the calculation of the sub-node clock counter in the period is kept unchanged.
In the above technical solution, when the frequency of the child node clock is smaller than that of the master node clock, the master node clock is used to sample the child node clock signal: when the main node clock is a rising edge, sampling the sub node clock, and generating a sampling result according to the level state of the sub node clock; when the sampling result shows a falling edge, the current period counting result of the sub-node clock counter is increased by one more.
In the above technical solution, the master node decodes the digital signal of the slave node after receiving the digital signal, recovers the clock and the data, and then performs clock domain correction.
In the above technical solution, the width of the window is set according to the two clock jitter magnitudes and the magnitude of the two clock frequency differences.
The invention also provides a distributed system for correcting the time information of the cross-clock domain, which comprises a main node and a plurality of sub-nodes; the main node adopts a system clock, and the sub nodes adopt local independent clocks; the system executes the clock domain crossing time information correction method, so that the master node corrects the digital signals from each sub-node from the clock domain of the sub-node to the clock domain of the master node.
The beneficial effects of the invention are as follows: the clock domain time information correction method can simplify the clock link design of the whole system, particularly each sub-node, each sub-node can directly use the local independent clock reference, each sub-node clock does not need to be synchronized with the clock of the total node, and the calculation cost and the manufacturing cost of the sub-node system are effectively saved. The master node uses the slave node clock and the local system clock recovered from the data stream based on the time information and the data stream transmitted from the slave node, and the time information of the slave node event can be converted from the slave node clock domain to the system clock domain of the master node by combining the correction method provided by the invention, so that the higher time measurement precision of the slave node data received by the master node is ensured.
Further, the correction accuracy of the sub-node clock is further improved by correcting the correction result of the sub-node clock counter, and the sub-node data received by the main node is guaranteed to have higher time measurement accuracy.
Furthermore, the correction method provided by the invention can dynamically reduce the problem of unstable period P caused by the jitter problem, and further improve the time measurement precision.
Furthermore, the invention adds a window for prohibiting correction after the first edge jump of the sampling result, thereby effectively avoiding the problem of error correction operation of the counter caused by clock jitter and improving the stability of the calibration operation.
Furthermore, the invention can dynamically adjust the time of the child node clock counter each time by setting the enabling signal, thereby ensuring the accuracy of the calibration operation and improving the time measurement precision.
Furthermore, the sampling mode adopted by the invention can keep the consistency of counter values in different clock domains according to different scenes, and the realization method is simpler and the resource consumption is low.
Furthermore, the invention carries out transcoding before executing clock domain correction, thereby ensuring the correctness of data transmission, simultaneously ensuring the high quality of data transmission in an electric link and further reducing the risk of data errors.
Furthermore, the window width is set according to the information of the two clocks, so that the condition that the whole system is invalid due to overlarge clock jitter can be avoided. The time calibration accuracy is improved, and the misoperation probability is reduced.
Drawings
FIG. 1 is a schematic flow chart of the method of the present invention;
FIG. 2 is a schematic diagram of a system distribution of an embodiment;
FIG. 3 is a schematic diagram of sample result generation according to an embodiment;
FIG. 4 is a schematic diagram of counter calibration according to an embodiment;
FIG. 5 is a schematic diagram of an enable signal according to an embodiment.
Detailed Description
The invention will now be described in further detail with reference to the drawings and specific examples, which are given for clarity of understanding and are not to be construed as limiting the invention.
As shown in fig. 1, the method for correcting time information of a clock domain crossing comprises the following steps:
the child node sends a digital signal carrying the self clock and data information to the main node, and then the main node recovers the digital signal;
the master node is configured with a child node clock counter and a master node clock counter; the master node samples the other clock through any one clock of the slave node clock and the master node clock, and when the lag time between the two clocks reaches a single period of the clock with faster frequency, the slave node clock counter is adjusted to keep the two clock counters consistent;
and obtaining the time stamp of the data of the child node in the master node clock domain through conversion of the child node clock counter and the master node clock.
The invention also provides a distributed system for correcting the time information of the cross-clock domain, which comprises a main node and a plurality of sub-nodes; the main node adopts a system clock, and the sub nodes adopt local independent clocks; the system executes the clock domain crossing time information correction method, so that the master node corrects the digital signals from each sub-node from the clock domain of the sub-node to the clock domain of the master node.
The method provided by the invention is still applicable when the frequencies of the system clock of the main node and the local clock of the sub-node are obviously different.
The principles of the present invention are further described below in connection with specific embodiments.
As shown in fig. 2, this embodiment includes a plurality of child nodes, and the main node is an FPGA. The signal interaction mode of each sub-node and the main node is the same, and the main node respectively executes the clock domain crossing time information correction method aiming at each sub-node. The present invention is explained by the time information correction procedure of the master node to a certain child node.
The child nodes use local respective independent clocks f node As a reference for time measurement, applied to local modules, e.g. time-to-digital converters (TDCs), f node But also as a reference clock for the uplink data link. The child node sends the clock f to the master node through the unidirectional optical fiber node And a digital signal of data information. The sub-node and the main node both realize conversion between optical signals and electric signals through SFP+ modules.
The master node adopts a system clock f sys As a reference, the Transceiver (transmitter) recovers the data and clock f under the clock domain of the sub-node transmitted from the sub-node node . Then adopts a calization module and utilizes the recovered child node clock f node With local system clock f sys Correcting the time information of the child node to the local f sys Under the system clock domain.
The master node is configured with a child node clock counter CNT fcal_int And master node clock counter CNT sys . Running on a local system clock f sys Lower counter CNT sys The count value is incremented by one for each master node clock cycle. Run on recovered clock, i.e. sub-node clock f node Lower child node clock counter CNT fcal_int Normally one is added to each child node clock cycle.
In this embodiment, the child node clock f node The frequency is slightly higher than the system clock f sys The correction procedure of this embodiment is as follows:
using a sub-node clock f node For the system clock f sys Sampling is performed when the sub-node clock f node When rising edge occurs, for the master node clock f sys Sampling to generate sampling result DFF out . As shown in fig. 3, if the sampling time, i.e., the rising edge of the sub-node clock, occurs, the system clock f sys At high level, the result DFF is sampled out High and vice versa.
As shown in FIG. 4, when the sampling result DFF out When a falling edge occurs, i.e. the delay time between the two clocks reaches the single period of the sub-node clock, the sub-node counter CNT will be controlled fcal_int The count value of the secondary period remains unchanged.
Specifically, the child node counter CNT fcal_int And a system clock counter CNT sys The count values remain the same at the initial time, and are J. The sub-node counter CNT at a time before the falling edge occurs in the sampling result DFFout fcal_int The count value of (1) is K-1, and the system clock counter CNT sys The count value of (2) is K-2, the count value difference of the two counters reaches 1, and the trailing edges are aligned. So at the next clock cycle, the system clock counter CNT sys Normally counting, the count value becomes K-1, the sub-node counter CNT fcal_int The count value of (2) remains consistent with the last clock cycle, i.e., still K-1.
The embodiment is based on clock sampling and based on the sampling result DFF out The period difference of two asynchronous clocks can be measured, i.e. the sampling result is DFF out Is a frequency of (2); and the counter values of the two clock domains are maintained at less than 1 by adjusting the counter values.
Aiming at the correction method of the child node counter, the embodiment further provides a correction method for the correction result:
counting the period number P of the sub-node clock in the process that the counter of the two clocks reaches a single period of the clock with faster frequency from the coincidence of the delay time between the two clocks by the master node, and generating a correction value CNT of the sub-node clock counter based on the period number P fcal_frac The method comprises the steps of carrying out a first treatment on the surface of the At each period of the sub-node clock, the counter of the sub-node clock increases the correction value as the correction result of the counter of the sub-node clock (i.e., CNT fcal_int +CNT fcal_frac )。
When the counters of the two clocks are consistent, the corrected value of the child node clock is 0; the correction value of the sub-node clock is increased by-1/P in each clock period of the sub-node compared with the previous clock period until the counters of the two clocks are adjusted to be consistent, thereby cycling.
As shown in fig. 4, for the child node clock f node Lower counter information J+2, correct to f sys The counter is J+2-2/P when the clock domain is down.
The embodiment further corrects the fractional part of the time information of the sub-node clock, and the corrected precision is close to the period difference of the two clocks in ideal condition.
Multiplying the corrected and corrected child node clock counter with the clock frequency of the master node to obtain the relative time of the digital signal of the child node from 0 point in the clock domain of the master node, and then superposing the relative time and the system time of the clock domain of the master node to obtain a final time stamp, thereby realizing the time information correction of the digital signal from the child node clock domain to the clock domain of the master node.
The actual sampling result DFF is due to the fact that there is Jitter (Jitter) in the clock edges of both clocks out As will be seen in fig. 5, there is a ripple near each ideal edge, i.e. a brief, repetitive transition between low level 0 and high level 1. Therefore, when the correction is actually performed in the embodiment, a Window (Window) for prohibiting correction is added after the first jump of each ideal edge, and only the result DFF is sampled out Generating a Calibrate pulse at the position of the falling edge, counter CNT for the sub-node clock fcal_int And performing primary correction to keep the primary node clock counter consistent.
Window's width setting may be configured online, depending on the size of the clock jitter and the size of the difference between the two clock frequencies. The criteria of the width setting are mainly dependent on the sampling result DFF out It is generally recommended to take 1/4 of the period as the window size.
In the prior art, clock synchronization is needed between a main node and a plurality of sub-node devices, so that the design requirements on a scheme are more severe, the scheme is inflexible, and the number of interconnection cables between the devices is more. The invention effectively solves the problem of recovering time information under the cross-clock domain, provides more possibility of scheme design, can be applied to some systems which cannot perform time synchronization, and simplifies the overall structure of the system.
Compared with the prior art, the system design complexity is effectively reduced, as in the traditional large-scale system, clock distribution is commonly used for completing clock synchronization of the whole system, and at least 2 cables are needed for each subsystem for transmitting digital signals from the slave node to the master node and transmitting clock signals from the master node to the slave node.
The method provided by the invention can calibrate the clock signals of the sub-nodes into the main system under the condition of using an asynchronous clock, so that the connection with each sub-system is reduced to 1 cable, and the method is only used for transmitting digital signals from the nodes to the main node. The equipment cost, the system design complexity and the design speed are obviously improved.
It is worth noting that in some large systems, hundreds or even thousands of subsystems are often required, and the cables are long and high in cost, so that the invention can save hundreds or even tens of thousands of costs when applied to the large systems.
What is not described in detail in this specification is prior art known to those skilled in the art.
Claims (10)
1. A clock domain crossing time information correction method is characterized in that: the method comprises the following steps:
the child node sends a digital signal carrying self clock and data information to the main node, and then the main node recovers the clock and the data of the child node;
the master node is configured with a child node clock counter and a master node clock counter; the master node samples the other clock through any one clock of the slave node clock and the master node clock, and when the lag time between the two clocks reaches a single period of the clock with faster frequency, the slave node clock counter is adjusted to keep the two clock counters consistent;
and obtaining the time stamp of the data of the child node in the clock domain of the master node through the conversion of the clock counter of the child node and the clock of the master node.
2. A method according to claim 1, characterized in that: the method also comprises the following steps: counting the cycle number P of the sub-node clock in the process that the counter of the two clocks reaches a single cycle of the clock with faster frequency from the coincidence of the counter of the two clocks, and generating a correction value of the sub-node clock counter based on the cycle number P by the main node; and in each period of the sub-node clock, the sub-node clock counter increases the correction value as a counting result of the sub-node clock counter on the premise of normal counting.
3. A method according to claim 2, characterized in that: when the counters of the two clocks are consistent, the correction value of the counter of the child node clock is 0;
under the condition that the clock frequency of the child node is larger than that of the main node, the correction value of the clock counter of the child node is increased by-1/P in each clock period of the child node compared with the previous clock period until the counter of the two clocks is adjusted to be consistent, and the cycle is performed;
in the case where the child node clock frequency is smaller than the master node clock frequency, the correction value of the child node clock counter is increased by +1/P over the last clock period at each child node clock period until the counter of the two clocks is adjusted to be identical, thereby cycling.
4. A method according to claim 1, characterized in that: for the sampling result of one clock to the other clock, when the lag time between the two clocks reaches a single period of the clock with a faster frequency, a window for prohibiting correction is added to the first jump edge of the sampling result.
5. A method according to claim 1, characterized in that: an enable signal is generated when the lag time between the two clocks is found to reach a single period of the faster frequency clock, the enable signal being used to adjust the counter of the child node clock.
6. A method according to claim 1, characterized in that: when the frequency of the sub-node clock is larger than that of the main node clock, sampling the main node clock by adopting the sub-node clock: when the sub-node clock is a rising edge, sampling the main node clock, and generating a sampling result according to the level state of the main node clock; when the sampling result shows a falling edge, the calculation of the sub-node clock counter in the period is kept unchanged.
7. A method according to claim 1, characterized in that: when the frequency of the sub-node clock is smaller than that of the main node clock, sampling the sub-node clock signal by adopting the main node clock: when the main node clock is a rising edge, sampling the sub node clock, and generating a sampling result according to the level state of the sub node clock; when the sampling result shows a falling edge, the current period counting result of the sub-node clock counter is increased by one more.
8. A method according to claim 1, characterized in that: the master node receives the digital signals of the child nodes, decodes the digital signals, recovers clocks and data, and then performs clock domain correction.
9. A method according to claim 4, characterized in that: the width of the window is set according to the two clock jitter magnitudes and the magnitude of the two clock frequency differences.
10. A distributed system for cross-clock domain time information correction, characterized by: the system comprises a main node and a plurality of sub-nodes; the main node adopts a system clock, and the sub nodes adopt local independent clocks; the system performs the method for correcting time information across clock domains according to any one of claims 1-9, so that the master node corrects the digital signal from each child node from the clock domain of the child node to the clock domain of the master node.
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| CN202311813746.XA CN117792554A (en) | 2023-12-27 | 2023-12-27 | Clock domain crossing time information correction method and distributed system thereof |
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