CN117792401A - Sigma delta analog-to-digital converter - Google Patents
Sigma delta analog-to-digital converter Download PDFInfo
- Publication number
- CN117792401A CN117792401A CN202311863221.7A CN202311863221A CN117792401A CN 117792401 A CN117792401 A CN 117792401A CN 202311863221 A CN202311863221 A CN 202311863221A CN 117792401 A CN117792401 A CN 117792401A
- Authority
- CN
- China
- Prior art keywords
- analog
- stage
- adder
- digital
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 46
- 230000003111 delayed effect Effects 0.000 claims description 19
- 238000005070 sampling Methods 0.000 claims description 13
- 230000010354 integration Effects 0.000 claims description 10
- 230000008030 elimination Effects 0.000 claims 3
- 238000003379 elimination reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The application relates to the technical field of analog integrated circuits and discloses a Sigma delta analog-to-digital converter, which comprises a third-order cascade structure, wherein an ith-order structure comprises: an i-th stage analog adder, an input end of which is connected with an input signal; the ith analog integrator is connected with the ith analog adder; an ith comparator connected to the ith analog integrator to generate an ith quantized signal; an i-th digital-to-analog converter, the input end of which is connected with the comparator, and the output end of which is connected with the other input end of the i-th analog adder; converting the quantized signal of the ith comparator, transmitting the converted signal to an ith analog adder, and performing difference with the input signal; the output end of the ith stage analog integrator is also connected with an analog adder of the next stage so as to transmit the noise of the current stage to the next stage; i=1, 2, 3. The device configures the order of the Sigma delta analog-to-digital converter according to the requirements so as to meet the application of different requirements.
Description
Technical Field
The present application relates to the field of analog integrated circuits, for example, to a Sigma delta analog to digital converter.
Background
At present, a noise-shaped ADC (i.e. Sigma-delta ADC) is a high-precision ADC structure which is widely applied, and the requirements of low speed and high precision are realized by using the over-sampling and noise shaping technology. The structure of Sigma delta ADC mainly includes two kinds of single-ring higher-order structure and cascade structure. The cascade structure has different cascade modes according to the orders, and the number of comparators is set according to the different cascade modes. The single loop higher order structure has only one comparator.
The related art discloses a modulator applied to a high-precision low-power-consumption analog-to-digital converter, which comprises a signal input end, a signal output end, a digital-to-analog converter, a first analog adder, a first analog integrator, a second analog adder, a second analog integrator, a third analog adder and a first comparator, wherein the first analog adder, the first analog integrator, the second analog adder, the second analog integrator, the third analog adder and the first comparator are sequentially connected; the input end of the first analog adder is connected with the signal input end, and the output end of the first comparator is connected with the signal output end; the signal output end is also connected with the input end of the digital-to-analog converter, and the output end of the digital-to-analog converter is respectively connected with the first analog adder and the second analog adder; the first analog integrator and the second analog integrator are switched capacitor integrators based on the dynamic amplifier, and the switched capacitor integrators comprise a second comparator for enabling the output common mode level of the dynamic amplifier to reach a set value.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
in the related art, the power consumption is reduced by the dynamic amplifier, but the application scene is single.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a Sigma delta analog-to-digital converter, which can configure the order of the analog-to-digital converter according to requirements so as to meet the application of different requirements.
In some embodiments, the Sigma delta analog to digital converter: a third-order cascade structure, each order structure comprising:
an i-th stage analog adder, an input end of which is connected with an input signal; an ith analog integrator connected with the ith analog adder to integrate the output result of the ith analog adder; an ith comparator connected with the ith analog integrator to compare the integration result of the ith analog integrator and generate an ith quantized signal; an i-th digital-to-analog converter, the input end of which is connected with the comparator, and the output end of which is connected with the other input of the i-th analog adder; converting the quantized signal of the ith comparator, transmitting the converted signal to an ith analog adder, and performing difference with the input signal;
the output end of the ith stage analog integrator is also connected with an analog adder of the next stage so as to transmit the noise of the current stage to the next stage; the output end of the ith stage comparator is connected with the input end of the analog adder of the next stage through an intermediate analog-to-digital converter.
The Sigma delta analog-to-digital converter provided by the embodiment of the disclosure can realize the following technical effects:
in the embodiment of the disclosure, a comparator is arranged in each order structure of the Sigma delta analog-to-digital converter to quantize the output result of the integrator of each order structure. Because the comparator is arranged in each stage structure, the analog-to-digital converter can be configured into a first-stage, second-stage or third-stage structure according to the requirements of performance and power consumption. Thus, the same structure of the analog-to-digital converter can meet the application of different requirements. Meanwhile, the comparator of the later stage can quantize the noise of the earlier stage so as to shift the noise of the low frequency region to the high frequency region, thereby facilitating the subsequent noise processing.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a schematic diagram of a Sigma delta analog to digital converter provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a three-stage digital integrator applied to a two-stage Sigma delta analog-to-digital converter according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a three-stage digital integrator applied to a third-order Sigma delta analog-to-digital converter according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a Sigma delta analog-to-digital converter provided by an embodiment of the present disclosure;
FIG. 5 is an enlarged schematic diagram of one of the switched capacitor analog integrators of FIG. 4;
fig. 6 is an enlarged schematic diagram of a switched capacitor analog adder of fig. 4.
Reference numerals:
11: a first stage analog adder; 12: a first stage analog integrator; 13: a first stage comparator; 14: a first digital-to-analog converter; 21: a second stage analog adder; 22: a second stage analog integrator; 23: a second stage comparator; 24: a second digital-to-analog converter; 31: a third stage analog adder; 32: a third stage analog integrator; 33: a third stage comparator; 34: a third digital-to-analog converter; 40: an intermediate digital-to-analog converter; 51: a first digital adder; 52: a second digital adder; 53: a third digital adder; 54: a fourth digital adder; 55: and a fifth digital adder.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.
In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, "connected" may be in a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
Referring to fig. 1, an embodiment of the present disclosure provides a Sigma delta analog-to-digital converter, including a third order cascade structure. The i-th order structure includes: the i-th stage analog adder has an input end connected to the input signal. And the ith analog integrator is connected with the ith analog adder to integrate the output result of the ith analog adder. And the ith comparator is connected with the ith analog integrator and used for comparing the integration result of the ith analog integrator to generate an ith quantized signal. An i-th digital-to-analog converter, the input end of which is connected with the comparator, and the output end of which is connected with the other input of the i-th analog adder; the quantized signal of the ith comparator is converted, and the converted signal is transmitted to the ith analog adder to be differenced with the input signal. The output end of the ith stage analog integrator is also connected with an analog adder of the next stage so as to transmit the noise of the current stage to the next stage; the output end of the i-th stage comparator is connected with the input end of the analog adder of the next stage through an intermediate analog-to-digital converter, and i=1, 2 and 3.
Here, the Sigma delta analog-to-digital converter includes a third order cascade structure, each of which includes an analog adder, an analog integrator, and a comparator. The adjacent step structures are connected through a digital-to-analog converter. The comparator output of the first-order structure is connected with the adder of the second-order structure through a digital-to-analog converter. Since the output signal of the comparator is a digital signal and the input signal of the analog adder is an analog signal, when the output signal of the preceding comparator is used as the input signal of the next analog adder, a digital-to-analog converter is required to convert the digital signal into the analog signal.
The first-stage analog adder 11 calculates an input signal and an output signal of the first-stage digital-to-analog converter 14 (i.e., a signal after digital-to-analog conversion of the first-stage quantized signal), the first-stage analog integrator 12 integrates the output signal V1 of the first-stage analog adder 11, and the first-stage comparator 13 compares the output signal Y1 of the first-stage analog integrator 12 to generate the first-stage quantized signal Q1. The second-stage adder 21 operates the output signal Y1 of the first-stage integrator 12 and the first-stage quantized signal Q1 (the quantized signal is converted by the intermediate digital-to-analog converter), and the quantized signal Q2 (the quantized signal is converted by the second digital-to-analog converter) output from the second-stage comparator 23. The second-stage analog integrator 22 integrates the output signal V2 of the second-stage analog adder 21; the second-stage comparator 23 compares the output result Y2 of the second-stage integrator 22 to generate a second-stage quantized signal Q2. The third-stage analog adder 31 operates the output result Y2 of the second-stage analog integrator 22 and the second-stage quantized signal Q2 (which is converted by the intermediate digital-to-analog converter), and the quantized signal Q3 (which is converted by the third digital-to-analog converter) output from the third-stage comparator 33; the third-stage analog integrator 32 integrates the output result V3 of the third-stage analog adder 31; the third-stage comparator 33 compares the output result Y3 of the third-stage integrator 32, and generates a third-stage quantized signal Q3.
In the above process, the first-stage analog integrator 12 shapes the quantization noise, and the output signal V1 of the first-stage analog integrator 12 is transmitted to the second-stage analog adder 21 while being transmitted to the first-stage comparator 13. The second-stage analog integrator 22 integrates noise output from the first-stage analog integrator 12. Similarly, the third-stage analog integrator 32 again processes the noise output from the second-stage analog integrator 22. Thus, the low-frequency noise is continuously moved to the high-frequency area, and the noise in the high-frequency area is filtered by the rear-stage circuit, so that the signal-to-noise ratio is improved.
Meanwhile, each stage of structure is provided with a comparator, and the output result of the integrator can be quantized. The analog-to-digital converter can be configured according to performance and power consumption requirements. Thus, the analog-to-digital converter in the embodiment of the disclosure can be used as a first-order structure, a second-order structure or a third-order structure. It will be appreciated that the more orders, the higher the power consumption of the Sigma delta analog to digital converter. The power consumption is low if the order is small.
With the Sigma delta analog-to-digital converter provided by the embodiment of the present disclosure, a comparator is disposed in each order structure of the Sigma delta analog-to-digital converter, so as to quantize the output result of the integrator of each order structure. Because the comparator is arranged in each stage structure, the analog-to-digital converter can be configured into a first-stage, second-stage or third-stage structure according to the requirements of performance and power consumption. Thus, the same structure of the analog-to-digital converter can meet the application of different requirements. Meanwhile, the comparator of the later stage can quantize the noise of the earlier stage so as to shift the noise of the low frequency region to the high frequency region, thereby facilitating the subsequent noise processing.
Optionally, the input of the first stage analog integrator 12 is also connected to a random noise input signal E R (Z)。
Here, random noise is input to the first stage analog integrator. For analog signals, the interference power is concentrated at one frequency point to generate single-tone interference. Therefore, random noise is injected into the integrator to avoid the concentration of noise at one frequency point. Thereby eliminating the single tone interference of the analog-to-digital converter.
Optionally, the analog-to-digital converter of the first-order structure, the second-order structure or the third-order structure is configured by turning on the integrator and the comparator of the corresponding stage in the third-order cascade structure.
When the first-order structure is configured, an integrator and a comparator of the first stage are turned on; when the second-order cascade structure is configured, an integrator and a comparator of the first stage and the second stage are opened; when the third-order cascade structure is configured, the integrators and comparators of the first stage, the second stage and the third stage are turned on.
Here, the configuration of the analog-to-digital converter of the different order structure is completed by the switching control of the integrator and the comparator. The input of the first stage analog adder serves as the input of the entire analog-to-digital converter, so that configuration is started from the first stage when the configuration is performed. Specifically, when the first-order structure is configured, the analog adder, the analog integrator, the comparator, and the digital-to-analog converter of the first stage operate. The second stage structure and the third stage structure are not operated (i.e. the integrator, comparator controlling the second stage and the third stage are turned off). Similarly, when the second cascade structure is configured, the analog adder, analog integrator, comparator, and digital-to-analog converter of the first stage and the second stage, and the intermediate digital-to-analog converter between the first stage and the second stage operate. The tertiary structure does not work. When the third-order cascade structure is configured, all devices work.
It will be appreciated that turning off the integrator and comparator of the corresponding stage may be done by enabling the control. Or the on-off of the power supply of the integrator and the comparator is controlled by a switch, and the integrator and the comparator are closed. If the first-order structure or the second-order structure is configured, the later-order device is not closed, and the quantized signal is transmitted to the later-order structure, so that energy consumption is wasted.
As shown in connection with fig. 2 and 3, the analog-to-digital converter further comprises: a three-stage digital integrator. Wherein, three input ends of the three-stage digital integrator are respectively connected with the output end of the first-stage comparator 13, the output end of the second-stage comparator 23 and the output end of the third-stage comparator 33; to noise-cancel the first-stage quantized signal and the second-stage quantized signal, or the first-stage quantized signal, the second-stage quantized signal, and the third-stage quantized signal.
Here, the three-stage digital integrator corresponds to the aforementioned third-order junction structure. When the Sigma delta analog-to-digital converter is configured in a second or third order configuration, the post integrator integrates (i.e., shapes) the noise of the pre integrator. Therefore, the noise in the low frequency region is moved to the high frequency region, and when the second-order structure or the third-order structure is configured, the noise in the high frequency region is eliminated by using the three-stage digital integrator.
Specifically, for second order structures. And inputting the first quantized signal output by the first-stage comparator and the second quantized signal output by the second-stage comparator into two input ends of the three-stage digital integrator to perform logic operation so as to eliminate noise of the first stage. Similarly, for the third-order structure, the first quantized signal output by the first-stage comparator, the second quantized signal output by the second-stage comparator, and the third input terminal of the third-stage input three-stage digital integrator are subjected to logic operation to eliminate noise of the second stage.
Optionally, the three-stage digital integrator comprises five digital adders. The first digital adder 51 has a first input connected to the first-stage quantized signal delayed by a first time period. A second digital adder 52 having a first input connected to the second-stage quantized signal delayed by the second time period and a second input connected to the second-stage quantized signal delayed by the first time period; the output terminal is connected with the second input terminal of the first digital adder. And a third digital adder 53, the first input terminal of which is connected to the third-stage quantized signal, and the second input terminal of which is connected to the third-stage quantized signal delayed by the second period. And a fourth digital adder 54, the first input terminal of which is connected to the output signal of the third digital adder, and the second input terminal of which is connected to the output signal of the third digital adder after being delayed for a second period of time. And a fifth digital adder 55, the first input terminal of which is connected to the output signal of the first digital adder, the first input terminal of which is connected to the output signal of the fourth digital adder, and the output terminal of which outputs the noise-eliminated signal.
Wherein the fifth digital adder sums the signal at the first input terminal and the signal at the second input terminal; the first digital adder, the second digital adder, the third digital adder and the fourth digital adder each perform a difference between the signal at the first output terminal and the signal at the second input terminal.
Fig. 2 is a simplified structure of a digital integrator that performs noise cancellation on a second order structure. With reference to fig. 1, a first quantized signal Q of an analog-to-digital converter in a first order structure can be obtained 1 (Z)：
Wherein X (Z) is an input signal, Z -1 Representing a delay of one clock cycle, E 1 (Z) is the output noise of the first stage. After finishing, the formula (2) can be obtained:
Q 1 (Z)＝Z -1 *X(Z)+(1-Z -1 )*E 1 (Z) (2)
when the two-stage structure is adopted, the first stage output noise is output to the first stageSecond quantized signal Q of second-order analog-to-digital converter 2 (Z)：
First and second stages are cascaded to cancel noise of the first stage, i.e., equations (2) and (3) cancel E 1 (Z) the obtainable:
Q 1 (Z)*Z -1 -Q 2 (Z)*(1-Z -1 )＝Z -2 *X(Z)-E 2 (Z)(1-Z -1 ) 2 (4)
it can be seen that the output noise E of the first stage 1 (Z) is eliminated.
Optionally, in the case of noise cancellation of the first-stage quantized signal and the second-stage quantized signal, the first duration is one clock cycle and the second duration is one clock cycle. Wherein the clock period is the clock period of the analog-to-digital converter.
It will be appreciated that the noise cancellation is performed on the same signal, so that in the second order configuration, the first quantized signal is delayed by one clock cycle to obtain the same signal as the second quantized signal. And the signal at the first input of the second digital adder does not need to be delayed; meanwhile, the second quantized signal is subtracted from the signal delayed by one clock cycle to obtain the integration of the second quantized signal in the digital domain. And then the noise-eliminated signal is obtained after the operation of the first digital adder.
Referring to fig. 1 and 3, when the third order structure is adopted, the third quantized signal Q of the analog-to-digital converter 3 (Z)：
The first, second and third stage structure cascades to cancel second stage noise, i.e., equations (4) and (5) cancel E 2 (Z)。
Q 1 (Z)*Z -2 -Q 2 (Z)*(1-Z -1 )*Z -1 +Q 3 (Z)*(1-Z -1 ) 2 ＝Z -3 *X(Z)+E 3 (Z)*(1-Z -1 ) 3 (6)
It can be seen that the output noise E of the second stage 2 (Z) is eliminated.
Optionally, in the case of noise cancellation of the first-stage quantized signal, the second-stage quantized signal, and the third-stage quantized signal, the first duration is two clock cycles, and the second duration is one clock cycle. Wherein the clock period is the clock period of the analog-to-digital converter.
Here, the principle of the delay time length is as described above. In the third order structure, the first quantized signal needs to be delayed by two clock cycles, the second quantized signal needs to be delayed by one clock cycle, and the first input signal of the third digital adder does not need to be delayed. Thus, the three quantized signals are signals at the same time.
Meanwhile, the second quantized signal delayed by one clock cycle needs to be subtracted from the signal delayed by one clock cycle to obtain the integration of the second quantized signal in the digital domain. Likewise, the third quantized signal of the third digital adder is subtracted from the delayed third quantized signal; and subtracting the subtracted signal from the subtracted signal delayed by one clock period to finally obtain twice integration of the third quantized signal in the digital domain. To eliminate the output noise of the second stage.
Optionally, the switched capacitor analog integrator comprises: full differential operational amplifier, first sampling capacitor C S1 A second sampling capacitor C S2 First integrating capacitor C c1 And a second integrating capacitor C c2 . Wherein, the first sampling capacitor C S1 One end is connected with the first switch phi 11 Is connected with the first input signal end and also passes through the second switch phi 21 One end of the common mode input voltage Vcm is connected; the other end passes through a first two-way switch phi 12 Connected to the first input of the fully differential operational amplifier and also via a second switch phi 22 And the other end of the common mode input voltage is connected with the other end of the common mode input voltage. Second sampling capacitor C S2 One end passes through a thirdA switch phi 31 Is connected with the first input signal end and also passes through a fourth switch phi 41 One end of the common mode input voltage is connected with the output end of the common mode input voltage; the other end passes through a third second switch phi 32 Connected to the second input of the fully differential operational amplifier and further via a fourth switch phi 42 And the other end of the common mode input voltage is connected with the other end of the common mode input voltage. First integrating capacitor C c1 The first input end and the first output end of the full differential operational amplifier are connected in a bridging mode. Second integrating capacitor C c2 And the second input end and the second output end of the full differential operational amplifier are connected in a bridging mode.
Here, a first one-to-one switch phi 11 Second switch phi 22 A third switch phi 31 And a fourth second switch phi 42 Controlled by a first logic signal of the clock, such as a high level signal of the clock. First two-switch phi 12 A second switch phi 21 Third switch phi 32 And a fourth switch phi 41 Controlled by a second logic signal of the clock, such as a low level signal of the clock. I.e. two sets of switches are controlled by two phase clock signals, one of which controls sampling and the other of which controls integration. During sampling, the input signal is stored on the first sampling capacitor and the second sampling capacitor. Meanwhile, the output signal at the previous moment is stored in the first integrating capacitor and the second integrating capacitor. And during integration, the charge transfer of the first sampling capacitor and the second sampling capacitor reaches the corresponding integration band content, so that integration is realized.
Optionally, the switched capacitor adder includes: first capacitor C 1 And a second capacitor C 2 . First capacitor C 1 Through a fifth set of switches (phi) 51 And phi is 52 ) Connecting two ends of a reference voltage signal; the other end passes through a sixth switch phi 61 One end of the switched capacitor analog integrator is connected, and two ends of the common mode input voltage pass through a seventh group of switches (phi 71 And phi is 72 ) And the two ends of the first capacitor are respectively connected. Second capacitor C 2 Through an eighth group of switches (phi) 81 And phi is 82 ) Connecting two ends of a reference voltage signal; the other end passes through a sixth switch phi 62 Connecting switch capacitorThe other end of the analog integrator and the two ends of the common mode input voltage pass through a ninth group of switches (phi 91 And phi is 92 ) And two ends of the second capacitor are respectively connected.
Here, the fifth group of switches includes a fifth first switch and a fifth second switch, and the seventh group of switches includes a seventh first switch and a seventh second switch. Wherein the fifth group of switches, the seventh second switch are controlled by one phase clock (e.g. high level), and the sixth switch and the seventh switch are controlled by the other phase clock (e.g. low level). Likewise, the switch of the second capacitor is as described above for the switch of the first capacitor. The first capacitor and the second capacitor are respectively connected with two input ends of the switch capacitor analog integrator through a sixth first switch and a sixth second switch.
In addition, the analog adder and the analog integrator of each-stage structure have the same structure, and the two-phase clock signals are identical and synchronous.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A Sigma delta analog to digital converter comprising a third order cascade structure, the ith order structure comprising:
an i-th stage analog adder, an input end of which is connected with an input signal;
an ith analog integrator connected with the ith analog adder to integrate the output result of the ith analog adder;
an ith comparator connected with the ith analog integrator to compare the integration result of the ith analog integrator and generate an ith quantized signal;
an i-th digital-to-analog converter, the input end of which is connected with the comparator, and the output end of which is connected with the other input end of the i-th analog adder; converting the quantized signal of the ith comparator, transmitting the converted signal to an ith analog adder, and performing difference with the input signal;
the output end of the ith stage analog integrator is also connected with an analog adder of the next stage so as to transmit the noise of the current stage to the next stage; the output end of the i-th stage comparator is connected with the input end of the analog adder of the next stage through an intermediate analog-to-digital converter, and i=1, 2 and 3.
2. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,
the input of the first stage analog integrator is also connected to a random noise input signal.
3. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,
configuring an analog-to-digital converter of a first-order structure, a second-order cascade structure or a third-order cascade structure by opening an integrator and a comparator of a corresponding stage in the third-order cascade structure;
when the first-order structure is configured, an integrator and a comparator of the first stage are turned on; when the two-stage cascade structure is configured, an integrator and a comparator of a first stage and a second stage are opened; when the third-order cascade structure is configured, the integrators and comparators of the first stage, the second stage and the third stage are turned on.
4. An analog-to-digital converter according to any one of claims 1 to 3, characterized in that the analog-to-digital converter further comprises:
three input ends of the three-stage digital integrator are respectively connected with the output end of the first-stage comparator, the output end of the second-stage comparator and the output end of the third-stage comparator; to noise-cancel the first-stage quantized signal and the second-stage quantized signal, or the first-stage quantized signal, the second-stage quantized signal, and the third-stage quantized signal.
5. The analog-to-digital converter of claim 4, wherein the three-stage digital integrator comprises:
the first input end of the first digital adder is connected with a first-stage quantized signal delayed by a first time length;
the first input end of the second digital adder is connected with the second-stage quantized signal delayed by the second time length, and the second input end of the second digital adder is connected with the second-stage quantized signal delayed by the first time length; the output end is connected with the second input end of the first digital adder;
the first input end of the third digital adder is connected with the third-stage quantized signal, and the second input end of the third digital adder is connected with the third-stage quantized signal delayed for a second duration;
the first input end of the fourth digital adder is connected with the output signal of the third digital adder, and the second input end of the fourth digital adder is connected with the output signal of the third digital adder after delaying the second time length;
and the first input end of the fifth digital adder is connected with the output signal of the first digital adder, the second input end of the fifth digital adder is connected with the output signal of the fourth digital adder, and the output end of the fifth digital adder outputs the signal after noise elimination.
6. The analog-to-digital converter of claim 5, wherein the analog-to-digital converter comprises,
under the condition of carrying out noise elimination on the first-stage quantized signal and the second-stage quantized signal, the first duration is one clock cycle, and the second duration is one clock cycle;
wherein the clock period is the clock period of the analog-to-digital converter.
7. The analog-to-digital converter of claim 5, wherein the analog-to-digital converter comprises,
under the condition of carrying out noise elimination on the first-stage quantized signal, the second-stage quantized signal and the third-stage quantized signal, the first duration is two clock cycles, and the second duration is one clock cycle;
wherein the clock period is the clock period of the analog-to-digital converter.
8. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises,
the ith stage analog integrator is a switched capacitor analog integrator;
the i-th stage analog adder is a switched capacitor adder.
9. The analog-to-digital converter of claim 8, wherein the switched-capacitor analog integrator comprises:
a fully differential operational amplifier;
one end of the first sampling capacitor is connected with the first input signal end through a first one-to-one switch and is also connected with one end of the common-mode input voltage through a second one-to-one switch; the other end is connected with the first input end of the fully differential operational amplifier through a first two-way switch and is also connected with the other end of the common-mode input voltage through a second two-way switch;
one end of the second sampling capacitor is connected with the first input signal end through a third switch and is also connected with one end of the common-mode input voltage through a fourth switch; the other end is connected with the second input end of the fully differential operational amplifier through a third second switch, and is also connected with the other end of the common-mode input voltage through a fourth second switch;
the first integrating capacitor is connected across the first input end and the first output end of the fully-differential operational amplifier;
and the second integrating capacitor is connected across the second input end and the second output end of the fully-differential operational amplifier.
10. The analog-to-digital converter of claim 8, wherein the switched-capacitor adder comprises:
one end of the first capacitor is connected with two ends of the reference voltage signal through a fifth group of switches; the other end is connected with one end of the switched capacitor analog integrator through a sixth switch, and two ends of the common-mode input voltage are respectively connected with two ends of the first capacitor through a seventh group of switches;
one end of the second capacitor is connected with two ends of the reference voltage signal through an eighth group of switches; the other end is connected with the other end of the switched capacitor analog integrator through a sixth switch, and two ends of the common-mode input voltage are respectively connected with two ends of the second capacitor through a ninth group of switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311863221.7A CN117792401A (en) | 2023-12-29 | 2023-12-29 | Sigma delta analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311863221.7A CN117792401A (en) | 2023-12-29 | 2023-12-29 | Sigma delta analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117792401A true CN117792401A (en) | 2024-03-29 |
Family
ID=90390838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311863221.7A Pending CN117792401A (en) | 2023-12-29 | 2023-12-29 | Sigma delta analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117792401A (en) |
-
2023
- 2023-12-29 CN CN202311863221.7A patent/CN117792401A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4920544A (en) | Delta-sigma modulator | |
| US7167119B1 (en) | Delta-sigma modulators with double sampling input networks and systems using the same | |
| US8217815B2 (en) | Sigma-delta modulator with shared operational amplifier and associated method | |
| EP1495546B1 (en) | Delta sigma modulator | |
| EP1784918B1 (en) | Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter | |
| JPH04225624A (en) | Sigma-delta analog-digital converter | |
| US9698805B1 (en) | Electrical noise reduction in an analog-to-digital converter | |
| CN106209104A (en) | Analog-digital converter | |
| US6184811B1 (en) | Double-sampled ΣΔ modulator of second order having a semi-bilinear architecture | |
| US6147631A (en) | Input sampling structure for delta-sigma modulator | |
| WO2003105348A1 (en) | Delta - sigma modulators with improved noise performance | |
| US7916054B2 (en) | K-delta-1-sigma modulator | |
| US9900023B1 (en) | Multi-stage delta-sigma pipelined successive approximation register analog-to-digital converter | |
| JPH08125541A (en) | Delta sigma modulator | |
| US9641192B1 (en) | Methods and apparatus for a delta sigma ADC with parallel-connected integrators | |
| US8643524B1 (en) | Feed-forward analog-to-digital converter (ADC) with a reduced number of amplifiers and feed-forward signal paths | |
| US8344796B2 (en) | Switched capacitor circuit | |
| CN110086470A (en) | The control method of analog-digital converter and analog-digital converter | |
| Brewer et al. | A 100dB SNR 2.5 MS/s output data rate/spl Delta//spl Sigma/ADC | |
| US9692444B1 (en) | Neutralizing voltage kickback in a switched capacitor based data converter | |
| JP4171222B2 (en) | Multi-input ΔΣ modulation circuit | |
| CN117792401A (en) | Sigma delta analog-to-digital converter | |
| CN111988037A (en) | Sigma-Delta modulator with capacitor sharing structure | |
| CN115801003A (en) | Multi-step analog-to-digital converter and implementation method thereof | |
| US7283078B2 (en) | Digital-to-analog converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |